Abstract: Various systems and methods for creating, storing, structuring, displaying, enhancing, and/or referencing publications and related content in an online user network are described. In some embodiments, document contents are stored in the form of individually addressable document elements, which can be displayed selectively based on display criteria received from a user.

Abstract: A memory system may include a memory device including a plurality of a super blocks, a list, and a controller suitable for updating the list with block information regarding one of the super blocks when a super block is opened or closed; and at power up, reading the block information from the list and rebuilding a logical block addressing (LBA) table based on the block information.

Abstract: The present application is directed to employing prefetch to reduce write overhead. A device may comprise a processor and a cache memory. The processor may determine if data to be written to the cache memory comprises multiple cache lines wherein at least one of the cache lines will be fully written. If the data comprises at least one cache line to be fully written, then the processor may perform a “prefetch” wherein the processor may write dummy data to sections of the cache memory corresponding to the data to be written in full cache lines. The processor may then write actual data to the sections containing the dummy data without the processor first having to verify ownership of the sections. Any remaining data that will not be written in full cache lines may then be written to the cache memory utilizing a standard write transaction.

Abstract: An I/O control circuit, includes a mode setting unit configured to generate a first mode signal, a second mode signal, a third mode signal, and a fourth mode signal in accordance with one of a plurality of I/O option modes, a first control signal generation unit configured to generate a first mode determination signal and a first control signal enable signal in response to the first I/O option signal and the first mode signal, and a second control signal generation unit configured to generate a second control signal enable signal, a third control signal enable signal, and a fourth control signal enable signal in response to a second I/O option signal, the first mode determination signal, the second mode signal, the third mode signal, and the fourth mode signal.

Abstract: Integrated circuits that include memory interface and controller circuitry for communicating with external memory are provided. The memory interface and controller circuitry may include a user logic interface, a memory controller, and a physical layer input-output interface. The user logic interface may be operated in a first clock domain. The memory controller may be operated in a second clock domain. The physical layer interface may be operated in a third clock domain that is an integer multiple of the second clock domain. The user logic interface may include only user-dependent blocks. The physical layer interface may include memory protocol agnostic blocks and/or memory protocol specific blocks. The memory controller may include both memory protocol agnostic blocks and memory protocol dependent blocks. The memory controller may include one or more color pipelines for scheduling memory requests in a parallel arbitration scheme.

Abstract: Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate requests that would occur if the memory access requests were to be executed in the received order are detected, and the received order of the memory access requests is rearranged to avoid or minimize the conflicts or delays and to optimize the flow of data to and from the memory data bus. The memory access requests are executed in the reordered sequence, while the originally received order of the requests is tracked. After execution, data read from the memory device by the execution of the read-type memory access requests are transferred to the respective requestors in the order in which the read requests were originally received.

Abstract: Processor context save latency is reduced by only restoring context registers with saved state that differs from the reset value of registers. A system agent monitors access to the design blocks and sets a dirty bit to indicate which design block has registers that have changed since the last context save. During a context save operation, the system agent bypasses design blocks that have not had context changes since the latest context save operation. During a context restore operation the system agent does not restore the context registers with saved context values that are equal to the reset value of the context register.

Abstract: Forensic data acquisition apparatus and method. The forensic data acquisition apparatus according to an embodiment includes a command analysis unit for activating a boot loader and a Universal Serial Bus (USB) module of a smart device and analyzing a format of a flash memory read command based on results of analysis of the boot loader, a partition information analysis unit for analyzing partition information of flash memory in compliance with the flash memory read command, and a data acquisition unit for generating a dump image by dumping data stored in the flash memory based on the flash memory read command and the partition information, and for acquiring forensic data based on the dump image.

Abstract: A memory system comprises a memory device coupled to a memory controller, the memory controller for receiving one or more memory requests from one or more core devices via an interconnect bus. The memory controller tracks utilization of the interconnect bus by tracking a selection of the one or more memory requests with fetched data from the one or more memory devices and waiting for scheduling to return on the interconnect bus during a time window. The memory controller, responsive to detecting utilization of the interconnect bus during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of the fetched data to be returned with at least one read request from among the selection of one or more memory requests, the reduced data size selected from among at least two read data size options for the at least one read request of a maximum read data size and the reduced read data size that is less than the maximum read data size.

Abstract: A method for transferring memory pages to a first and a second page repository identifies pages in a memory sharing operation for transfer to a first page repository and pages in a memory migration operation for transfer to a second page repository. Pages in the memory migration operation may be prepared for transfer prior to transfer of the pages in the memory sharing operation. Transferring pages in the migration operation may remove the need to transfer pages in the memory sharing operation.

Abstract: Operations associated with a memory and operations associated with one or more functional units may be received. A dependency between the operations associated with the memory and the operations associated with one or more of the functional units may be determined. A first ordering may be created for the operations associated with the memory. Furthermore, a second ordering may be created for the operations associated with one or more of the functional units based on the determined dependency and the first operating of the operations associated with the memory.

Abstract: Embodiments of the present invention provide systems, methods, and computer program products for managing computing devices to handle an input/output (I/O) request. In one embodiment, the I/O request may eligible for performance throttling based, at least in part, on the associated importance level for performing the received I/O request and one or more characteristics of the received I/O request. Embodiments of the present invention provide systems, methods, and computer program products for throttling the I/O request and transmitting the I/O request to a storage controller.

Abstract: An apparatus includes a register memory and circuitry. The register memory is configured to hold a minimal value specified for a performance measure of a given type of memory access commands, whose actual performance measures vary among memory devices. The circuitry is configured to receive a memory access command of the given type, to execute the received memory access command in one or more memory devices, and to acknowledge the memory access command not before reaching the minimal value stored in the register memory.

Abstract: A semiconductor system includes a controller and a semiconductor device. The controller generates command signals, a composite control signal, and data signals. The semiconductor device generates a first mode signal and a second mode signal according to the command signals. The semiconductor device includes a write control circuit suitable for receiving the composite control signal and the data signals to determine an execution/non-execution of a data masking operation and a data bus inversion (DBI) operation when a write operation or a masking write operation is performed according to the first and second mode signals.

Abstract: A processor includes a plurality of storage modules and an arbiter, where the storage modules are arranged for storing a plurality of read/write commands, respectively, and the read/write commands are arranged to read/write a memory external to the processor; and the arbiter is coupled to the storage modules, and is arranged to receive the read/write commands from the storage modules, and arrange a sequence of the read/write commands for transmitting to a memory controller.

Abstract: A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.

Abstract: Embodiments of the present invention disclose a method and apparatus of cache management for a non-volatile storage device. The method embodiment includes: determining a size relationship between a capacity sum of a clean page subpool and a dirty page subpool and a cache capacity; determining, when the capacity sum is equal to the cache capacity, whether identification information of a to-be-accessed page is in a history list of clean pages or a history list of dirty pages; and when it is determined that the identification information of the to-be-accessed page is in the history list of clean pages, adding a first adjustment value to a clean page subpool capacity threshold; and when the identification information of the to-be-accessed page is in the history list of dirty pages, subtracting a second adjustment value from the clean page subpool capacity threshold.

Abstract: When a process is swapped out of memory, a record of the sharable memory pages of the process is maintained. The sharable memory pages can then be repurposed. When the process is subsequently swapped back into memory, concurrently with the process running the sharable memory pages of the process are prefetched. If during this prefetching the process requests a memory page that is not currently in physical memory, a high priority I/O request is issued for that memory page. The high priority I/O request is placed at the front of an I/O queue, so the high priority I/O request is processed before the pending prefetch requests.

Abstract: Aspects of the subject disclosure are directed towards increasing a community of interest group users of an interest group, e.g., a network site having a feed of posts generally related to a particular topic. Many newly created interest groups do not have enough content to keep users interested and attract new users. The technology described herein automatically obtains content that backfills such an interest group with additional related content. The backfilled content may be found by keywords search and/or by crawling general public data, data from specific sites, historical conversation data, and/or more widely scoped data. Also described is creating a new interest group and seeding the group with content based upon backfilling technology.

Abstract: A data-processing apparatus includes: a plurality of processing blocks which is connected to a common bus; a memory which includes an address space having a plurality of banks; and a common bus arbitrating section which arbitrates an access request to access the memory, and controls data delivery through the common bus that receives the access request and is provided between the plurality of processing blocks and the memory. At least one processing block among the plural processing blocks is an exchange-processing block that performs exchange of an access order to access the banks in the memory when the communication of the data is performed between the memory and the processing block through the common bus. The exchange-processing block includes a data transfer control device that performs the exchange of the access order to access the banks by controlling the order of the data.

Abstract: Embodiments of the present invention provide systems, methods, and computer program products for managing computing devices to handle an input/output (I/O) request. In one embodiment, the I/O request may eligible for performance throttling based, at least in part, on the associated importance level for performing the received I/O request and one or more characteristics of the received I/O request. Embodiments of the present invention provide systems, methods, and computer program products for throttling the I/O request and transmitting the I/O request to a storage controller.

Abstract: A memory device and a method of operating the memory device are provided. The memory device comprises a plurality of storage units and access control circuitry. The access control is configured to receive an access request and in response to the access request to initiate an access procedure in each of the plurality of storage units. The access control circuitry is configured to receive an access kill signal after the access procedure has been initiated and, in response to the access kill signal, to initiate an access suppression to suppress the access procedure in at least one of the plurality of storage units. Hence, by initiating the access procedures in all storage units in response to the access request, e.g.

Abstract: A method for deduplication rehydration is described. In one embodiment, a request to restore a backup image is received. The backup image is stored in a deduplication system. The backup image includes a plurality of data segments. The method includes determining locality information for at least one of the plurality of data segments. The locality information includes information regarding a location of the at least one data segment in relation to each other data segment of the plurality of data segments in the backup image. The method includes obtaining an identifier of each data container storing the plurality of data segments of the backup image, determining a degree to which the plurality of data segments of the backup image are processed by prefetching, and prefetching one or more of the plurality of target data segments from a data container based at least in part on a predetermined effectiveness threshold.

Abstract: Technologies are described for implementing a migration mechanism in a storage system containing multiple tiers of storage with each tier having different cost and performance parameters. Access statistics can be collected for each territory, or storage entity, within the storage system. Data that is accessed more frequently can be migrated toward higher performance storage tiers while data that is accessed less frequently can be migrated towards lower performance storage tiers. The placement of data may be governed first by the promotion of territories with higher access frequency to higher tiers. Secondly, data migration may be governed by demoting territories to lower tiers to create room for the promotion of more eligible territories from the next lower tier. In instances where space is not available on the next lower tier, further demotion may take place to an even lower tier in order to make space for the first demotion.

Abstract: The present application is directed to systems and methods for managing data in a device for hibernation states. In one implementation, the device includes an interface and a processor. The interface is coupled with a first memory and a second memory. The processor is in communication with the first and second memories via the interface. The processor is configured to read first data from the first memory, generate image data of the data stored in the first memory based on the first data, and write to the second memory prior to the device entering an initial hibernation state the image data of the data stored in the first memory. The processor is further configured to, after the device awakes from the initial hibernation state, read the image data from the second memory, reconstruct the first data based on the image data, and write the first data to the first memory.

Abstract: An I/O control circuit, includes a mode setting unit configured to generate a first mode signal, a second mode signal, a third mode signal, and a fourth mode signal in accordance with one of a plurality of I/O option modes, a first control signal generation unit configured to generate a first mode determination signal and a first control signal enable signal in response to the first I/O option signal and the first mode signal, and a second control signal generation unit configured to generate a second control signal enable signal, a third control signal enable signal, and a fourth control signal enable signal in response to a second I/O option signal, the first mode determination signal, the second mode signal, the third mode signal, and the fourth mode signal.

Abstract: An apparatus includes a shared cache memory and a controller. The shared cache memory is configured to be divided into sectors by assigning one or more ways to each sector in accordance with a reusability level of data. The controller changes a sector division ratio indicating a ratio between way counts of the divided sectors of the shared cache memory, where the way count is a number of ways assigned to each sector. When first and second jobs are being executed in parallel, in response to a designation of a program of the second job, the controller calculates the sector division ratio, based on data access amount including a size and an access count of data accessed by the first and second jobs and a volume of the shared cache memory, and changes the sector division ratio of the shared cache memory to the calculated sector division ratio.

Abstract: A computer-implemented method for identifying access rate boundaries of workloads may include (1) tracking the number of times each region of data within a plurality of regions of data is accessed during a period of time, (2) creating an ordered list of each region of data from the plurality of regions of data, (3) calculating one or more drops in access rates between two or more regions of data in the ordered list, (4) determining that a calculated access-rate drop from a first region of data to a second region of data exceeds a predefined threshold, and (5) calculating a boundary access rate for a workload of data. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Systems, apparatuses, and methods for enabling the efficient configuration of a User Interface (UI) for a user so that the configured UI represents the UI elements used most commonly by the user. In one embodiment, the invention may be used by the operator and users of a multi-tenant business data processing platform to permit each user to be associated with a specific configuration of UI elements and capabilities based on that user's typical or most common usage patterns. Further, in one embodiment, information or data that represents the UI configuration associated with a user may be encoded and provided to the multi-tenant business data processing platform in an efficient manner to enable the platform to present the desired UI to that user.

Abstract: Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the number of transfers meeting a threshold and communicating the transfers via the bypass path to the grantor based on the request, the interconnect network granting control of the grantor in response to the request. The method also includes the interconnect network requesting control of the grantor based on an event and communicating delayed transfers via the interconnect network from other requestors, the delayed transfers being delayed due to the grantor being previously controlled by the requestor, the communicating based on the control of the grantor being changed back to the interconnect network.

Abstract: Methods for controlling an interface operation, the method including stopping an operation being processed in a storage device and switching the state of the storage device to a first state, when a condition for switching the state of the storage device to an idle state occurs in a command processing process according to a communication protocol; performing an operation of deleting information from a previous command stored in hardware of the storage device when the state of the storage device is switched to the first state; and switching the state of the storage device to the idle state after the operation of deleting the information on the previous command is completed, wherein in the first state, the storage device cannot be switched to the first state before the information from the previous command is deleted.

Abstract: A processing unit of a data processing system having a shared memory system executes a memory transaction including a transactional store instruction that causes a processing unit of the data processing system to make a conditional update to a target memory block of the shared memory system conditioned on successful commitment of the memory transaction. The memory transaction further includes a transaction check instruction. In response to executing the transaction check instruction, the processing unit determines, prior to conclusion of the memory transaction, whether the target memory block of the shared memory system was modified after the conditional update caused by execution of the transactional store instruction. In response to determining that the target memory block has been modified, a condition register within the processing unit is set to indicate a conflict for the memory transaction.

Abstract: A processing unit of a data processing system having a shared memory system executes a memory transaction including a transactional store instruction that causes a processing unit of the data processing system to make a conditional update to a target memory block of the shared memory system conditioned on successful commitment of the memory transaction. The memory transaction further includes a transaction check instruction. In response to executing the transaction check instruction, the processing unit determines, prior to conclusion of the memory transaction, whether the target memory block of the shared memory system was modified after the conditional update caused by execution of the transactional store instruction. In response to determining that the target memory block has been modified, a condition register within the processing unit is set to indicate a conflict for the memory transaction.

Abstract: The present invention discloses a method of arbitrating among a plurality of channels to access a resource, comprising the steps of: providing each channel an address back-to-back counter; assigning each address back-to-back counter an initial value and a pre-defined threshold, wherein the address back-to-back counter is updated according to the activities of back-to-back access to the resource by the channel; and providing each channel a contiguous window setting to define a number of contiguous times for the channel to access the resource; wherein a channel being served is to be served for contiguous times defined by the contiguous window setting of the channel if the address back-to-back counter value of the channel is higher than the pre-defined threshold of the channel.

Abstract: A method and system for optimizing network I/O throughput is disclosed. In one embodiment, a method for optimizing an input/output (I/O) throughput for a storage network comprises measuring a service time for a storage device of the storage network in completing an I/O request serviced by a storage driver. The method also comprises determining a status of an I/O performance between the storage driver and the storage device by comparing the service time with an expected service time for the storage device in completing the I/O request, where the expected service time is calculated based on a type of the storage device and a size of the I/O request. The method further comprises adjusting a maximum queue depth associated with the storage device based on the status of the I/O performance.

Abstract: A system, method, and computer program product are provided for reducing a rate of data transfer to at least a portion of memory. In operation, a rate of degradation of at least a portion of memory associated with a drive is determined. Furthermore, a rate of data transfer to the at least a portion of the memory is reduced, based on the determined rate of degradation.

Abstract: Fetching a cache line into a plurality of caches of a multilevel cache system. The multilevel cache system includes at least a first cache, a second cache on a next higher level and a memory, the first cache being arranged to hold a subset of information of the second cache, the second cache being arranged to hold a subset of information of a next higher level cache or memory if no higher level cache exists. A fetch request is sent from one cache to the next cache in the multilevel cache system. The cache line is fetched in a particular state into one of the caches, and in another state into at least one of the other caches.

Abstract: A method for accelerating execution of read operations in a distributed interconnect peripheral bus is provided. The method comprises generating a first number of speculative read requests addressed to an address space related to a last read request served on the bus; sending the speculative read requests to a root component connected to the bus; receiving a second number of read completion messages from the root component of the bus; and sending a read completion message out of the received read completion messages component to the endpoint component only if the read completion message is respective of a real read request or a valid speculative read request out of the speculative read requests, wherein a real read request is issued by the endpoint component.

Abstract: An apparatus includes a memory and storage circuitry. The storage circuitry is configured to receive at least one request causing execution of a sequence of memory commands in the memory, to identify that, although a first memory command appears in the sequence before a second memory command, the execution of the second memory command would improve a performance of the execution of the first memory command, and to execute the second memory command and then to execute the first memory command with the improved execution performance.

Abstract: Exemplary method, system, and computer program product embodiments for priority based depopulation of ranks in a computing storage environment are provided. In one embodiment, by way of example only, multiple ranks selected for depopulation are prioritized. The highest priority rank of the multiple ranks is depopulated to a target rank. Additional system and computer program product embodiments are disclosed and provide related advantages.

Abstract: A semiconductor device comprises: a read queue configured to store one or more read requests to a semiconductor memory device; a write queue configured to store one or more write requests to the semiconductor memory device; and a dispatch block configured to determine a scheduling order of the one or more read requests and the one or more write requests and switch to the read queue or to the write queue if a request exists in a Row Hit state in the read queue or in the write queue.

Abstract: A storage device being one of a plurality of storage devices storing data includes a memory and a processor coupled to the memory. The processor executes determining, when having received a new request and a new priority information during a preparation for an execution of another update processing, whether a new priority indicated by the new priority information is higher than a priority of the update processing in the preparation. The process including canceling the update processing in the preparation when having determines at the determining that the new priority is higher than the priority of the update processing in the preparation. The process includes forwarding the new request and the new priority information to another storage device when having determined at the determining that the new priority is higher than the priority of the update processing in the preparation.

Abstract: This controller is used in a system in which initiators and targets are connected via distributed buses to control transmission timing of an access request received from the initiators. The controller stores intermittent information including information about an intermittent period in which interference between packets can be restricted and bus operating frequency information indicating a bus operating frequency at which real-time performance is guaranteed for each initiator and which has been generated based on system configuration information and flow configuration information indicating, on a flow basis, a specification required for each initiator to access the target. The controller includes a clock generator; communications circuitry; and transmission interval setting circuitry which sets a time to send transmission permission responsive to a transmission request based on the intermittent period, a time when the transmission request is detected, and a previous transmission time.

Abstract: A channel activating method and a peripheral device are provided for activating a serial transmission channel to retrieve at least one firmware instruction from a host. The peripheral device includes a serial transmission port coupled to the host, a microprocessor coupled to the serial transmission port for performing functions of the peripheral device according to the firmware instruction, a memory for holding the firmware instruction, a trigger generator for generating a trigger signal by monitoring a control signal received from the host via the serial transmission port, and a signal generator, coupled to the trigger generator, for generating an indication signal to the host via the serial transmission port according to the trigger signal to activate the serial transmission channel.

Abstract: A method that includes configuring a queue into a plurality of segments, wherein each segment is associated with a depth factor which defines number of entries of task elements capable of being added in each segment, and wherein each segment is associated with a requirement factor; generating a plurality of task elements, each task element having an importance factor; and if a value of an importance factor of a task element is at least equal to a value of a requirement factor of a segment with an available entry to add the task element, then adding the task element in the entry of the segment.

Abstract: An address detection circuit may include one or more address storage units, an initialization unit suitable for deleting an address stored in an address storage unit having a value greater than N, wherein the value is obtained by dividing a respective total input number that addresses have been inputted after the corresponding address is stored by a respective input number corresponding to the stored address, a detection unit suitable for detecting an address having an input number that is a reference number or more from the addresses stored in the one or more address storage units, and a selection unit suitable for selecting an address storage unit in which an address is not stored and storing an input address in the selected address storage unit.

Abstract: A memory control apparatus that controls writing and reading of data to/from a memory. The memory control apparatus includes: a sequence control unit that receives a packet sequence including a write packet including a write request of data and a read packet including a read request of the data, and changes an arrangement of the write packet and the read packet included in the packet sequence so that a first predetermined number of write packets are arranged successively and a second predetermined number of read packets are arranged successively; and a command output unit that receives the packet sequence from the sequence control unit, and outputs a write command according to the write packet and an a read command according to the read packet to the memory, in accordance with an order of arrangement of the write packet and the read packet.

Abstract: There are provided a semiconductor integrated circuit device, a method of controlling a semiconductor integrated circuit device, and a cache device capable of efficiently implementing power saving, wherein the cache device includes a low-voltage operation enabling cache (200), and a small-area cache (300) having a type different from that of the cache (200), the cache (200) and the cache (300) being independently supplied with source voltage; the cache (200) being operable at a voltage lower than the lower limit voltage at which the cache (300) is operable; a cache control unit (400) operating switchable controls between a first mode allowing only the cache (200) to operate, and a second mode allowing the cache (200) or the cache (300) to operate; and the cache (200) in the first mode operating to supply a voltage below the lower limit voltage at which the cache (300) is operable, while interrupting power supply to the cache (300).

Abstract: A method and system are disclosed that permit a host application to obtain cluster location data, for example logical addresses associated with the clusters of a file, and to allow a host application to communicate the logical block address mapping information to firmware of a storage device. The method includes the host transmitting one or more clusters or partial clusters having a signature to the storage device where the storage device knows or has been instructed by the host to look for the signature. The storage device may receive clusters having a signature and, responsive to a host request, return logical address information to a host for the location in the storage device of the marked clusters. The host may parse a data structure on the storage device to obtain remaining cluster location information using a file's first cluster location or may request that the storage device return the cluster location information.

Abstract: Systems and methods for predicting electronic component behavior in bus-based systems are described. In some embodiments, a method may include identifying a first bus access request pending in a request queue, the first bus access request associated with a first master component operably coupled to a bus. The method may also include calculating a first wait time corresponding to the first bus access request, the first wait time indicative of a length of time after which the first master component is expected to be granted access to the bus. The method may further include, in response to the first wait time meeting a threshold value, issuing a command to the first master component. In some embodiments, various techniques disclosed herein may be implemented, for example, in a computer system, an integrated circuit, or the like.