Abstract: It is desirable that data stored in an old storage device is migrated to a new storage device without any interruption. According to a computer system of this invention, in a first data storage device, a second data storage area of a second data storage device is recognized as a virtualized data storage area of the first data storage device, a data copy relation between the first data storage area and the virtualized data storage area is established, the second data storage area is recognized from the computer based on the data copy relation, data is copied from the first data storage area to the virtualized data storage area based on the data copy relation, and after completion of a data copy operation, a connecting path is switched from the first data storage area to the second data storage area based on the data copy relation.

Abstract: A memory management apparatus suitable for reducing amount of memory usage and simplifying programs is provided. When an area allocation request has been inputted, an unused area having a size that is determined by area size information included in the area allocation request is searched for as a candidate area on the basis of a memory management table 400. And overlap flag corresponding to an adjoining area that is contiguous with the candidate area in its lower address orientation is read from the memory management table 400, and, based on the overlap flag, it is determined whether or not the adjoining area is an area that allows overlapped allocation. If it is determined the area is an area allowing overlapped allocation, a used area that overlaps with the adjoining area is allocated.

Abstract: A first software program executing on a computing device emulates a second computing device executing a software program using emulated memory. The first software program permits the second software program to perform an operation on a contiguous portion of the emulated memory only when a pointer and a table entry both contain the same identifier, thus protecting against common types of memory usage errors in the second software program. The pointer has an address to the contiguous portion. The table entry maps to the contiguous portion. A plurality of table entries map to a respective plurality of contiguous portions of the emulated memory. A plurality of the pointers each contain the address to a respective contiguous portion of the emulated memory as well as containing an identifier corresponding to the respective contiguous portion of the emulated memory. The second computing device can be high or low in resources.

Abstract: A method is disclosed to assign network addresses in a storage array disposed in a data storage and retrieval system comprising (P) data storage devices disposed in (N) data storage device assemblies. The method configures the (N) data storage device assemblies to comprise a spare data storage device assembly and a first storage array comprising (N?1) active data storage device assemblies, wherein each data storage device configured in the first storage array is assigned a network address, and wherein one of the spare data storage device disposed in the spare data storage device assembly is assigned a network address. In the event the method detects a failed data storage device disposed in the first storage array, then the method forms a second storage array comprising the first storage array, except the failed data storage device, in combination with the (i)th spare data storage device.

Abstract: Memory modules having accurate operating current values stored thereon and methods for fabricating and implementing such devices to improve system performance. Memory modules comprising a number of volatile memory devices may be fabricated. Operating current values for specific memory devices on the memory module or a specific lot in which the memory devices are fabricated may be stored on a non-volatile memory device on the memory module. A system may be configured in accordance with the operating current values stored on the non-volatile memory device such that operating current thresholds are not exceeded.

Abstract: In a network management application, a system applies a management action to a resource by receiving a selection of a resource representation in a network environment that represents a resource to which a management action is to be applied. The system applies a series of resource traversal functions to a repository containing objects representative of network resources in the network environment. The traversal functions identify a set of action affected resources in the network environment existing along a set of relationship paths extending to at least one storage device that have a current allocation relationship to the selected resource. The system presents a representation of the set of allocated resources in the network environment to a user of the management application.

Abstract: A mechanism that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to perform I/O transactions using the PCI host bus, device, and function numbers to validate that an I/O transaction originated from the proper host is provided. Additionally, a method for facilitating identification of a transaction source partition is provided. An input/output transaction that is directed to a physical adapter is originated from a system image of a plurality of system images. The host data processing system adds an identifier of the system image to the input/output transaction. The input/output transaction is then conveyed to the physical adapter for processing of the input/output transaction.

Abstract: A method, computer program product, and distributed data processing system that allows a system image within a multiple system image virtual server to directly expose a portion, or all, of its associated system memory to a shared PCI adapter without having to go through a trusted component, such as a Hypervisor. Specifically, the present invention is directed to a mechanism for sharing conventional PCI I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications.

Abstract: Alignment of clusters to pages is provided in a non-volatile memory system that receives data from a host in clusters and writes data to a memory array in units of a page. Alignment is implemented within each block using offsets in logical-to-physical mapping of data. Different blocks may have different offsets. When a host sends data with different cluster boundary locations, the data may be written with different offsets so that data maintains alignment.

Abstract: A configuration setting system is provided for a network system including a plurality of electronic devices communicably connected to a network. The configuration setting system sets a configuration of an electronic device based on a configuration of a predetermined electronic device functioning as a model device. The predetermined electronic device is provided with a checking system that checks whether there is a currently operating model device on the network when the predetermined electronic device is to function as the model device, and a determining system that determines, when the checking system detects no model device on the network, that the predetermined electronic device should operate as the model device for the network system.

Abstract: A MIME or XML formatted message is stored and a map is processed in place of a message. The map is a compact representation of the message. The map is indicative of the content and structure of the message. The map comprises tags that map to and are indicative of portions of the message. When a portion of the message is to be accessed, the associated tag in the map is processed to determine the location of the associated portion of the message, and the associated portion of the message is accessed at the location. To allow accurate decryption of signed messages, the format of the message is preserved.

Abstract: Systems and methods are provided for accessing thread private data in a computer. In one embodiment, a method is provided for accessing thread private data in a computer for a program executed by using a plurality of threads, wherein each of the plurality of threads may be associated with a different area of its respective stack for storage of thread private data. Further, the stacks of threads may cover a coherent address space in a memory of the computer, starting at a base address. The method may include determining a thread identifier of the one of the plurality of threads based on the base address and a stack pointer of one of the plurality of threads. In addition, the method may include accessing thread private data of one of the stacks based on the determined thread identifier.

Abstract: A method, computer program product, and distributed data processing system that allows a single physical I/O adapter to validate that a memory mapped I/O address referenced by an incoming I/O operation is associated with a virtual host that initiated the incoming memory mapped I/O operation is provided. Specifically, the present invention is directed to a mechanism for sharing a PCI family I/O adapter and, in general, any I/O adapter that uses a memory mapped I/O interface for communications. A mechanism is provided that allows a single physical I/O adapter to validate that a memory mapped I/O address referenced by an incoming memory mapped I/O operation used to initiate an I/O transaction is associated with a virtual host that initiated the incoming memory mapped I/O operation.

Abstract: The present invention provides improved techniques for managing storage resources, such as disk drives, I/O ports, and the like in a network based storage system according to a user position within the network. Embodiments according to the present invention can provide a relatively high performance storage access environment for the mobile users moving around a wide area. For example, in one applicable environment, there are several data centers in the wide area, and each data center has a local storage system that is connected to the other storage systems through a network. Copies of a user's volume can be made in some of the storage systems. A remote copy function is utilized for making real time copies of the user's volume.

Abstract: The present disclosure relates to attempting to monitor and control memory access and, more specifically, to attempting to limit memory access to a specific registered software agent.

Abstract: An integrated device is provided that includes a non-volatile memory having an addressing parallelism and a data parallelism, and a communication interface for interfacing the memory with an external bus. The external bus has a transfer parallelism lower than the addressing parallelism and the data parallelism. The communication interface includes control means for executing multiple reading operations and/or multiple writing operations on the memory according to different modalities in response to corresponding command codes received from the external bus. Also provided is a method of operating such an integrated device.

Abstract: A method, computer program product, and distributed data processing system that enables host software or firmware to allocate virtual resources to one or more system images from a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, is provided. Adapter resource groups are assigned to respective system images. An adapter resource group is exclusively available to the system image to which the adapter resource group assignment was made. Assignment of adapter resource groups may be made per a relative resource assignment or an absolute resource assignment. In another embodiment, adapter resource groups are assigned to system images on a first come, first served basis.

Abstract: Embodiments of the invention generally provide a memory device and a method for providing the memory device. In one embodiment, the method includes providing one or more layers including a memory array of the memory device. The one or more layers are arranged in a manner allowing selection of a configuration for the memory device from at least a first configuration and a second configuration. Operation of the memory device is different in the first configuration with respect to the second configuration. The method also includes selecting a configuration for the memory device from at least the first configuration and the second configuration. The method further includes providing a first layer disposed on the one or more layers if the first configuration is selected. The first layer corresponds to the first configuration. The method also includes providing a second layer disposed on the one or more layers if the second configuration is selected. The second layer corresponds to the second configuration.

Abstract: A storage apparatus is capable of relocating volumes accurately even when a plurality of storage apparatuses are connected. The storage apparatus comprises an external connection function for recognizing an external logical volume set on a physical storage device as a logical volume inside the storage apparatus, a storage control device with a volume relocation function for relocating the logical volumes based on set conditions, and a storage unit with a plurality of physical storage devices. When the host sends a read request to the logical volume set on the physical storage device of the storage unit, the volume relocation function generates internally the same read request to the external storage volume set on the physical storage device in the external storage apparatus and relocates volumes based on the monitor information obtained by monitoring responses to the read request.

Abstract: A data handling device capable of operating in a system in which two or more devices are connected by a data bus for the transmission of communications therebetween, the data bus having two or more data lines and the device having: two or more data bus connectors, each for connection to a respective data line of the data bus; an identity acquisition unit capable of functioning in a first mode of operation of the device to receive data transmitted over the data bus and in response to the order in which the bits of one or more data words of a predetermined form are received on the data bus connectors during the first mode of operation determine an identity for the device and store the identity in an identity store of the device; and a data handling unit capable of functioning in a second mode of operation of the device to handle communications transmitted over the bus and that specify the identity stored in the data store as a destination.

Abstract: Methods, systems and computer program products to communicate between System On Chip (SOC) units in a cluster configuration are provided herein. A local SOC unit that includes a local controller and a local on-chip memory is provided. In response to receiving a signal from a remote SOC, the local controller is configured to retrieve a message from a remote on-chip memory of the remote SOC and store the message in the local on-chip memory. The local controller is a node controller and the local on-chip memory is a Static Random Access Memory (SRAM). The local SOC and the remote SOC are part of a cluster.

Abstract: The invention relates to a method for the automatic retrieval of engineering data from installations. The engineering and runtime objects are described by a uniform object model. This allows the correspondence between engineering objects and runtime objects to be determined at object level and no information is lost as a result of the mapping. In addition, a direct communication between engineering and runtime objects can take place, which can be utilized when the method is carried out.

Abstract: A high-speed memory is provided, the memory having a write port and a read port and comprised of the following: a plurality of N memory modules for storing fixed size cells, which are segments of a variable size packet divided into X cells, the X cells being grouped into ?X/N? groups of cells; a read-write control block receiving cells from the write port and storing each cell, which belongs to the same group, in a selected different one of the N memory modules at the same memory address (the group address); a multi-cell pointer (MCP) storage for storing an MCP for the group of cells (an associated MCP) at an MCP address, the MCP having N memory module identifiers to record the order in which cells of the group of cells are stored in the N memory modules; the MCP address being the same as the group address.

Abstract: An integrated circuit implementing a storage-shelf router used alone, or in combination with other storage-shelf routers, and in combination with path controller cards, to interconnect the disks within a storage shelf or disk array to a high-bandwidth communications medium, such as an FC arbitrated loop, through which data is exchanged between the individual disk drives of the storage shelf and a disk-array controller. A set of interconnected storage-shelf routers within a storage shelf can be accessed through a single port of an FC arbitrated loop or other high-bandwidth communications medium. Because, in one implementation, eight storage-shelf routers can be interconnected within a storage shelf to provide highly available interconnection of sixty-four disk drives within the storage shelf to an FC arbitrated loop via a single FC-arbitrated-loop port, a single FC arbitrated loop including a disk-array controller, may interconnect 8,000 individual disk drives to the disk-array controller within a disk array.

Abstract: Storage protection keys and system data share the same physical storage. The key region is dynamically relocatable by firmware. A Configuration Array is used to map the absolute address of the key region in to its physical address. The absolute address of keys can be fixed even though the physical location of the keys is relocated into a different region. A triple-etect double correct ECC scheme is used to protect keys. The ECC scheme is different from regular data in the storage and can be used to detect illegal access. Extra firmware and hardware is also designed to restrain customer's applications from directly accessing keys. With the key region being relocatable, the firmware could move the key region away from a known faulty area in a memory to improve system RAS. We also achieved the commonality objective that key memory device can use the same memory devices with other server systems that do not use keys.

Abstract: A system and method for performing incremental initialization of a master runtime system process is presented. A set of one or more warmup actions is defined from a source definition provided as object-oriented program code. A master runtime system process is executed. Each warmup action is executed to refine a memory space of the master runtime system process. The memory space is cloned as a child runtime system process responsive to a process request and the child runtime system process is executed. Initialization is incremental, such that the warmup actions are interleaved with potential requests for cloning child runtime system processes. The interleaving allows a user to interact with the master runtime system process before the full set of warmup actions are completed by the master runtime system process.

Abstract: Embodiments of the present invention provide a method and apparatus for conserving power in an electronic device. In particular, embodiments of the present invention dynamically place the memory in self-refresh and chipset clock circuits in power down mode while keeping the isochronous streams (such as display) updated and servicing bus master cycles in a power savings mode.

Abstract: Provided are a mapping method and a video system for mapping pixel data included in the same pixel group to the same bank of a memory, A method for mapping the position of pixel data of a picture to an address of a memory comprises a pixel group dividing operation and an address mapping operation. The pixel group dividing operation divides the pixels of the picture into at least one pixel group. The address mapping operation maps pixel data of pixels included in the same pixel group to the same bank of the memory.

Abstract: Data are stored in a memory whose physical pages have a common physical page size by exporting, to a host, a flash-type NAND interface for exchanging data sectors with the host. The common size of the data sectors is different than the physical page size.

Abstract: A pointer manager is described. The pointer manager includes write circuitry to enter, into a queue that is implemented with a first memory, a pointer value that a read hub has exhausted the use of. The pointer manager also includes read circuitry to remove, from said queue, a pointer value that is to be sent to a write hub. The pointer manager also includes write circuitry to add, to a link list that is maintained with a second memory, a pointer value that is to be sent to the write hub. The pointer manager also includes read circuitry to obtain, from said link list, a pointer value that is to be sent to a read hub.

Abstract: With scope-based cache coherence, a cache can maintain scope information for a memory address. The scope information specifies caches in which data of the address is potentially cached, but not necessarily caches in which data of the address is actually cached. Appropriate scope information can be used as snoop filters to reduce unnecessary coherence messages and snoop operations in SMP systems. If a cache maintains scope information of an address, it can potentially avoid sending cache requests to caches outside the scope in case of a cache miss on the address. Scope information can be adjusted dynamically via a scope calibration operation to reflect changing data access patterns. A calibration prediction mechanism can be employed to predict when a scope calibration needs to be invoked.

Abstract: Provided are a method, system, and article of manufacture, wherein in certain embodiments, a plurality of logical memory blocks corresponding to a memory in a computational device are allocated. An attribute is associated with at least one logical memory block, wherein the attribute indicates whether the at least one logical memory block can be swapped from the memory, and wherein physical blocks corresponding to the at least one logical memory block are contiguous.

Abstract: Presented herein is a direct memory access engine for providing data words in the reverse order. The data words are fetched in batches comprising a predetermined number of data words starting from the last data word and proceeding to the first data word. The batches are stored in a local buffer. The contents of the local buffer are transmitted in reverse order.

Abstract: In a cluster-structured disk subsystem, when creating a volume for an online backup separately from a volume for a normal I/O, it is desirable to be able to achieve such a creation for any volume under subsystem. Further, with an increase in the capacity of the subsystem, it becomes more difficult for a user to determine where to place a volume to which data is to be copied. Thus, a cluster-structured storage system is provided in which it is possible to reference/renew snapshot control information in shared memory of other clusters and achieve a snapshot between clusters via an inter-cluster connecting mechanism. In this system, control is performed inside/outside the cluster, and a control is performed inside/outside the cluster, and a volume to which data is to be copied is suggested to the user.

Abstract: A method for migrating from a source storage system to a target storage system includes defining a volume defined on a device to be migrated in the source storage system as an external volume to the target storage system; causing the host to access the volume on the drive to be migrated through an input/output port of the drive to be migrated as the external volume of the target storage system; blocking the other input/output port of the drive to be migrated while maintaining the access to the external volume of the target storage system; reconnecting the blocked input/output port with an interface in the target storage system; blocking the input/output port through which the external volume is being accessed, and connecting it with the interface in the target storage system; and implementing the drive to be migrated in the target storage system.

Abstract: A graphics processing system has a cache which is partitionable into two or more slots. Once partitioned, the slots are dynamically allocatable to one or more texture maps. First, number of texture maps needed to render a given scene is determined. Then, available slots of the cache are allocated to the texture maps. Sometimes, more slots are allocated to the largest texture map. At other times, more slots are allocated to the texture map which is likely to be used most often. The slots can also be allocated equally to all of the texture maps needed.

Abstract: A memory system (200) has an array of addressable storage elements (210) arranged in a plurality of rows and a plurality of columns, and decoding circuitry (220, 230) coupled to the array of addressable storage elements (210). The decoding circuitry (220, 230), in response to decoding a first address, accesses a first storage element of a first row of the plurality of rows, and, in response to decoding a second address consecutive to the first address, accesses a second storage element of a second row of the plurality of rows. The second row of the plurality of rows is different from the first row of the plurality of rows. By implementing a memory system wherein consecutive addresses correspond to storage elements of different rows, read disturb stresses along a single row can be minimized.

Abstract: An agent system processes information by agents. The agent system is connected to an agent system of different type through a network. A wrapper class memory stores component data of wrappers corresponding to each type of agent system. The wrapper specially processes information in a corresponding agent system. A wrapper generation section generates a wrapper corresponding to an agent system of a different type based on the component data of the different type in the wrapper class memory. The wrapper acts for the agent to use resources in the other agent system.

Abstract: When a peripheral LSI has a memory space which is other than the memory space of a CPU, access is made without one of the memory spaces being aware of the other memory spaces. A flexible bus controller BSC makes address translation according to information on the relation between addresses of both memory spaces. The invention assures wider latitude in CPU type selection and makes it easy to reuse an existing program or develop a new program.

Abstract: A branch aware first-in first-out (FIFO) memory may include a memory array to store data; a push pointer to address memory locations therein to write data; a pop pointer to address memory locations therein to read data; a pointer memory; and control logic coupled to the pointer memory. The pointer memory saves prior pop pointer values of the pop pointer. The control logic may restore prior pop pointer values from the pointer memory into the pop pointer in response to receiving program branching information.

Abstract: A first array of disk drives overlaps with a second array of disk drives in a Redundant Array of Inexpensive Drives (RAID) system, in which the first and second arrays share at least one disk drive. A first stripe of data from a first client is stored in the first array, and a second stripe of data from a second client is stored in the second array. The shared disk drives are less than the number of drives needed to reconstruct a full stripe. Thus, in the event of a drive failure in the first array, the first client can reconstruct the first data stripe, but is never able to reconstruct the second stripe. Likewise, in the event of a drive failure in the second array, the second client can reconstruct the second data stripe, but is never able to reconstruct the first stripe.

Abstract: A single memory element, which may consist of general purpose SRAM chips, implements both tag and data cache memory functions, resulting in an efficient, low cost implementation of high speed external cache memory. In one embodiment, a bank of general purpose RAM used by a microprocessor as an external cache memory stores both cache tags and cache data in separate memory locations. During a read operation, the microprocessor retrieves a cache tag from the bank of general purpose RAM before retrieving corresponding cache data therefrom, and compares the cache tag to a memory address to assess whether requested data resides in the cache memory. The comparison may also be performed concurrently by a system controller device, which may abort the main memory access if a cache hit is detected.

Abstract: Methods and apparatus are disclosed for determining if a user-defined software function is a memory allocation function during compile-time. The methods and apparatus determine if a user-defined function returns a new memory object every time the user-defined function is invoked. In addition, the methods and apparatus determine if the memory objects created by the user-defined function are available outside the scope of the user defined function. If the user-defined function returns a new memory object every time the user-defined function is invoked, and the memory objects created by the user-defined function are not available outside the scope of the user defined function, then the user-defined function is determined to be a memory allocation function. Otherwise, the user-defined function is determined to be a non-memory allocation function.

Abstract: This disclosure relates to drawing within a computer environment using a drawing resource. The computer environment includes a managed code portion and a native code portion. The computer environment compares a draw parameter call value being passed from the managed code portion to the native code portion with a stored drawing resource value stored in the native code portion. If the draw parameter call value is the same as the stored drawing resource value, then the computer environment is configured to draw onto a native drawing surface using the stored drawing resource. If the draw parameter call value is not the same as the drawing resource value, then a new drawing resource is created in the managed code portion. In another aspect, a portion of the drawing resource feature portion that contains data that describes at least one or more parameter of the drawing resource is transmitted between the managed code portion and the native code portion.

Abstract: The invention relates to an automatic decoding method for mapping and selecting a non-volatile memory device having a LPC serial communication interface in the available addressing area on motherboards. A logic structure is incorporated in the memory device, which allows a correct decoding to address the memory to the top of the addressable area or to the bottom of the same area, i.e., in both possible cases. This logic incorporates a non-volatile register whose information is stored in a Content Address Memory to enable the automatic mapping of the memory in the addressable memory area.

Abstract: Methods, devices, configuration tools and operating systems are disclosed for reducing memory and processor usage in a computer operating system utilising a processor, a memory and a single stack, the operating system comprising a plurality of tasks divided into predetermined priority categories, including preemptive tasks and at least one task that voluntarily yields control of the processor to tasks of lower priority than itself in predetermined circumstances, wherein each task has associated therewith a stack pointer, and wherein the at least one task, when started, has its stack pointer set to a precalculated worst-case value guaranteed to leave sufficient space in the stack beneath the stack pointer for any preemptive tasks of lower priority, and wherein the at least one task has allocated to it an area of memory into which its stack contents is saved, a size of the area of memory being determined by a declared precalculated worst-case stack usage of the at least one task at any point at which the at lea

Abstract: A processor having the capability to dispatch multiple parallel operations, including multiple load operations, accesses a cache which is divided into banks. Each bank supports a limited number of simultaneous read and write access operations. A bank prediction field is associated with each memory access operation. Memory access operations are selected for dispatch so that they are predicted to be non-conflicting. Preferably, the processor automatically maintains a bank predict value based on previous bank accesses, and a confirmation value indicating a degree of confidence in the bank prediction. The confirmation value is preferably an up-or-down counter which is incremented with each correct prediction and decremented with each incorrect prediction.

Abstract: A method and system enables dynamic support of memory mapping devices in a multi-node computer system. One of central process unit (CPU) nodes determines a total amount of MMIO address spaces that are needed for all MMIO devices and generates an optimized granularity to support the total amount of MMIO address spaces. Based on the granularity, a CPU node controller configures MMIO range registers of the interconnect and other MMIO registers in IO nodes and CPU node controllers to support dynamic changes of MMIO address space requirements of the system.

Abstract: The present invention provides for a system for programmable memory initialization. A configuration module is configured with initialization control commands and associated configuration information. An initialization module is coupled to the configuration module and a memory device and is configured to receive initialization control commands and associated configuration information from the configuration module, and to send memory initialization commands to the memory device based on received initialization control commands and associated configuration information.

Abstract: Apparatus and methods for addressing predicting useful in high-performance computing systems. The present invention provides novel correlation prediction tables. In one embodiment, correlation prediction tables of the present invention contain an entered key for each successor value entered into the correlation table. In a second embodiment, correlation prediction tables of the present invention utilize address offsets for both the entered keys and entered successor values.