Abstract: Method and apparatus for tagged references for identifying thread-local data in multithreaded applications. Embodiments may provide a dynamic mechanism that identifies thread-local objects by “tagging” references to the objects. In embodiments, in an application, if an object is to be allocated as a thread-local object, one or more bits of the object reference may be “tagged” to indicate that the object is a thread-local object. In one embodiment, the lowest-order bit of the object reference may be set to indicate that the object is a thread-local object. In embodiments, thread locality of an object may be determined by testing the reference itself rather than loading a bit or field from the referenced object or by checking address ranges. Further, embodiments do not rely on address ranges to identify objects as thread-local, and so the allocation of thread-local objects may not be restricted to thread-local heaps.

Abstract: Systems and/or methods that facilitate accessing data to/from a memory are presented. An electronic memory component can operate with reduced data access times by eliminating/reducing the use of logical block addressing and employing physical block addressing. Data access is thereby directly associated with the physical location of the stored bits and the need to translate between a logical address and the physical address is reduced or eliminated. This can be even more efficient under asymmetric data access patterns. Further, legacy support for logical block addressing can be included to provide backward compatibility, mixed mode operation, or complimentary mode operation.

Abstract: A method for storing a memory defect map is disclosed whereby a memory component is tested for defects at the time of manufacture and any memory defects detected are stored in a memory defect map and used to optimize the system performance. The memory defect map is updated and the system's remapping resources optimized as new memory defects are detected during operation.

Abstract: In one embodiment, there is provided a method for a media storage device to manage digital content. The method comprises determining if there is digital content to be categorized into one or more galleries; automatically categorizing said digital content into the one or more galleries; and for digital content categorized into a gallery with an auto-publish flag, sending at least one of said digital content and a derivative form of said digital content to a server.

Abstract: A method, computer program product, and distributed data processing system that allows a system image within a multiple system image virtual server to directly expose a portion, or all, of its associated system memory to a shared PCI adapter without having to go through a trusted component, such as a Hypervisor. Specifically, the present invention is directed to a mechanism for sharing conventional PCI I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications.

Abstract: Methods and apparatus provide for receiving a request for memory from a network stack subsystem running in user mode. The request is received at a listing of pointers that resides within the network stack but separate from kernel memory. Each available pointer in the listing of pointers references a particular free kernel memory location. In response to the request, the listing of pointers provides the network stack subsystem with at least one pointer to a free kernel memory location. Via the pointer, the network stack subsystem that received the pointer to the free kernel memory location directly writes at least one segment of a packet to the free kernel memory location.

Abstract: A computer-implemented method, apparatus, and computer usable program code are disclosed for migrating a virtual adapter from a source physical adapter to a destination physical adapter in a data processing system where multiple host computer systems share multiple adapters and communicate with those adapters through a PCI switched-fabric bus. The virtual adapter is first caused to stop processing transactions. All in-flight transactions that are associated with the virtual adapter are then captured. The configuration information that defines the virtual adapter is moved from the source physical adapter to the destination physical adapter. The in-flight transactions are then restored to their original locations on the destination virtual adapter. The virtual adapter is then restarted on the destination physical adapter such that the virtual adapter begins processing transactions.

Abstract: A hardware Secure Processing Unit (SPU) is described that can perform both security functions and other information appliance functions using the same set of hardware resources. Because the additional hardware required to support security functions is a relatively small fraction of the overall device hardware, this type of SPU can be competitive with ordinary non-secure CPUs or microcontrollers that perform the same functions. A set of minimal initialization and management hardware and software is added to, e.g., a standard CPU/microcontroller. The additional hardware and/or software creates an SPU environment and performs the functions needed to virtualize the SPU's hardware resources so that they can be shared between security functions and other functions performed by the same CPU.

Abstract: A method and system are provided for a virtual distributed data manager. In one example of the method, the virtual data manager involves receiving a request to mount a file system onto the client computer, wherein the file system is stored on the server system and contains the one or more data files; transferring a copy of a directory structure of the file system stored on the server system to the client computer; and creating on the client computer a virtual file system including the copy of the directory structure. The method is preferably transaction based and provides high performance on high latency network connections.

Abstract: The present invention provides a controller that allows plural processor nodes to access plural boot memories concurrently.

Abstract: A computer program product, apparatus, and method are provided for determining a state of an input/output (I/O) operation in an I/O processing system. A request from a channel subsystem is received at a control unit for performing the I/O operation. After a predetermined amount of time passes without the I/O operation completing, an interrogation request is received from the channel subsystem at the control unit for determining the state of the I/O operation. A response is sent from the control unit to the channel subsystem indicating the state of the I/O operation in response to the interrogation request. The response also includes information regarding a state of an I/O device executing the I/O operation and information indicating a state of the control unit controlling the I/O device executing the I/O operation.

Abstract: Systems, methods and computer program products for providing indirect data addressing at an I/O subsystem of an I/O processing system. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a control word for an I/O operation. The control word includes an indirect data address for data associated with the I/O operation. The indirect data address includes a starting location of a list of storage addresses that collectively specify the data, the list spans two or more non-contiguous storage locations. Data is gathered responsive to the list. The gathered data is transmitted to a control unit in the I/O processing system.

Abstract: A mechanism for modifying resources in a logically partitioned data processing system is provided. A request to modify resources associated with a virtual adapter allocated on a physical adapter is invoked. The resources associated with the virtual adapter comprise a subset of the physical adapter resources. The request to modify the physical adapter is conveyed to the physical adapter. Responsive to receipt of the request by the physical adapter, the physical adapter modifies the resources allocated to the virtual adapter.

Abstract: Disclosed is memory apparatus (20) in which an area (34) of a memory element (24) is reserved for configuration data relating to parameters of the memory apparatus (20), the area (34) being accessible using a command issued by a device driver (10). Including the configuration data in the memory apparatus (20) simplifies the design and maintenance of the device driver (10).

Abstract: Aspects of the subject matter described herein relate to initializing a database to be used for synchronization. In aspects, a peer in a synchronization topology creates a consistent copy of its database. Metadata associated with this copy is marked to distinguish changes made before the copy was created from changes made after the copy was created and also that the copy needs to be prepared before being used in synchronization. Any client may then download the copy and start immediately reading and modifying its downloaded copy. Before the client synchronizes its copy with other databases already in the synchronization topology, the downloaded copy is prepared for use in the topology using the markers.

Abstract: Techniques for converting file-systems used for organizing and storing data on computer readable mediums are disclosed. A first file-system is converted to a second file-system while file(s) stored on the computer readable medium remain(s) virtually undisturbed in the same location. A FAT file-system (e.g., FAT32) is converted to an HFS file-system (e.g., HFS Plus) by generating HFS data structures (Catalog, Allocation File and Extents) for file(s) already stored in the HFS file-system. The number and location of the file(s) can be determined primarily based on the FAT file-system's data structures (FAT and Directory). The conversion process can be stopped before the FAT file-system indicators (partition map and boot sector) are overwritten.

Abstract: A method, apparatus, system and computer program product that provide a virtual worldwide name (vWWN) nameservice in a Fiber Channel storage area network (SAN) are provided. Embodiments of the vWWN nameservice can receive a request for a vWWN from a node in the SAN, where the request includes a identifier associated with resources in the SAN, then determine if the identifier matches contents of a field in one or more entries in a vWWN table or database, and provide the vWWN associated with a matching entry to the requesting node.

Abstract: In one embodiment, a processor comprises execution circuitry and a translation lookaside buffer (TLB) coupled to the execution circuitry. The execution circuitry is configured to execute a store instruction having a data operand; and the execution circuitry is configured to generate a virtual address as part of executing the store instruction. The TLB is coupled to receive the virtual address and configured to translate the virtual address to a first physical address. Additionally, the TLB is coupled to receive the data operand and to translate the data operand to a second physical address. A hardware accelerator is also contemplated in various embodiments, as is a processor coupled to the hardware accelerator, a method, and a computer readable medium storing instruction which, when executed, implement a portion of the method.

Abstract: A chip multithreading processor schedules and assigns threads to its processing cores dependent on estimated miss rates in a shared cache memory of the threads. A cache miss rate of a thread is estimated by measuring cache miss rates of one or more groups of executing threads, where at least one of the groups includes the thread of interest. Using a determined estimated cache miss rate of the thread, the thread is scheduled with other threads to achieve a relatively low cache miss rate in the shared cache memory.

Abstract: A bank note processing machine includes a plurality of sensors, a transport system, an input/output device, a control device and an interface. The control device has a memory configured to control elements of the bank note processing machine by means of software and/or data stored in the memory. The interface is arranged to couple memory systems of different kinds to the bank note processing machine in order to alter, supplement or replace software and/or data stored in the memory.

Abstract: A data processing system includes a multiport memory module including a plurality of first ports and a plurality of second ports. The data processing system includes a plurality of first buses and a plurality of second buses. A plurality of hardware acceleration modules configured to communicate with respective ones of the plurality of first ports via respective ones of the plurality of first buses. The data processing system includes a processor module. A random access memory (RAM) module configured to store data. The processor module and the RAM module communicate with the multiport memory module via respective ones of the plurality of second buses. A shared bus includes a first bus portion configured to communicate with the plurality of hardware acceleration modules at a first rate. A second bus portion configured to communicate with the processor module and the RAM module at a second rate that is different than the first rate.

Abstract: A mobile phone with an expanded telephone directory, wherein any electronic telephone directory of the mobile phone is supplemented by, in each case, one data base located in the nonvolatile memory of the mobile phone, each data base being assigned to precisely one specific telephone directory. The data base assigned to a telephone directory is preferably an expansion telephone directory, and a number of the expansion telephone directories can be assigned to each telephone directory.

Abstract: Data transfer is performed to and from a host computer using a first block as the minimum unit. Data transfer is performed to and from a storage area using a second block as the minimum unit. A second block set of the storage area stores data obtained from performing data conversion processes that change the size of the data itself, with a first block set as the unit. Here a correspondence relationship is generated between the first block set and the second block set. In response to a read request from the host computer, a second block set, which corresponds to the first block set that includes the first block that is requested, is read, a reverse-conversion process is performed, and the data is sent to the host computer.

Abstract: There is provided a storage system capable of handling a large amount of control data at low cost in high performance. The storage system includes a cache memory for temporarily storing data read/written between a host computer and a disk array, a CPU for making a control related to data transfer, and a local memory for storing control data utilized by the CPU. The disk array has a first user data storing area for storing user data and a control data storing area for storing all control data. A control unit has a virtualization unit for allocating a memory space of the control data storing area to a virtual address accessible from the CPU, reading the control data specified by the virtual address to a physical address of the local memory, and transferring the control data to the CPU.

Abstract: A method and device for flexible, dynamic and optimal buffering in a networking system are provided. Sizes of incoming packets are recognized and the packets are buffered into buffers of appropriate sizes. Usage times of buffers are counted, and during an idle state of the networking system, buffer number and descriptor number are re-calculated based on usage times. Then, buffers and descriptors are re-allocated based on the re-calculated number. By re-allocation, buffer sets with higher usage times are allocated with more buffers, and vice versa, so memory waste is lowered and the overall performance of the networking system is improved.

Abstract: A system and method are provided for storing and using recovery state information during a data stream transfer, such as a download. During the download of compressed, archived data, the system tracks the position of the last file boundary and the position of the last compression block boundary before the last file boundary, and the system stores this information as a recovery state. If the download is interrupted, the system uses the recovery state information to resume the download at an efficient location in the data stream.

Abstract: A method for verifying data in a storage system is disclosed. A host computer transmits area management data to a storage controller. The area management data specifies a range of a storage area in a storage device to be used by an application program having a mechanism for verifying data suitability. Upon receipt of an input/output request transmitted from the host computer, the storage controller performs verification, which is usually performed by the application program, of the data that is to be processed according to the data input/output request and to be input/output to/from the storage area, which is specified in accordance with the received area management data.

Abstract: A memory device and a method for managing the memory device is provided. The memory device includes a flash memory including a plurality of pages, a non-volatile RAM storing a first mapping table between a physical page address and a logical page address for each page of the plurality of pages, and a volatile RAM storing a second mapping table between the physical page address and the logical page address for each page of the plurality of pages.

Abstract: A computer system includes a CPU (Central Processing Unit) and a main storage interconnected by a bus to the CPU. The I/O module for transferring received data and data to be transmitted to and from an external unit is directly connected to the main storage, which stores the received data or the transmission data, so that data transfer can be effected every minimum data cycle that allows an access to a memory macro included in the main storage. This accomplishes high-speed data transfer based on DMA (Direct Memory Access) transfer over the bus.

Abstract: The described implementations relate to efficient scheduling of transactions and tasks. A memory location, address, or variable previously accessed by a blocked entity is observed periodically to determine an appropriate time to wake and retry the blocked entity. If the previous accessed memory location, address or variable changes state, a scheduler wakes the blocked entity and the blocked entity retries processing. A doubly-indexed data structure of blocked entities and memory locations associated with the blocked entities may be used to efficiently determine when a retrying execution would be profitable.

Abstract: A DMA transfer control apparatus comprises an internal memory for temporarily storing data, a buffer for temporarily storing data, a selector for selecting one of input data to the buffer and output data from the buffer per byte, and a rotator for rotating data. The internal memory receives read data from a transfer source, the buffer receives data from the internal memory, the selector receives data from the internal memory and data from the buffer, and the rotator receives data selected by the selector. An output of the rotator is used as write data. Thereby, high-speed DMA transfer is performed even when data transfer source addresses and data transfer destination addresses have different byte alignments where the addresses are located.

Abstract: Disclosed are systems and methods for reserve allocation of event data. A request event is received. The request event is associated with memory storing request event data. Memory for response event data is allocated from a first pool. The response event data is associated with a response, and the response is associated with the request. Upon failure of the allocation of memory for the response event data, memory is obtained for out-of-memory response event data. The out-of-memory response event data is associated with the response event. The request event is completed using the response event.

Abstract: A datastore, such as a registry or file system having a defined data structure with a logical layer, may be analyzed using a bitmap corresponding to equally sized blocks of data in the datastore. The bitmap is created by traversing the datastore and setting a bit at the beginning of each cell of data, where one cell may have multiple blocks. The datastore is traversed again at a logical layer to verify that each cell is used only one time. The second traverse may unset the beginning bit of each cell as the cell is used. An inconsistency is detected in the datastore when a bit is already unset during the second traverse and when set bits exist after the second traverse.

Abstract: An apparatus and method for implementing a unified hash algorithm pipeline. In one embodiment, a cryptographic unit may include hash logic configured to compute a hash value of a data block according to a hash algorithm, where the hash algorithm is dynamically selectable from a plurality of hash algorithms, and where the hash logic comprises a plurality of pipeline stages each configured to compute a portion of the hash algorithm. The cryptographic unit may further include a word buffer configured to store the data block during computing by the hash logic.

Abstract: A mechanism that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to perform I/O transactions using the PCI host bus, device, and function numbers to validate that an I/O transaction originated from the proper host is provided. Additionally, a method for facilitating identification of a transaction source partition is provided. An input/output transaction that is directed to a physical adapter is originated from a system image of a plurality of system images. The host data processing system adds an identifier of the system image to the input/output transaction. The input/output transaction is then conveyed to the physical adapter for processing of the input/output transaction.

Abstract: A system and method for reducing instability in an information handling system are disclosed. A method includes detecting a configuration change of a first memory device. Next, the method determines a device identifier for a second memory device depending on the configuration change. The method proceeds to update a Configurable Identification (CID) register in the second memory device with the device identifier.

Abstract: The invention relates to a method for updating a basic input/output system (BIOS) and method for repairing the BIOS. A part of a program code of the BIOS is stored in a backup memory block in advance. If the BIOS fails to update, the backup program code can be adopted to start up a computer system and then the BIOS will be repaired.

Abstract: Provided are a method, system, and article of manufacture, wherein in certain embodiments, a plurality of logical memory blocks corresponding to a memory in a computational device are allocated. An attribute is associated with at least one logical memory block, wherein the attribute indicates whether the at least one logical memory block can be swapped from the memory, and wherein physical blocks corresponding to the at least one logical memory block are contiguous.

Abstract: A method of initializing memory parameters of a main storage device at a time of starting an information processing apparatus includes acquiring a temperature at the time of starting the information processing apparatus; and initializing the memory parameters based on the temperature.

Abstract: A host information memory is provided in a semiconductor memory card and a data write start address and a data size supplied by an access unit are stored. A free physical area generation section determines whether or not to perform erasing of an invalid block of a nonvolatile memory when writing of data based on the data write start address and data size, and determines the number of blocks to be erased. When erasing, writing of data and erasing of invalid blocks are simultaneously performed with respect to different memory chips. Erase process of data, herewith, can be optimized and high speed access from the access unit to a semiconductor memory card can be realized.

Abstract: A memory module stores data in the form of code words, each code word comprising useful bits and check bits for error correction. The memory module contains a first group of the memory devices including check bits and a second group of the memory devices including useful bits, the second group memory devices forming ranks, each rank being addressed as a whole, the ranks forming rank groups, each rank group including at least two ranks and a first group memory device. The memory module further contains a connecting device transferring bit packets each containing useful bits and check bits in the parallel format between an interface of the memory module and the memory devices of a selected rank group.

Abstract: Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. The logic die can include a command register that allows selective operation in either of two modes. In a direct mode, conventional command signals as well as row and column address signals are applied to the logic die, and the logic die can essentially couple these signals directly to the memory device dice. In an indirect mode, a packet containing a command and a composite address are applied to the logic die, and the logic die can decode the command and composite address to apply conventional command signals as well as row and column address signals to the memory device dice.

Abstract: Devices, systems and methods of reduced-power memory address generation. For example, an apparatus includes: a carry save adder including at least a first set of adders and a second set of adders, wherein the adders of the first set are able to receive a first number of input bits and to produce a first number of outputs, and wherein adders of the second set are able to receive a second number of input bits and to produce the first number of outputs.

Abstract: A computer network system includes a client-server architecture, where the client transmits SCSI commands over a network using TCP/IP to a server to request input and output operations for a physical storage device that is communicatively coupled to a storage device. The client perceives the storage device to be a local disk drive, even though the storage device is located on the target side of a network. The system includes a client-side disk-based cache.

Abstract: One embodiment of the invention relates to the transfer of content between a host computer that issues OAS access requests and a block I/O storage system. Specifically, a host computer may issue an access request for a content unit that identifies the content unit is an object identifier. The request may be received by a second server, which may determine the block address(es) on the block I/O storage system at which the content unit is stored. A request may then be sent to the block I/O storage system to retrieve the content stored at the requested block address(es) and the block I/O storage system may return the content.

Abstract: A storage device is communicatively coupled to a management station and comprises an interface manager to send a notification to the management station when a network address of the storage device is changed to a new address. The management station retains information on the network address of the storage device and, upon receipt of a notification, reestablishes a connection to the storage device using the new address. Related methods, and components of the system, are also disclosed.

Abstract: Techniques are provided for allocating a plurality of resources on a chip to a plurality of partitions in a partitionable computer system. In one embodiment, a resource allocated to a first partition generates a physical address in an address space allocated to the first partition. A partition identification value identifies the first partition. The first partition identification value is stored in the first physical address to produce a partition-identifying address, which may be transmitted to a system fabric. In another embodiment, a transaction is received which includes a source terminus identifier identifying a source device which transmitted the transaction. It is determined, based on the source terminus identifier, whether the source device is allocated to the same partition as any of the plurality of resources. If the source device is so allocated, the transaction is transmitted to a resource that is allocated to the same partition as the source device.

Abstract: Property information of a driver is newly set or updated via a simple operation on a network. First, property information is created. When a driver is installed or updated, the created property information associated with the driver is transmitted from a server device to a client device, which in turn sets the property information of the driver.

Abstract: A method, apparatus and computer program product for file and folder scanning is presented. A host agent uses a scanning policy from a server, and scans the storage for the host system in accordance with the scanning policy. The host system then builds a data summary from the scanning results. The data summary is then provided to the server where it can be used to modify the storage on the host.

Abstract: A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.