Abstract: A processing system comprises a multiport memory module having N ports, N data communication buses, and N hardware acceleration modules that communicate with a respective one of the N ports on a respective one of the N data communication buses. A first one of the N hardware acceleration modules performs a first processing task on data and transmits the data to the multiport memory module on a first one of the N data communication buses. A second one of the N hardware acceleration modules receives the data from the multiport memory module on a second one of the N data communication buses and performs a second processing task on the data. N is an integer greater than one.

Abstract: The processing apparatus in the present invention is a processing apparatus which executes a program and performs processes of the program, and includes the following: an execution circuit having a plurality of operation modes, each of which has a different effect on the processing performance and the power consumption of the processing apparatus; a measurement unit operable to measure at least one of a process execution performance and an execution power consumption of the processor circuit; and a control unit operable to compare a target value and a measurement result from the measurement unit, and to switch the operation modes in accordance to a result of the comparison.

Abstract: A method of monitoring computer system calls by determining the system calls to be monitored. Then, determining data to be recorded for each system call. Then, creating a configuration file that includes the system calls and associated data. Then, modifying a system call table in a computer operating system to replace pointers to routines that correspond to system calls with pointers to a user-definable routine. If a system call occurs in a computer program then jumping to the user-definable routine, which reads the configuration file, jumps to a system call routine to execute the system call, returns to the user-definable routine with data produced by the system call routine, and records any returned data that is in the configuration file for that system call. Then, monitoring the computer program for other system calls.

Abstract: In a first embodiment, an applications programming interface (API) implements and manages isochronous and asynchronous data transfer operations between an application and a bus structure. During an synchronous transfer the API includes the ability to transfer any amount of data between one or more local data buffers within the application and a range of addresses over the bus structure using one or more asynchronous transactions. An automatic transaction generator may be used to automatically generate the transactions necessary to complete the data transfer. The API also includes the ability to transfer data between the application and another node on the bus structure isochronously over a dedicated channel. During an isochronous data transfer, a buffer management scheme is used to manage a linked list of data buffer descriptors.

Abstract: A method, computer program product, and distributed data processing system for directly destroying the resources associated with one or more virtual adapters that reside within a physical adapter is provided. A mechanism is provided for directly destroying the resources associated with one or more virtual adapters that reside within a physical adapter, such as a PCI, PCI-X, or PCI-E adapter.

Abstract: An internal memory controller of a network processor or other type of processor controls access of processor clients to memory instances of an internal memory of the processor. The internal memory controller includes a configurable switching element that is connectable between the clients and the memory instances, and is operative to control access of particular ones of the clients to particular ones of the memory instances. Generally, the configurable switching element is configurable to connect any one of at least a subset of the clients to each of at least a subset of the memory instances. In a first selectable configuration of the configurable switching element, a given one of the processor clients is permitted to access a first set of one or more memory instances, and in a second selectable configuration of the configurable switching element, the given processor client is permitted to access a second set of one or more memory instances, with the second set being different than the first set.

Abstract: A memory system having a plurality of sets of memory modules. The system includes a plurality of sets of memory controllers, each one of the memory controllers being coupled to a corresponding one of the plurality of sets of memory modules. The system includes a port for providing address and read/write control signals to the memory system. The memory controllers are interconnected in a daisy chain arrangement to the port.

Abstract: A control machine which uses a data amount stored in an FIFO as a trigger and allows a DMA transfer to be started according to a capacity of the FIFO allows a control machine for preparing for the DMA transfer to start to prepare a command and the like for the DMA transfer. The control machine for preparing for the DMA transfer issues the prepared command to a control machine for transferring DMA data, so that a process according to the command is started. At the time of the DMA transfer, a burden on a host CPU is reduced.

Abstract: A method, apparatus and program product are provided for moving data from a source memory zone to a target memory zone of a computer. A source host operating system invokes a synchronous multiple move command for SBAL output buffers with a common target zone. The machine firmware identifies and validates the target argument of the first SBAL, validates the target zone state, moves the data associated with the first SBAL to the target zone; and then iteratively moves the data associated with the remaining SBALs to the target zone.

Abstract: An integrated circuit (IC) comprises an embedded processor. An embedded in-circuit emulator (ICE) emulates at least one function of the embedded processor, performs at least one of testing and debugging on the IC, and generates testing results based on the at least one of the testing and the debugging. A serializer located on the IC receives the testing results from at least one of the embedded ICE and the embedded processor, serializes the testing results, and serially outputs the testing results from the IC.

Abstract: Systems and/or methods that facilitate accessing data to/from a memory are presented. An electronic memory component can operate with reduced data access times by eliminating/reducing the use of logical block addressing and employing physical block addressing. Data access is thereby directly associated with the physical location of the stored bits and the need to translate between a logical address and the physical address is reduced or eliminated. This can be even more efficient under asymmetric data access patterns. Further, legacy support for logical block addressing can be included to provide backward compatibility, mixed mode operation, or complimentary mode operation.

Abstract: A method and device are disclosed for an associative and approximate, analog or digital scanning of databases that allows for the asynchronous accessing of data from a mass storage medium. The invention includes providing dedicated analog and digital circuitry and decision logic at the mass storage medium level for determining a key identifying the data of interest, continuously comparing the key to a signal generated from a reading of the data from the mass storage medium with an approximate or exact matching circuit to determine a pattern match, determining a correlation value between the key and the data as it is read in a continuous fashion, and determining a match based upon a preselected threshold value for the correlation value. The pattern matching technique eliminates any need to compare data based on its intrinsic structure or value, and instead is based on an analog or digital pattern. The key and data may be either analog or digital.

Abstract: A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues event signals and predetermined memory writes which trigger data transfer requests controlling the transfer controller. The event queue stores event numbers mapped to parameter memory locations storing data transfer parameters. The mapping table and the parameter memory are writeable via a memory mapped write operation. Memory protection registers store data indicative of permitted data accesses to the memory map.

Abstract: A data transfer control apparatus includes a channel controller and plural transfer controllers. The channel controller receives, prioritizes and queues data transfer requests. An event to transfer controller table enables recall of a transfer controller number corresponding to the data transfer request. The plural transfer controllers are independent and can operate simultaneously in parallel. Each transfer controller includes a read bus interface and a write bus interface which arbitrate with other bus masters in the case of blocking accesses directed to interfering devices or address ranges.

Abstract: A method for directly destroying one or more virtual resources that reside within a physical adapter and that are associated with a virtual host. Specifically, the present invention is directed to a mechanism for sharing conventional Peripheral Component Interconnect (PCI) I/O adapters, PCI-X I/O adapters, PCI-Express I/O adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for host to adapter communications.

Abstract: A method to determine the maximum number of VPNs assignable to plurality of routers in a VPN network. The first step in the method can be specifying a tolerance which is a probability that consumed router memory will exceed available router memory for each router in a plurality of routers. The second step can be computing the consumed router memory on each router in a plurality of routers by summing a route memory, an interface memory, a VPN memory, and a constant memory. The third step can be computing a number [V] of VPNs assigned to the router to insure that, with the specified probability tolerance, the consumed router memory will not exceed the available router memory for each router in a plurality of routers.

Abstract: Cascaded analyzer trace memories are described herein. According to one embodiment, the method comprises receiving a packet stream in a master analyzer and a slave analyzer, wherein the master analyzer includes a first trace memory, and wherein the slave includes a second trace memory. According to one embodiment, the method further comprises determining whether the first trace memory has been filled past a memory address. According to one embodiment, if the first trace memory has not been filled past the memory address, storing one or more packets of the packet stream in the first trace memory. In one embodiment, if the first trace memory has been filled past the memory address, performing the following operations: marking a location in the first trace memory, transmitting a signal to the slave analyzer, and storing one or more packets of the packet stream in the second trace memory.

Abstract: A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.

Abstract: A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.

Abstract: Multiple pipelined Translation Look-aside Buffer (TLB) units are configured to compare a translation address with associated TLB entries. The TLB units operated in serial order comparing the translation address with associated TLB entries until an identified one of the TLB units produces a hit. The TLB units following the TLB unit producing the hit might be disabled.

Abstract: A reconfigurable address generation circuit for image processing is configured to an arbitrary state based on configuration data generates a read address for reading out image data of pixel units having a plurality of rows and columns from a memory which stores image data. As the configuration data, there are set a X, Y count end value of the read out pixel unit, a width value of the image in the memory, and edge information for clip processing. The address generation circuit has X counter; Y counter; an X, Y clip processing circuits which convert the count value of the X, Y counter according to the left, right top and bottom edge information; and an address calcuration circuit which generates the reading out address, based on the count values from the X and Y clip processing circuits and the width value.

Abstract: The present invention provides a high-performance storage access environment to a user who moves around a wide area, while increasing the fault resistance of the system. A plurality of network storages (volumes) is assigned to the user. Then, at the occasion of logging in to a volume by the user, the volume that can be accessed with high performance from a position he made access is located. Addresses at a computer with which user makes access are associated with addresses of the volumes provided by a storage device in advance in an assigned volume management table so as to increase access performance. Then, a management server performs control so that the address of the volume associated with the user access position is returned as a response, at the time of logging in.

Abstract: A method and apparatus for effectively controlling data input to a turbo decoder for decoding forward packet data traffic in a 1xEV-DV mobile station (MS) are disclosed. After received code symbols are stored in one of several memories and read in deinterleaving order, read addresses and chip select signals are generated for the memories based on encoder packet size in synchronization to a decoder clock signal. The decoding starts by inputting a predetermined number of code symbols to the turbo decoder in an appropriate order. The decoder input apparatus reads demodulated forward packet data from decoder input buffers in an appropriate order using the read addresses and chip select signals to generate turbo decoder input data in an appropriate form. Thus, a small-size, low-cost, low-power consumption MS is achieved by processing channel-interleaved data at high speed and with reduced process delay and providing them to a decoder.

Abstract: The present invention, generally speaking, provides a hierarchy of configuration storage. The highest level of the hierarchy is an active configuration store; the lowest level is an off-chip configuration store; in between are one or more levels of configuration stores. Every configuration is promoted from the lowest off-chip level, through each level, up to the highest active level. Each ascending level of the hierarchy has a decreasing latency time required to promote a configuration to the next higher level of the hierarchy, and a decreasing amount of available storage. This separation into levels allows the amount of available storage to be adjusted depending on the inherent latency of the level's storage mechanism, where a longer latency requires a larger cache. This in turn allows the total required storage for a given performance level to be minimized.

Abstract: A method and system are provided for providing a consistent reintegration of a failed primary instance as a new secondary instance with implementation of truncation of log records. Upon failure of a primary instance, a secondary instance may be reassigned as the new primary instance. Prior to reintegration, any portion of the database log of the failed primary that is after the log position of the new primary instance may be truncated, followed by a comparison of the log positions of both the new primary instance and the new secondary instance. In limited circumstances, the truncation of the log data generated by the failed primary instance after the point of failure is possible, and supports reintegration of the failed primary as a new secondary instance with limited overhead.

Abstract: A memory controller receives a logical address of a data unit in a memory and scrambles the logical address according to an address scrambling scheme. The address scrambling scheme maps the logical address to time-multiplexed output of physical address pins of the memory controller. At least one of the physical address pins, which is to be mapped in a time phase in a baseline design, is to be unmapped in a corresponding time phase if a dimensional parameter of the memory changes. The logical address comprises row address bits and column address bits. All of the even row address bits may be mapped in a time phase for outputting the row address, and all of the odd row address bits may be mapped in another time phase for outputting the row address. Thus, configuration flexibility of the memory controller is improved.

Abstract: A mechanism in a multithreaded processor to allocate resources based on configuration information indicating how many threads are in use.

Abstract: A computer-implemented method, apparatus, and computer usable program code are disclosed for migrating a virtual adapter from a source physical adapter to a destination physical adapter in a data processing system where multiple host computer systems share multiple adapters and communicate with those adapters through a PCI switched-fabric bus. The virtual adapter is first caused to stop processing transactions. All in-flight transactions that are associated with the virtual adapter are then captured. The configuration information that defines the virtual adapter is moved from the source physical adapter to the destination physical adapter. The in-flight transactions are then restored to their original locations on the destination virtual adapter. The virtual adapter is then restarted on the destination physical adapter such that the virtual adapter begins processing transactions.

Abstract: A method for directly destroying the resources associated with one or more virtual adapters that reside within a physical adapter is provided. A mechanism is provided for directly destroying the resources associated with one or more virtual adapters that reside within a physical adapter, such as a PCI, PCI-X, or PCI-E adapter.

Abstract: Memory modules having accurate operating parameters stored thereon and methods for fabricating and implementing such devices to improve system performance. Memory modules comprising a number of volatile memory devices may be fabricated. Operating parameters for specific memory devices on the memory module or a specific lot in which the memory devices are fabricated may be stored on a non-volatile memory device on the memory module. A system may be configured in accordance with the operating parameters stored on the non-volatile memory device such that corresponding thresholds are not exceeded.

Abstract: An memory device (HDD) storage system (10) has at least one storing location (16) in which an memory device (18) is received while the memory device is not supplied with an electric power, at least one docking location (22) where the memory device is supplied with the electric power so that data can be stored in the memory device and retrieved from the memory device, and a transport device (30) for transporting the memory device between the shelf (16) and the docking location (22). Alternatively, a switching controller (110) connects a system controller (26) and also a power source (118) to an immovably secured memory device (18).

Abstract: Methods and apparatuses for data ordering in a multi-node system that supports non-snoop memory transactions.

Abstract: A multi-interfaced memory device includes an array of memory cells having a first interface and a second interface. The first interface and the second interface share an address bus and a data bus. One of the interfaces may be a random access memory interface and the second interface may be a paged access interface.

Abstract: A de-coupled memory access system including a memory access control circuit is configured to generate first and second independent, de-coupled time references. The memory access control circuit includes a read initiate circuit responsive to the first time reference and a read signal for generating a read enable signal, and a write initiate circuit responsive to the second time reference and a write signal for generating a write enable signal independent of the read enable signal for providing independent, de-coupled write access to a memory array.

Abstract: A system and method for translating addressing protocols between two types of storage drives in a storage environment is provided. A storage environment may include a JBOD of Serial ATA drives coupled to a host server through an external SCSI connection. The addressing protocol of the host server will typically involve addressing each Serial ATA drive by a unique SCSI target ID. This addressing protocol of the host server is translated to an addressing protocol in which each Serial ATA drive is addressed through unique LUN identifier and a single SCSI target ID, which is the addressing scheme of some SCSI-based peripheral controllers.

Abstract: Since no control of accesses made by a computer as accesses to a storage apparatus is executed, the computer can be used illegally to steal and improperly change data stored in the storage apparatus. Thus, an access-control mechanism external to the computer is constructed to solve this problem. That is to say, the control of accesses is executed in the storage apparatus and a network apparatus for each program executed by the computer. In order to enhance the implementability of such control of accesses, the control is executed without extending a variety of protocols of communications among the computer, the network apparatus and the storage apparatus. By implementing the control of accesses in this way, a program other than programs specified in advance is not capable of making an access to data stored in the storage apparatus. Thus, even if the computer is used illegally, data stored in the storage apparatus can be prevented from being stolen and changed improperly.

Abstract: A method, computer program product, and distributed data processing system that enables host software or firmware to map PCI adapter virtual resources to PCI bus addresses that are associated with a system image is provided. Virtual addresses maintained in a protection table segment assigned to a system image are mapped to physical addresses defined in entries of an address table segment assigned to the system image. Discontiguous memory regions identified in entries of the address table segment may thus be mapped to a contiguous virtual address space.

Abstract: In one embodiment, data carried by a plurality of data tributaries is received. As the data is received, a stored mapping of data tributaries to one or more tributary sets is accessed, and common data tags are assigned to the data carried by ones of the data tributaries mapped to common ones of the one or more tributary sets. The data based on the common data tags is filtered; the filtered data is analyzed; and a result of the analysis is output. Other embodiments are also disclosed.

Abstract: An information processing apparatus is disclosed which includes: a signal processing executing device for executing signal processing on data that has been acquired; a recording device for temporarily recording the data and information so that either the data or the information may be transmitted and received by the signal processing executing device, the information being necessary for the signal processing executing device to execute the signal processing on the data; and a data controlling device for controlling a destination to which to output the data after acquiring the data and the information and determining whether to execute signal processing. When determining that the signal processing is to be executed, the data controlling device writes the data and the information to the recording device. The signal processing executing device acquires either the data or the information from the recording device in order to execute the signal processing on the data.

Abstract: A hierarchical memory access control distinguishes between blocks of data that are known to be sequentially accessed, and the contents of each block, which may or may not be sequentially accessed. If the contents of a block are provided in a sequential manner within the block, but the sequence does not correspond to a higher-level sequence, due to a non-zero offset in the start of the sequence within the block, the memory access control is configured to optimize the use of available memory by signaling when the within-block sequence corresponds to the higher-level sequence. While the within-block sequence differs from the higher-level sequence, access to the buffer is limited to the higher-level partitioning of the buffer. When the within-block sequence corresponds to the higher-level sequence, access to the buffer is provided at the within-block partitioning of the buffer.

Abstract: A method and system in accordance with the present invention comprises a thread stack/thread heap combination, wherein the thread heap is for thread local memory usage and wherein the thread stack and thread heap grow in opposite directions. In the present invention the thread specific heap is allocated next to the thread's stack and grows in the opposite direction from that of the stack. This improvement allows the current space management of thread stacks, which spread out the memory placement of multiple stacks to avoid collision, to also be used for the heaps without additional overhead or complexity. It also allows the existing growth scheme of adding memory pages to the process for the stack to be used again because the growth is simply in the opposite direction. Thread specific heaps eliminate the need for expensive synchronization when allocating from a shared heap in a multiprocessor environment.

Abstract: A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations.

Abstract: A physical area management table (105) and a pointer table (106) are stored in a nonvolatile auxiliary storage memory (107). When a logical-physical conversion table (108) is updated (restored) in a main storage memory (140), the restored area is determined in a re-arrangement way by the pointer table to avoid rewrite concentration on the main storage memory (140). Immediately after data is written in the main storage memory (140), the state of the physical block on the physical area management table (105) is updated. Consequently, even if power interruption occurs, it is possible to reliably judge if the data is valid or not.

Abstract: In a network having transaction acceleration, for an accelerated transaction, a client directs a request to a client-side transaction handler that forwards the request to a server-side transaction handler, which in turn provides the request, or a representation thereof, to a server for responding to the request. The server sends the response to the server-side transaction handler, which forwards the response to the client-side transaction handler, which in turn provides the response to the client. Transactions are accelerated by the transaction handlers by storing segments of data used in the transactions in persistent segment storage accessible to the server-side transaction handler and in persistent segment storage accessible to the client-side transaction handler.

Abstract: Disclosed is a method and system to partition hardware resources between operating systems. A determination is made whether a first PCI resource attached to a line of a bus is to be sequestered to a service operating system (OS). If so, the first PCI resource is sequestered to the service OS. It is next determined whether at least one other PCI resource shares the same line of the bus as the sequestered first PCI resource. If so, the at least one other PCI resource is selected and sequestered to the service OS. The first PCI resource and the other sequestered PCI resource are then hidden from a subsequently loaded host OS.

Abstract: A method, a system, an apparatus, and a computer program product are presented for a fragment caching methodology. After a message is received at a computing device that contains a cache management unit, a fragment in the message body of the message is cached. Subsequent requests for the fragment at the cache management unit result in a cache hit. A FRAGMENTLINK tag is used to specify the location in a fragment for an included or linked fragment which is to be inserted into the fragment during fragment or page assembly or page rendering. A FRAGMENTLINK tag may include a FOREACH attribute that is interpreted as indicating that the FRAGMENTLINK tag should be replaced with multiple FRAGMENTLINK tags. The FOREACH attribute has an associated parameter that has multiple values that are used in identifying multiple fragments for the multiple FRAGMENTLINK tags.

Abstract: An apparatus for setting an enclosure address in a computer system having a plurality of enclosures includes at least one enclosure address control device including input means for changing the enclosure address of an associated enclosure of the plurality of enclosures, a display device for indicating the enclosure address assigned to the associated enclosure, a controller for receiving an enclosure address change input from the input means and a logic device for resetting devices within the associated enclosure. The apparatus further includes a register device for receiving the enclosure address from the controller a predetermined period of time after the controller receives the enclosure address change input from the input means. After the predetermined period of time expires, the controller issues a command to the logic device for resetting the devices within the associated enclosure, to assign the changed enclosure address to the devices.

Abstract: A data processing system and method in which, by way of example, a memory system is coupled to a video game program processing system. The video game program processing system has a predetermined address space for executing programs stored in a program memory portion of the memory system. The contents of a plurality of storage locations determine a configuration of the memory system depending on which of a plurality of different game programs is to be executed by the video game program processing system.

Abstract: Embodiments of the invention achieve data write in an appending manner by conversion from a logical block address to a physical block address in a HDD that has only one storage device and does not have a large-scale cache memory. In one embodiment, a check is made as to whether or not the size of an address translation table in a cache memory exceeds a threshold value. If the size exceeds the threshold value, entries whose number is specified are selected by the LRU method. The selected entries are added to a WRITE buffer, and the address translation table is saved on the HDD by executing WRITE. Seek time of a head at the time of WRITE is reduced, thereby improving WRITE performance. There is produced an effect of building such a snapshot that while a usual access to a HDD volume is allowed, it is possible to make an access to a volume of the snapshot which is a past state of the HDD. Disabling write after writing to the HDD is disabled.

Abstract: A processing device includes a first storage location configured to store a first value associated with a first address space, a second storage location configured to store a second value associated with a second address space, and a third storage location configured to store a third value associated with a third address space. The processing device further includes a memory management unit, which includes a first input configured to receive a first address value associated with a data transfer operation, a second input configured to receive an identifier associated with the data transfer operation, and an address space select module configured to identify a select value from the first value, the second value and the third value based on the identifier. The memory management module further includes an address modification module configured to generate a second address value based on the first address value and the select value.