Abstract: The present invention provides a method for accessing a secure digital (SD) card, which includes a voltage supply pin for receiving voltage supply from a host, at least one ground pin, a clock pin for receiving a clock signal from a host, a command pin for receiving a command from a host, and four data pins for writing data into the SD card or reading data from the SD card. The method includes receiving, via the command pin, an address extension command including a first address from a host, receiving, via the command pin, an access command including a second address from a host, and accessing, via the data pins, at least a memory location of the SD card indicated by a third address, which is a combination of the first address and the second address. The access command indicates an access operation to be performed on the SD card selected from: a single read operation, a single write operation, a multiple read operation, a multiple write operation and an erase operation.

Abstract: Techniques for determining data reduction options may include: receiving first data reduction information regarding compression and deduplication of chunks of a data set; determining, in accordance with the first data reduction information for the data set, first settings denoting whether compression and deduplication are enabled or disabled for the data set; receiving, during a first time period when the first settings are effective, writes directed to the data set; receiving second data reduction information regarding compression and deduplication of chunks of the data set modified by writes during the first time period; and determining, in accordance with the second plurality of data reduction statistics for the data set, second settings denoting whether compression and deduplication are enabled or disabled for the data set.

Abstract: A client identifies a first data unit to be shared from a first file to a second file and sends an operation to copy that indicates the first data unit to be shared. The operation to copy the first data unit from the first file to the second file is received. In response to receiving the operation to copy the first data unit from the first file to the second file, it is determined whether the first data unit can be shared with the second file. In response to determining that the first data unit cannot be shared with the second file, the first data unit is copied to the second file. In response to determining that the first data unit can be shared with the second file, the first data unit is shared between the first file and the second file.

Abstract: A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.

Abstract: This application discloses a resource allocation method, an allocation node, and an access node. The method includes: receiving a service request message sent by an access node, the service request message from the access node indicating a to-be-processed service in the access node, and obtaining work queue status information of a resource node. The method further includes allocating, according to the service request message and the work queue status information, the to-be-processed service to a resource node; receiving allocation, by the access node, of a resource node for the to-be-processed service and generating an allocation result; and sending the allocation result to the access node. The access node further sends a task request to the allocated resource node according to the allocation result.

Abstract: Memory-mapped interfaces for message passing computing systems are provided. According to various embodiments, a write request is received. The write request comprises write data and a write address. The write address is a memory address within a memory map. The write address is translated into a neural network address. The neural network address identifies at least one input location of a destination neural network. The write data is sent via a network according to the neural network address to the at least one input location of the destination neural network. A message is received via the network from a source neural network. The message comprises data and at least one address. A location in a buffer is determined based on the at least one address. The data is stored at the location in the buffer. The buffer is accessible via the memory map.

Abstract: A method, apparatus, computer-readable medium, and/or system described herein may be used to efficiently store, move, and/or process data across a plurality of computing clusters. For example, a computing device may receive an indication of one or more data storage locations within a first cluster of servers and/or an indication of one or more data storage locations within a second cluster of servers. The computing device may generate a data file comprising the indication of the one or more data storage locations within the first cluster of servers and/or the indication of one or more data storage locations within the second cluster of servers. Based on the generated data file, the computing device may generate a job to move data stored at the one or more data storage locations within the first cluster of servers to the one or more data storage locations within the second cluster of servers. Based on the job, the computing device may transmit, e.g.

Abstract: Systems, methods and computer program products using multi-tag storage to enable efficient data compression in caches without increasing a tag/data area overhead. One method can comprise storing compressed versions of data elements in a data array of a cache, with tags for the compressed versions respectively appended to the compressed versions as stored in the data array, and storing hashed versions of the tags in a tag array of the cache, wherein the hashed versions of the tags respectively have fewer bits than the tags. A tag block may store hashed versions of tags corresponding to first and second compressed data elements stored in a cacheline of the cache. Hashed tag entries may be compared with full versions of the tags appended to compressed versions of data elements stored in the data array to prevent false positive cache reads. A compressed identifier (CID) may be stored with the hashed versions of tags in the tag array.

Abstract: Disclosed are systems and methods for managing memory. A memory management system may include a table having multiple virtual memory addresses. Each virtual memory address may correspond to a physical memory address and data that identifies a type of memory device corresponding to the physical memory address. The physical memory device can be used to access the memory device when a table hit occurs.

Abstract: Methods, devices and systems for a compressor and a decompressor for encoding and decoding data in the cache/memory/data transferring subsystem in a computer system or in a communication network are described herein. Example variable-length compressors and decompressors are able to: compress more densely when specific values occur in specific positions in a data block; to improve compression and decompression latency when specific values that appear frequently occur in a data block; to also improve decompression latency by recording the lengths of variable-length encoded values of a compressed data block. The compressor and decompressor are able to support compression and decompression of common compression scenarios that are used in combination with variable-length compression to improve compressibility in the cache/memory/data transferring subsystem in a computer system or in a communication network.

Abstract: A storage system in one embodiment comprises a storage controller and a plurality of storage devices comprising a plurality of memory portions. The storage controller is configured to monitor a plurality of servers for a failure event. The servers store a plurality of copies of the memory portions. The storage controller is further configured to mark as invalid a copy of a memory portion on a failed server, search for and identify a location on an operational server for storing a new version of the copy, and communicate the copy invalidity and the identified location to a client device using the memory portion. The client device is configured to generate the new version of the copy for storage on the operational server, and the storage controller receives a notification from the client device regarding whether the new version of the copy was generated and stored on the operational server.

Abstract: A method, computer program product, and computing system for identifying one or more first layer metadata blocks that map to one or more second layer metadata blocks. A subset of the second layer metadata blocks that map to another second layer metadata block from the one or more second layer metadata blocks may be identified, thus defining one or more redirecting second layer metadata blocks. For each first layer metadata block of the one or more first layer metadata blocks: One or more first layer metadata blocks that map to the one or more redirecting second layer metadata blocks may be determined and the one or more first layer metadata blocks that map to the one or more redirecting second layer metadata blocks may be remapped to map to a target second layer metadata block.

Abstract: The present invention provides a method for managing dynamic memory between a host operating system and a guest operating system in an electronic device for executing a multi-operating system. A method for managing dynamic memory enables, with respect to the available memory state of a host operating system and a guest operating system, direct determination of transmission of guest operating system memory to the host operating system by the guest operating system and recovery of the transmitted memory to the guest operating system and enables a request for execution to the host operating system. Moreover, with respect to memory availability state information of the guest operating system, memory information of the host operating system can be collected at a designated collecting interval by means of a request to the host operating system. Also, the host operating system can allocate dynamic memory of the guest operating system with respect to a request from the guest operating system.

Abstract: Embodiments of the present disclosure relate to a system, a computer program product and a method for synchronizing data between a source disk and a target disk in a cluster by performing synchronization between a source disk and a target disk, the synchronization being performed while a plurality of application I/Os on a plurality of nodes in a cluster are configured to access the source disk; and wherein a coordinator and a plurality of workers in the cluster are configured to manage copying data from the source disk to the target disk.

Abstract: In one embodiment, a system includes host machines that form elements of the virtualization environment, and that include a hypervisor, a user virtual machine (UVM), a connection agent, and an I/O controller. The system further includes a virtual disk comprising a plurality of storage devices, the virtual disk being accessible by all of the I/O controllers. At least one of host machines receives a request associated with one of the elements using an application programming interface (API), and including a context-specific identifier. The host machine determines, using reflection, a type of the context-specific identifier and processes the request based on a mapping, according to the determined type, from the context-specific identifier to a unique identifier associated with the element.

Abstract: A method is used in managing data relocations in storage systems. A request is received to relocate a file system block of a file of a file system. The file includes a set of file system blocks. A determination is made as to whether the file system block has been identified for performing an operation on the file system block. The operation impacts the determination of whether to skip relocating of the file system block. Based on the determination, updating mapping information of the file system block is avoided upon relocation of the file system block.

Abstract: Disclosed embodiments relate to perform operations for receiving and integrating a delta file in a vehicle. Operations may include receiving, at an Electronic Control Unit (ECU) in the vehicle, a delta file, the delta file comprising a plurality of deltas corresponding to a software update for software on the ECU and startup code for executing the delta file in the ECU; executing the delta file, based on the startup code, in the ECU; and updating memory addresses in the ECU to correspond to the plurality of deltas from the delta file.

Abstract: A method is provided for installing or updating software on an electronic device 2 comprising processing circuitry 4 and memory access circuitry 10 to control access to at least one memory unit 6, 8 in response to physically-addressed memory access requests issued by the processing circuitry specifying physical addresses from a physical address space. The method comprises performing an address layout varying process comprising: obtaining at least one seed value; in dependence on the at least one seed value, selecting one of a plurality of software address layouts for code or data associated with the software, each software address layout corresponding to a different layout of the code or data in the physical address space; and triggering the electronic device to write the code or data associated with the software to locations of said at least one memory unit corresponding to the selected software address layout.

Abstract: A method for adjusting a number of logical threads for a component including acquiring a plurality of logical threads that is callable by a component; determining a load state of each logical thread according to a utilization rate of a data processing queue corresponding to each logical thread, the load state including a normal load state and an abnormal load state; determining, according to the load states of the logical threads of the component, whether the number of logical threads of the component needs to be adjusted; and adjusting the number of logical threads of the component according to the determination result if the number of logical threads of the component needs to be adjusted. By using the method and the apparatus, the utilization rate of resources is improved while ensuring real-time calculation of data.

Abstract: Embodiments of the present invention facilitate handling corrected memory errors on kernel text. An example computer-implemented method includes identifying a correctable error (CE) in a physical error location of a memory and a kernel function impacted by the CE. The identified kernel function includes a plurality of instructions including a first instruction of the identified kernel function at a first physical memory location in a first region of the memory. The first region includes the physical error location. The plurality of instruction is loaded to a second region of the memory. The loading includes storing the first instruction of the identified kernel function at a second physical memory location in the second region of the memory. The first physical memory location in the first region of the memory is updated to include an instruction to branch to the second physical memory location in the second region of the memory.

Abstract: A data storage device includes a storage tier and a storage controller operably coupled to the storage tier and configured to be communicatively coupled to a host device. The storage controller includes a first memory operably coupled to the storage controller and configured to store a superseding data structure. The storage controller further includes a second memory operably coupled to the storage controller and configured to store a forward map configured to map a plurality of logical block addresses to physical locations on the storage tier. The storage controller further includes a sifting module configured to sift the forward map based on data contained in the superseding data structure. The storage controller further includes a compression module configured to compress the forward map to generate a compressed forward map.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller configured to control the nonvolatile memory using first data. The controller is configured to write either the first data or second data into the nonvolatile memory based on a total write amount of user data into the nonvolatile memory. The second data is compressed data of the first data.

Abstract: The disclosure describes methods and apparatus for quickly prototyping of a solution developed using one or more sensing devices (e.g., sensors), functional blocks, algorithm libraries, and customized logic. The methods produce firmware executable by a processor (e.g., a microcontroller) on an embedded device such as a development board, expansion board, or the like. By performing these methods on the apparatus described, a user is able to create a function prototype without having deep knowledge of the particular sensing device or any particular programming language. Prototypes developed as described herein enable the user to rapidly test ideas and develop sensing device proofs-of-concept. The solutions produced by the methods and apparatus improve the functioning of the sensor being prototyped and the operation of the embedded device where the sensor is integrated.

Abstract: A computer-implemented method, according to one embodiment, includes: receiving an access request for data in a first block of storage space in memory, and returning the data in the first block of storage space in response to the access request. An identifier at an end of the data in the first block of storage space is also located, and pointers included in a trailer appended to the identifier are used to identify additional blocks of storage space which include data having temporal locality with the data in the first block of storage space. The data in each of the identified additional blocks of storage space is further prepared for use.

Abstract: A system includes a multi-core processor that includes a scheduler. The multi-core processor communicates with a system memory and an operating system. The multi-core processor executes a first process and a second process. The system uses the scheduler to control a use of a memory bandwidth by the second process until a current use in a control cycle by the first process meets a first setpoint of use for the first process when the first setpoint is at or below a latency sensitive (LS) floor or a current use in the control cycle by the first process exceeds the LS floor when the first setpoint exceeds the LS floor.

Abstract: A method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller is coupled to the memory device and configured to access the memory device and establish a physical to logical address mapping table and a logical address section table. The logical address section table records statuses of a plurality of logical address sections. Each status is utilized to indicate whether the physical to logical address mapping table records any logical address that belongs to the corresponding logical address section. The logical address section table includes a plurality of section bits in a plurality of dimensions. When the memory controller receives a write command to write data of a first predetermined logical address, the memory controller determines the section bit of each dimension corresponding to the first predetermined logical address, and accordingly sets a corresponding digital value for each section bit.

Abstract: A method for operating a controller is provided. Program code having internal controller functions is stored on the controller, the program code being equipped with at least one service function. A service configuration for the at least one service function is provided on the controller. The method includes; detecting, in the controller, the service configuration; and executing a service functionality in accordance with the service configuration when the at least one service function is invoked. The service configuration denotes at least one internal controller function which is executed as a service functionality of the corresponding at least one service function. The at least one service function, via the service configuration, provides at least one value for at least one argument of the at least one internal controller function in the controller and/or receives at least one return value of the at least one internal controller function.

Abstract: A system for managing memory resources related to boot, including a memory; a boot configuration circuit, configured to designate one or more memory regions as a first type or a second type, the first type requiring scrubbing before beginning system operation, and the second type permitting scrubbing after beginning system operation; one or more processors, configured to scrub the memory regions of the first type; define a first caching policy of one or more memory regions of the second type; and begin system operation before scrubbing memory regions of the second type.

Abstract: Methods and systems which, for example, reduce energy usage in cache memories are described. Cache location information regarding the location of cachelines which are stored in a tracked portion of a memory hierarchy is stored in a cache location table. Address tags are stored with corresponding location information in the cache location table to associate the address tag with the cacheline and its cache location information. When a cacheline is moved to a new location in the memory hierarchy, the cache location table is updated so that the cache location information indicates where the cacheline is located within the memory hierarchy.

Abstract: A user equipment (UE) receives downlink data using resource blocks in a wireless mobile communication system. The UE receives downlink control information including resource allocation information and downlink data mapped to physical resource blocks (PRBs) based on the downlink control information. The resource allocation information indicates virtual resource block (VRB) allocations for the UE. A resource block pair includes a first resource block associated with a first time slot and a second resource block associated with a second time slot adjacent to the first time slot. The first and second resource blocks are allocated to the same frequency indices. A mapping between VRB pairs and PRB pairs exists such that frequency consecutive VRB pairs are mapped to non-frequency consecutive PRB pairs and that each resource block pair is split so there is a frequency gap between the first and second parts of the resource block pair.

Abstract: A hybrid digital rights management (DRM) system includes a hybrid digital rights management server (RMS server) connected to first and second RMS servers and a client computer. The hybrid RMS server stores a policy mapping table that maps its DRM policies to remote DRM policies on the first or second RMS servers, and can also create policies that satisfy the schema requirements of the first or second RMS server using policies stored in the hybrid RMS server. When the hybrid RMS server receives a document protection request from the client computer, it extracts the filename extension for the document to be protected, and uses the filename extension to select one of the first and second RMS servers as a target RMS server. The document is protected by the target RMS server, and also added to a protected document database on the hybrid RMS server.

Abstract: In one embodiment, a storage drive is configured to receive a selective flush command which causes the storage drive to selectively flush write data which has been identified in connection with the selective flush command, from volatile buffer memory to a nonvolatile storage memory. Conversely, write data stored in the volatile buffer memory which is not identified in connection with the selective flush command, may remain unaffected by the selective flush command, and thus may remain stored in the volatile buffer memory without being flushed to the nonvolatile storage memory as a result of the selective flush command. Other aspects are described herein.

Abstract: A method for accessing a physical region page (PRP) list includes obtaining a PRP address of a PRP list, in which the PRP address has M bits; performing operation to the first N bits of the PRP address and the N+1 th to Mth bits of the PRP address respectively to obtain a page base address if the PRP address is within a page boundary; and performing operation to the first N bits of the PRP address and the N+1 th to Mth bits of the PRP address respectively to obtain next PRP address pointer if the PRP address reaches the page boundary. N is an integer, and M is an integer larger than N.

Abstract: Embodiments are directed to a method of regulating client agent backup jobs in a backup server by defining a server parallelism value specifying a maximum number of active backup jobs that can be simultaneously performed by the backup server, maintaining a plurality of queues in memory and including an active queue storing active backup jobs comprising a number of current backup jobs not exceeding the server parallelism value, and one or more overflow queues storing backup jobs exceeding the server parallelism value, receiving backup job requests from a plurality of clients and processing the received backup job requests through the plurality of queues, and transmitting a hold command to the plurality of clients if the plurality of queues are full. The overflow queues may comprise a wait queue and a sleep queue.

Abstract: The present disclosure provides a method and electronic device for processing information. The method is applied in a solid state storage apparatus which is connected to an electronic device. The solid state storage apparatus supports N logical-address-to-physical-address mapping tables different from each other simultaneously, wherein N is an integer greater than or equal to 1. The method comprises: receiving identity information for a user from the electronic device; determining a first logical-address-to-physical-address mapping table corresponding to the user based on the identity information; and assigning the first logical-address-to-physical-address mapping table to the user.

Abstract: A method for expanding a high-availability server cluster is disclosed. The method includes configuring at least two nodes comprised in a server cluster to be expanded as one or more server units, each server unit consisting of at least two nodes; configuring a newly added node into the server cluster, and configuring the newly added node as at least one newly added server unit in the server cluster; and broadcasting routing information of the newly added server unit. The method realizes an expansion of a server cluster by adding a newly added server unit to the server cluster, i.e., increasing the number of server units in the server cluster, so that the number of sessions and processing performance of the expanded server cluster can be improved, with a relatively low expansion cost.

Abstract: A multicore processor may include multiple processing cores that were previously designated as active cores and at least one processing core that was previously designated as a functional spare. The processor may include an interface to receive, during operation of the processor in an end-user environment, a request to change the designation of at least one of the processing cores. The processor may be to store, into a desired cores configuration data structure in response to the request, data representing a bitmask that reflects the requested change, and to execute a reset sequence. During the reset sequence, the processor may activate, dependent on the bitmask, a processing core previously designated as a functional spare, or may deactivate, dependent on the bitmask, a processing core previously designated as an active core. The processor may include a predetermined maximum number of active cores and a predetermined minimum number of functional spares.

Abstract: A technique for facilitating direct doorbell rings in a virtualized system is provided. A first device is configured to “ring” a “doorbell” of a second device, where both the first and second devices are not a host processor such as a central processing unit and are coupled to an interconnect fabric such as peripheral component interconnect express (“PCIe”). The first device is configured to ring the doorbell of the second device by writing to a doorbell address in a guest physical address space. For security reasons, a check block checks an offset portion of the doorbell address against a set of allowed doorbell addresses for doorbells specified in the guest physical address space, allowing the doorbell to be written if the doorbell is included in the set of allowed doorbell addresses.

Abstract: A method, computer program product, and computer system for receiving, at a computing device, an I/O request directed to a compressed data portion of a storage system. It may be determined whether the I/O request includes one of a first portion of information and a second portion of information. An address of the compressed data portion may be obtained via downward mapping if the I/O request includes the first portion of information. The address of the compressed data portion may be obtained via upward mapping if the I/O request includes the second portion of information. The I/O request may be executed at the compressed data portion.

Abstract: Embodiments describe Object-based Storage Device (OSD) targets that utilize Remote Direct Memory Access (RDMA) to allow the OSD target to directly transfer objects requested by a host system to the memory of host system, thereby bypassing an OSD interface of the host system. One embodiment comprises an OSD target that includes an OSD manager, an RDMA manager, and a non-volatile storage device that stores an object. The OSD manager communicatively couples with an OSD interface of a first host system. The RDMA manager communicatively couples with at least one of a first RDMA interface of the first host system and a second RDMA interface of a second host system. The OSD manager receives an OSD command to retrieve the object from the OSD interface, locates the object at the non-volatile storage device, and provides the object to the RDMA manager. The RDMA manager provides the object to at least one of the first RDMA interface of the first host system and the second RDMA interface of the second host system.

Abstract: A system, method, and computer program product is provided for migrating an application from a source computing environment having a source Operating System (OS) to a target computing environment, the target computing environment having a target OS. The method may include discovering applications and resources on the source computing environment; preparing a migration computing environment having the target OS based on the discovered applications and resources; instantiating a virtual migration sandbox in the migration computing environment; instantiating the application within the virtual migration sandbox; and, capturing in-process and out-of-process calls made by the application during execution; updating the migration computing environment based on the captured in-process and out-of-process calls.

Abstract: A data storage device includes a memory device, an SRAM and a controller. The memory device includes a first buffer configured to store data of a plurality of consecutive logical pages. The SRAM stores a first mapping table. The first mapping table records which logical page the data stored in each physical page of the first buffer directs to. The controller is coupled to the memory device and the SRAM. When the controller performs an erase operation to erase the data stored in the first buffer in response to an erase command, the controller checks whether an interrupt signal or a reset command issued by a host device has been received every time the erase operations of a predetermined number (M) of logical pages have finished. The predetermined number (M) is a positive integer greater than 1.

Abstract: A data storage device includes a nonvolatile memory device including a main map table, the main map table including a plurality of map segments; and a controller comprising a sub map table including only some of the plurality of map segments of the main map table, the controller is suitable for updating access frequencies for the respective map segments of the main map table; and for determining whether to erase a map segment of the sub map table based on the updated access frequencies for the respective map segments.

Abstract: An integrated circuit (IC) is provided. The IC includes a cache memory and an address decoder. The cache memory is divided into a plurality of groups. The address decoder provides a physical address according to an access address. When the access address corresponds to a specific group of the groups of the cache memory, the address decoder changes the access address to provide the physical address, and when the access address corresponds to one of the groups other than the specific group in the cache memory, the address decoder assigns the access address as the physical address.

Abstract: A memory device includes: a memory array comprising a plurality of bit cells arranged along a plurality of rows and along a plurality of columns, respectively; a plurality of row circuits respectively arranged along the plurality of rows; a plurality of column circuits respectively arranged along the plurality of columns; and a control logic circuit coupled to the memory array, and configured to determine respective locations of a first plurality of diagonal bit cells of the memory array for testing the pluralities of the row and column circuits.

Abstract: A semiconductor storage device and a memory system having the same. The semiconductor storage device includes a memory array, an error checking/correction (ECC) element, and a setting element. The ECC element stores generated error correction codes to a storage area. The setting element can set the storage area from the external.

Abstract: A nonvolatile memory system includes: a nonvolatile memory device that includes a nonvolatile memory cell array and a page buffer; and a memory controller that loads into the page buffer mapping data that is stored in the nonvolatile memory cell array, and in response to a logical address received from outside the memory controller, translates the logical address into a physical address based on the mapping data that is loaded into the page buffer.

Abstract: A semiconductor system comprises a nonvolatile memory storing a patch code, the patch code comprising a unique identifier (ID). An internal read only memory (IROM) stores a boot code, the boot code comprising a patch code execution function for executing the patch code and a linked register (LR) address for specifying a storage location where the patch code is to be executed. A static random access memory (SRAM) stores a copy of the patch code at the storage location, the copy of the patch code including the unique ID. A processor executes the copy of the patch code from the storage location. The processor executes the copy of the patch code stored at the storage location in the SRAM according to the comparison result.

Abstract: Embodiments of the present disclosure provide a method and bus for accessing a dynamic random access memory (DRAM). The embodiments include receiving an access instruction, where the access instruction includes an access address, the access address includes a physical address, and a first field and a second field that are additionally set, the first field is used to indicate an interleaving mode, the interleaving mode indicates a manner of selecting an access channel, the second field is used to indicate an interleaving granularity, and the interleaving granularity indicates a capacity of an address space corresponding to the access channel; determining, according to the first field and the second field, the access channel and an address corresponding to the access channel; and accessing the DRAM according to the access channel and the address corresponding to the access channel.