Abstract: An apparatus in one embodiment comprises at least one processing device comprising a processor coupled to a memory, with the processing device being configured to maintain a content-based signature cache for a plurality of data pages. For each of a plurality of read operations to be directed to a distributed content addressable storage (CAS) system, the processing device determines if a data page targeted by the read operation has a corresponding content-based signature in the content-based signature cache. Responsive to the data page having a content-based signature in the content-based signature cache, the processing device identifies a particular storage node that stores the data page in the distributed CAS system, and directs the read operation to the identified storage node using the content-based signature to specify the data page targeted by the read operation. The processing device illustratively comprises a host device coupled to the CAS system over a network.

Abstract: Provided is an enclosure for use in a modular storage system, the enclosure comprising a plurality of drive bays, a controller canister, an expansion canister, and a midplane connecting the drive bays to the canisters, wherein the controller canister occupies a greater volume of the enclosure than the expansion canister.

Abstract: An aspect of implementing globally optimized partial deduplication of storage objects includes gathering pages that share a common feature, dividing the pages into groups based on commonality with corresponding representative pages, where each is assigned as a representative dedupe page for the corresponding groups. For each group in the groups of pages, an aspect also includes writing the pages to a corresponding physical container.

Abstract: Example redundant array of independent disks (RAID) storage systems and methods provide rebuild of logical data groups. Storage devices are configured as a storage array for storing logical data groups distributed among the storage devices. The logical data groups are written in a configuration of RAID stripes in the storage devices. A failed storage device may be rebuilt using the RAID stripes and completed rebuilds of logical blocks may be tracked during the device rebuild process. A logical group rebuild status may be determined by comparing the completed rebuilds of logical blocks to a logical group map. The logical group rebuild status for each logical data group may be provided as complete in response to all logical blocks in the logical data group having been rebuilt. In the event the array rebuild fails, the logical groups that did complete rebuild may be brought online as a partially completed rebuild to prevent the loss of the entire array.

Abstract: Disclosed are a memory system, a memory controller and a method for operating a memory controller. The memory controller manages statuses of respective pages by referring to a first memory and a second memory, the first memory stores a valid page table which includes valid page checking information of the respective pages, and the second memory caches a cache table which includes information for updating a part of the valid page table and has a size smaller than the valid page table, whereby it is possible to improve write performance through effective management of page status information.

Abstract: A data storage system includes a logical space having logical block addresses (LBAs) divided into non-overlapping LBA ranges, and a physical space having pairs of physical bands. The system also includes a map in which first successive alternate LBAs of each different one of the non-overlapping LBA ranges are mapped to successive adjacent physical blocks of a first physical band of each different pair of the pairs of physical bands, and second successive alternate LBAs of each different one of the non-overlapping LBA ranges are mapped to successive adjacent physical blocks of a second physical band of each different pair of the pairs of physical bands. A controller employs the map to concurrently read data from a first physical block of the first physical band of one pair of physical bands and from a first physical block of the second physical band of the same pair of physical bands.

Abstract: Methods, non-transitory machine readable media, and computing devices that provide improved dictionary-based compression are disclosed. With this technology, a first portion of an input data stream is compressed using a first dictionary. A second dictionary is trained when the first dictionary is determined to be stale. The dictionary can be determined to be stale based on a size of the input data stream compressed using the first dictionary or a compression ratio decreasing by a threshold, for example. The first dictionary can be stored with metadata associated with the compressed first portion of the input data stream. Accordingly, this technology improves compression ratios, eliminates the need for reference counting, and facilitates improved reclamation of orphan dictionaries, among other advantages.

Abstract: Virtual computer systems (virtual machines) have become increasingly common with the evolution of virtualization technology, cloud computing, etc. However, as a virtual machine and its associated guest operating system seek to execute and/or access a page of memory through synchronous processes execution of the virtual processor associated with the virtual processing is blocked until the page of memory is locked and available. Accordingly, time is wasted on calls waiting for physical page availability thereby reducing utilization of the host machine and virtual machine respectively. To address this an asynchronous virtual machine environment is established allowing the virtual machine or physical machine to handle additional operations whilst waiting for physical page availability.

Abstract: The described technology is directed towards efficiently invalidating cached data (e.g., expired data) in a hash-mapped cache, e.g., on a timed basis. As a result, data is able returned from the cache without checking for whether that data is expired, (if desired and acceptable), because if expired, the data is only briefly expired since the last invalidation run. To this end, a data structure such as a linked list is maintained to track information representative of hash-mapped cache locations of a hash-mapped cache, in which the information tracks a sequential order of entering data into each hash-mapped cache location. An invalidation run is performed on part of the hash mapped cache, including using the tracking information to invalidate a sequence of one or more cache locations, e.g., only the sequence of those locations that contain expired data.

Abstract: A method is used in managing inline data de-duplication in storage systems. The method receives a request to write data at a logical address of a file in a file system of a storage system. The method determines whether the data can be de-duplicated to matching data residing on the storage system in a compressed format. Based on the determination, the method uses a block mapping pointer associated with the matching data to de-duplicate the data. The block mapping pointer includes a block mapping of a set of compressed data extents and information regarding location of the matching data within the set of compressed data extents.

Abstract: A request is received to retrieve at least a portion of a file from a compressed data archived image stored in a backup storage device. The compressed data archived image comprises a backup of a file system having a number of directories and a number of files. The compressed data archived image comprises a file that includes a compression of the number of files. An address of the at least the portion of the file within the compressed data archived image is determined. The at least the portion of the file is retrieved at the address in the compressed data archived image, without decompressing the compressed data archived image.

Abstract: Devices and techniques for managing flash memory are disclosed herein. A memory controller may receive a first program request comprising first host data to be written to the flash memory. The flash memory may comprise a number of storage units with each storage unit comprising a number of storage sub-units. If the first host data is less than a remainder threshold, the memory controller may generate a first program data unit comprising the first host data and first log data describing the flash memory. The memory controller may program the program data unit to the first storage unit of the flash memory, where the first log data is written to a first storage sub-unit of the number of storage sub-unit. The memory controller may also store an indication that the first storage sub-unit is invalid.

Abstract: A network device determines, based on a size of a lookup value, that the lookup value is to be stored across a set of two or more memory banks including a first memory bank and a second memory bank of a database. A first hash function is for determining locations for storing lookup values entirely in the first memory bank, whereas a second hash function is for determining locations for storing lookup values entirely in the second memory bank. A hash operation is performed on the lookup value using the first hash function to determine a memory location for storing the lookup value. A first segment of the lookup value is stored in the first memory bank at the memory location determined using the first hash function, and a second segment of the lookup value is stored in the second memory bank at the memory location determined using the first hash function.

Abstract: Provided is an enclosure for use in a modular storage system, the enclosure comprising a plurality of drive bays, a controller canister, an expansion canister, and a midplane connecting the drive bays to the canisters, wherein the controller canister occupies a greater volume of the enclosure than the expansion canister.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: The present disclosure provides techniques for managing a cache of a computer system using a cache management data structure. The cache management data structure includes a cold queue, a ghost queue, and a hot queue. The techniques herein improve the functioning of the computer because management of the cache management data structure can be performed in parallel with multiple cores or multiple processors, because a sequential scan will only pollute (i.e., add unimportant memory pages) cold queue, and to an extent, ghost queue, but not hot queue, and also because the cache management data structure has lower memory requirements and lower CPU overhead on cache hit than some prior art algorithms.

Abstract: Disclosed embodiments relate to perform operations for receiving and integrating a delta file in a vehicle. Operations may include receiving, at an Electronic Control Unit (ECU) in the vehicle, a delta file, the delta file comprising a plurality of deltas corresponding to a software update for software on the ECU and startup code for executing the delta file in the ECU; executing the delta file, based on the startup code, in the ECU; and updating memory addresses in the ECU to correspond to the plurality of deltas from the delta file.

Abstract: An aspect includes providing a metadata structure having a logical level that points to a virtual level and a physical level to which the virtual level points. The method also includes storing, at the virtual level, a reference counter for each of a plurality of virtual-level type storage address entries in the metadata structure, and providing a pointer in the metadata structure between each pair of a number of pairs of virtual level address entries in which corresponding pages share a set of common sectors. The reference counter tracks a number of instances in which a corresponding pointer points to a corresponding virtual level address entry. An aspect further includes storing a single instance of the common sectors at the physical level.

Abstract: A controller controls an operation of a semiconductor memory device. The controller includes a request analyzer, a storage, and a garbage collection controller. The request analyzer generates invalid data information, based on an erase request received from a host. The storage stores a garbage collection reference table representing memory blocks excluded from selection as a victim block on which a garbage collection operation is to be performed, based on the invalid data information. The garbage collection controller controls the garbage collection operation on the semiconductor memory device, based on exclusion block information generated according to the garbage collection reference table.

Abstract: A method, a system, and a computer program product for executing a database compression. A compressed string dictionary having a block size and a front coding bucket size is generated from a dataset. Front coding is applied to one or more buckets of strings in the dictionary having the front coding bucket size to generate one or more front coded buckets of strings. One or more portions of the generated front coded buckets of strings are concatenated to form one or more blocks having the block size. Each block is compressed. A set of compressed blocks is stored. The set of the compressed blocks stores all strings in the dataset.

Abstract: Disclosed is a distributed storage system and methods for providing real-time localized data access from different storage nodes of the distributed storage system. Providing the localized data access may include tracking access frequencies with which a file is directly accessed from the different storage nodes, storing a source copy of the file at the first storage node in response to the access frequency at the first storage node being greater than the access frequency at the other storage nodes, caching the file at a second storage node, transferring control over the source copy from the first storage node to a third storage node based on a change to the access frequencies, and validating the cached copy of the file at the second storage node against the source copy at the third storage node prior to responding to a request for the file from the second storage node.

Abstract: A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.

Abstract: A method of repairing an indirect addressing structure of a file system damaged by corruption of a virtual data block (VDB) mapping data stored in corresponding physical data blocks (PDBs) includes scanning PDB descriptors to identify PDBs storing data mapped by the corrupted VDB, where each identified PDB includes a set of PDB entries each having a backward pointer identifying a corresponding VDB entry of a corresponding VDB. The identified PDBs are scanned to identify PDB entries whose backward pointers refer to VDB entries of the corrupted VDB, then a replacement VDB is created by (1) for each of the identified PDB entries, recreating a corresponding VDB entry including a forward pointer to the identified PDB entry, and (2) incorporating the recreated VDB entries into the replacement VDB. The replacement VDB is then incorporated into the indirect addressing structure in place of the corrupted VDB.

Abstract: A device compresses a mapping table in a flash translation layer of a SSD. The mapping table includes mappings between Logical Page Numbers (LPNs) and Physical Page Numbers (PPNs). A base PPN table stores at least one entry including a base PPN common to multiple LPNs. A PPN offset table stores an offset for each mapping. A set of hash functions are duplicated for each entry in the base PPN table. A bit extension unit adds bits to the respective offset in the PPN offset table to provide an extended offset bit. A hash calculator calculates a hash value using the base PPN and one of the hash functions corresponding to the base PPN. An exclusive OR unit outputs a new PNN for each of different LPNs, including the multiple LPNs, by applying an exclusive OR operation to the hash value and the extended offset bit.

Abstract: A Non-Volatile Memory Express (NVMe) data reading/writing method and an NVMe device, where in the method, a transceiver receives an NVMe command from a host into a submission queue (SQ), an SQ control circuit sends the NVMe command in the SQ to an solid state drive (SSD) controller when detecting that the SQ in an SQ cache changes, the SSD controller executes the NVMe command, writes a generated NVMe command response into a completion queue (CQ) using a CQ control circuit, and instructs, by triggering an interrupt, the host to read the CQ such that the host processes the NVMe command response in the CQ. Because both the SQ and the CQ are located in the NVMe device, a central processing unit (CPU) can directly read the NVMe command response in the CQ or directly write the NVMe command into the SQ, thereby further reducing consumption of CPU resources.

Abstract: Computer-implemented methods and systems are provided for managing databases. Consistent with disclosed embodiments, a database system can serve configuration requests received from administration systems using an active cluster of at least two geographically separated computing clusters. Serving configuration request can include updating an active configuration database of the active cluster based on the configuration request. The system can also serve search requests received from user devices that specify a search criterion using a closest one of the geographically separated computing clusters by retrieving items satisfying the search criterion from local copies of a cache replicated across the geographically separated computing clusters. Furthermore, the system can serve transaction requests received from the user devices using the active cluster by updating an active local copy of the cache replicated in the active cluster.

Abstract: Address translation circuitry performs virtual-to-physical address translations using a page table hierarchy of page table entries, wherein a translation between a virtual address and a physical address is defined in a last level page table entry of the page table hierarchy. The address translation circuitry is responsive to receipt of the virtual address to perform a translation determination with reference to the page table hierarchy, wherein an intermediate level page table entry of the page table hierarchy stores an intermediate level pointer to the last level page table entry.

Abstract: In one embodiment, an apparatus includes: a control circuit to enable a comparison circuit based on a dynamic update to a hook table and a patch table; and the comparison circuit coupled to the control circuit to compare an address of a program counter to at least one address stored in the hook table, and in response to a match between the address of the program counter and the at least one address stored in the hook table, cause a jump from code stored in a read only memory to patch code stored in a patch storage. Other embodiments are described and claimed.

Abstract: A memory with a processing in memory architecture and an operating method thereof are provided. The memory includes a memory array, a mode register, an artificial intelligence core, and a memory interface. The memory array includes a plurality of memory regions. The mode register stores a plurality of memory mode settings. The memory interface is coupled to the memory array and the mode register, and is externally coupled to a special function processing core. The artificial intelligence core is coupled to the memory array and the mode register. The plurality of memory regions are respectively selectively assigned to the special function processing core or the artificial intelligence core according to the plurality of memory mode settings of the mode register, so that the special function processing core and the artificial intelligence core respectively access different memory regions in the memory array according to the plurality of memory mode settings.

Abstract: Techniques are disclosed for session control of a client-side native application that utilizes a browser for an authentication process. A login request from the browser is received in a proxy service, which scans the request for a URL redirecting back to the native application. The URL is modified to redirect the login request to a policy endpoint to determine if the request is allowed based on policy applied to the native application and browser. If the request is allowed, the policy endpoint restores the URL redirecting to the native application and bypasses the request to resume normal authentication flow. If the request is prohibited, a failure message is sent to the browser. Some implementations may include injection of browser detection code into the browser to determine which variant of the browser is used and sending the browser data regarding the variant to the policy endpoint for consideration in applying policy.

Abstract: A processing apparatus supporting register renaming is provided with checkpoint circuitry to capture register mapping checkpoints indicative of speculative register mappings between logical registers and physical registers at a given point of speculative execution, and register group tracking circuitry to maintain tracking information for groups of logical registers. The tracking information for a given group indicates whether the given group is a changed group comprising at least one logical register for which a corresponding speculative register mapping has changed since a last checkpoint was captured, or an unchanged group for which none of the logical registers in that group have had their speculative register mappings changed since the last checkpoint was captured. When capturing a new register mapping checkpoint, unchanged groups of logical registers are excluded from the new register mapping checkpoint. This can save power in a register mapping checkpointing scheme.

Abstract: An example method of the present disclosure includes, responsive to a loss of last written page information by a memory system, initiating a last written page search to determine last written page information of a memory device, where the last written page search is initiated via a command from a controller of the memory system to the memory device, responsive to receiving the command, performing the last written page search on the memory device, and providing the last written page information to the controller.

Abstract: A memory controller controls an operation of a memory device including a plurality of planes, based on a request from a host. The memory controller includes a request storage unit and a request controller. The request storage unit stores a plurality of read requests received from the host. The request controller controls the request storage unit to perform a processing operation for a read request that has been map-cache-hit, more preferentially than a pairing operation for multi-plane reading, based on whether the plurality of read requests have been map-cache-hit.

Abstract: A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.

Abstract: A memory system includes a memory device including plural memory blocks storing plural pieces of data classified by a first attribute and a second attribute different from the first attribute, and a controller configured to determine whether each data stored in each page in a first part of a target memory block for garbage collection in the memory device has either the first attribute or the second attribute, to determine that all data stored in a second part of the memory block has one of the first attribute and the second attribute, based on a first attribute page count of the memory block and the number of pages storing data of the first attribute in the first part of the memory block, and to migrate data having one of the first attribute and the second attribute to another memory block.

Abstract: Disclosed embodiments relate to perform operations for receiving and integrating a delta file in a vehicle. Operations may include receiving, at an Electronic Control Unit (ECU) in the vehicle, a delta file, the delta file comprising a plurality of deltas corresponding to a software update for software on the ECU and startup code for executing the delta file in the ECU; executing the delta file, based on the startup code, in the ECU; and updating memory addresses in the ECU to correspond to the plurality of deltas from the delta file.

Abstract: There is disclosed techniques for use in managing data storage in storage systems. For example, in one embodiment, there is disclosed a method comprising receiving a request to store data of a data object in a storage system. The method also comprising determining that at least a portion of the data is to be stored in an uncompressed format in the storage system in response to receiving the request. The method also comprising storing at least a portion of the data in the uncompressed format in an allocation unit of a segment in the storage system such that the stored data in the uncompressed format emulates stored data in a compressed format based on the said determination.

Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.

Abstract: A user equipment (UE) receives downlink data using resource blocks in a wireless mobile communication system. The UE receives downlink control information including resource allocation information and downlink data mapped to physical resource blocks (PRBs) based on the downlink control information. The resource allocation information indicates virtual resource block (VRB) allocations for the UE. Indexes of the PRBs to which the downlink data are mapped are determined based on a mapping relationship between virtual resource blocks (VRBs) and the PRBs. The mapping relationship is defined based on indexes of the VRBs which are mapped to the indexes of the PRBs for a first slot of a subframe and a second slot of the subframe. The indexes of the PRBs for the second slot are shifted with respect to the indexes of the PRBs for the first slot based on a predetermined gap. The mapping relationship includes a transformation of VRB indexes based on a matrix.

Abstract: Distributed computing systems, devices, and associated methods of virtual RDMA switching are disclosed herein. In one embodiment, a method includes intercepting a command from an application in a container to establish an RDMA connection with a remote container on a virtual network. In response to the intercepted command, an RDMA endpoint at a physical NIC of a server is created. The method can also include intercepting another command to pair with a remote RDMA endpoint corresponding to the remote container. The intercepted another command contains data representing a routable network address of the remote RDMA endpoint in the RDMA computer network. Then, the RDMA endpoint created at the physical NIC of the server can be paired with the remote RDMA endpoint using the routable network address of the remote RDMA endpoint.

Abstract: Methods and systems are provided for performing a garbage collection scheme for hybrid address mapping. A controller of a memory system receives data and a logical address for the data from a host device, writes the data in a page of an open log block and performs a garbage collection on a log block and under a certain condition, one or more data blocks, when the open log block is full.

Abstract: An integrated circuit device can comprise addressable memory, and a receiver. Data integrity logic can be coupled to the input data path and configured to receive a data stream having a reference address, and a plurality of data chunks with data integrity codes. Also, the data integrity logic can include a configuration store to store configuration data for the data integrity checking. Also, the integrated circuit can include logic to parse the data chunks and the data integrity codes from the data stream, and logic to compute computed data integrity codes of data chunks in the received data stream, and compare the computed data integrity codes with received data integrity codes to test for data errors in the received data stream. The data integrity logic includes logic responsive to the configuration data that control the data integrity logic. In one aspect, the data integrity data indicates a floating boundary data integrity mode or a fixed boundary data integrity mode.

Abstract: Automated Tiered Storage (ATS) has become widely accepted technique in IT industry. Since IO data has different data densities on storage systems, higher storage capacity and improved performance can be achieved by combining two or more storage device tiers having different performance and cost characteristics. These multiple different storage device tiers can be combined into one automated storage pool, which automatically chooses optimal data placement for achieving both the highest performance and the lowest cost. When the storage device tier information can be stored as metadata for each of the data chunks. When there is a system failure and data needs to recovered, the device tier information metadata can be used to restore data to the predetermined optimum storage device tier of the ATS system which shortens the post-recovery warm-up time.

Abstract: A multi-slice processor comprising a high-level structure and history buffer. Write backs are no longer associated with the history buffer and the history buffer comprises slices determined by logical register allocation. The history buffer receives a register pointer entry and either releases or restores the entry with functional units comprised in the history buffer.

Abstract: A method and memory apparatus that operate to minimize and limit memory initialization time when powering up after an unexpected shutdown. Instead of relying only on a cached log table that is lost when memory powers down unexpectedly, the method and apparatus disclosed herein preserve the information needed to rebuild the log table within predefined memory locations. These predefined locations are optimized such that parallel sensing will capture initialization information for a certain number of word lines across all dies and planes within the memory structure during a single read operation at power up.

Abstract: A variety of applications can include memory systems that have one or more memory devices capable of performing memory operations on multiple blocks of memory in response to a command from a host. For example, improvement in erase performance can be attained by erasing multiple blocks of memory by one of a number of approaches. Such approaches can include parallel erasure followed by serial verification in response to a single command. Other approaches can include sequential erase and verify operations of the multiple blocks in response to a single command. Additional apparatus, systems, and methods are disclosed.

Abstract: The present disclosure provide a method and an apparatus for identifying hotspot intermediate code.

Abstract: Systems and methods for migrating locking data for a file system object within a distributed file system. An example method may comprise: initiating a transfer of locking data from a first node of a distributed file system to a second node of the distributed file system, wherein the locking data is associated with a file system object and comprises a connection identifier indicating a connection between a client requesting a lock and the first node; constructing a modified connection identifier that indicates a connection between the client and the second node; and updating the second node to include the locking data with the modified connection identifier.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for archiving storage volume snapshots. An archive module determines at least one snapshot or point in time copy of data. A metadata module determines metadata for restoring a snapshot or point in time copy. A storage module replicates a snapshot or point in time copy and stores the replicated snapshot or point in time copy and metadata to a target storage location, such as one or more data files in a file system of one or more storage devices from a different vendor than a storage device from which the data was copied. In another embodiment, both the ability to archive a storage volume snapshot and restore a previously archived storage volume snapshot is provided.

Abstract: The invention introduces an apparatus for generating a storage mapping table at least including a direct memory access controller for reading first physical location (PL) information corresponding to a logical location of the storage mapping table; an expanding circuit for obtaining the first PL information and expanding the first PL information into second PL information; and a controller for transmitting the second PL information to a host.