Abstract: A method and system is provided for securing micro-architectural instruction caches (I-caches). Securing an I-cache involves maintaining a different substantially random instruction mapping policy into an I-cache for each of multiple processes, and for each process, performing a substantially random mapping scheme for mapping a process instruction into the I-cache based on the substantially random instruction mapping policy for said process. Securing the I-cache may further involve dynamically partitioning the I-cache into multiple logical partitions, and sharing access to the I-cache by an I-cache mapping policy that provides access to each I-cache partition by only one logical processor.

Abstract: Disclosed is a disk array apparatus which includes disk apparatuses and which reads and writes data of the disk apparatus based on an I/O instruction issued by a host computer, includes: a CPU which carries out a first firmware; a memory which stores the first firmware in a first storage area of physical address space; and a TLB which belongs to the CPU and makes the first storage area of the physical address space of the memory associated with a first logical area of logical address space, wherein in case that the CPU receives a second firmware and an instruction to exchange firmware, the CPU stores the second firmware in a second storage area of the physical address space of the memory, and updates the TLB to make the second storage area associated with the first logical area. A method and program for exchanging firmware are also disclosed.

Abstract: A storage system includes a storage medium configured to store data and a buffer memory configured to buffer data to be written to the storage medium. The storage system further includes a controller configured to selectively transfer the buffered data to the storage medium responsive to an invalidity indicator received from an external source. For example, the invalidity indicator may comprise unwrite information received from an external source, e.g., information that indicates that selected buffered data corresponds to deleted file data.

Abstract: A disk storage system for controlling a plurality of disk devices in multiple disk array systems consisting of disk array switches in a fiber channel connection where the disk devices are organized as multiple logical units. The multiple logical units are mapped between each other to improve high speed operation of the disk storage system and the disk storage system transfers data mutually between the two or more disk array switches improving performance and throughput.

Abstract: Provided is a microcomputer having the improved flexibility in changing correspondences between exception causes and exception vectors. The microcomputer includes: a vector candidate output section capable of outputting a plurality of vector candidates; an address selecting section selecting, as an exception vector, one of the vector candidates according to an exception cause; an instruction execution section starting an exception processing routine by accessing a memory area specified by the exception vector; and a correspondence changing section changing the number of exception causes associated with at least one of address candidates included in the vector candidates.

Abstract: A method of locating a storage device of a number of storage devices is provided. A request for a data item is received. The request includes a globally unique identifier (GUID) that is associated with a user. A start number is generated based on the GUID, and the storage device that stores the data item is located based on the start number. The data item is then read from the located storage device. Other techniques for locating a storage device are also described.

Abstract: Serial number based storage device allocation is disclosed. A serial number associated with the storage device is mapped to a device file associated with the storage device on a host having a connection to the storage device. The serial number is mapped to a device address by which the storage device is known to a library with which the storage device is associated. A request requiring that an available storage device be allocated to service the request is received. The storage device is allocated, based at least in part on the serial number to device file and serial number to device address mappings, to service the request.

Abstract: Disclosed herein is an improved sector remapping method that maps logical sectors into physical sectors in storage disks such as SATA (Serial ATA) drives without reducing either storage capacity or I/O performance efficiency. Under this sector remapping method, logical sectors of data can be written into the physical sectors of a storage device through control frames having padded data or information associated with the padded data, as well as data frames having real data to be stored. With the padded data to be added to the real data, the frames provide multiple physical sectors to be transmitted into the storage device in a single write operation. The sector remapping method can be implemented in a storage bridge coupled to a storage device such as SATA drives.

Abstract: Some embodiments are directed to a technique for storing and/or locating content units stored on an object addressable storage (OAS) system, wherein each content unit is identified by an object identifier. The OAS system may comprise a plurality of zones, each of which stores content units. A mapping process may be defined that maps object identifiers for content units to zones on the OAS system. Thus, the storage location for a content unit on the OAS system may be the zone on the OAS system to which the object identifier for the content unit maps.

Abstract: One implementation of a method for providing backup storage services for encrypted data includes receiving signatures of convergently encrypted portions of data from client computers, determining whether the encrypted portions are already present on a backup storage, and obtaining only the needed portions. Users unassociated with a particular user account are denied access to information backed up in that account. The backup storage also stores password protected key files holding signatures of the unencrypted portions of data. One implementation of a system includes a memory, a single-instance storage circuit, a user account management circuit, and a signature index. The memory holds a user-account database and backup copies of convergently encrypted portions of data. The single-instance storage circuit uses the signature index to prevent duplicative backup copies. The user account management circuit responds to download requests after authenticating the user information associated with the requested data.

Abstract: Systems and/or methods are presented that provide for recording transactions that occur during a write process for the purpose of recovering the transactions in the event of a power loss. In an aspect a system implements an organization that reflects a cache architecture that is organized according to the cache way and set index of each transaction In this regard, the cache way and set index cache architecture provides for a post-power loss search operation that is limited to identifying duplicate locations within the cache-line and keeping only the most recent modification. Thus the system provides pre-organization in terms of self-aggregation by cache way and set index recording that facilitates cache-line eviction processing in the event that the cache is determined to be full.

Abstract: A method of storing data blocks onto sectors of a storage device comprises determining a specific number n of blocks, where n is greater than 1, storing n blocks consecutively onto consecutive sectors, such that each block begins directly after the previous block ends, repositioning the storing at the beginning of the next sector, and storing a further n blocks consecutively onto consecutive sectors, such that each block begins directly after the previous block ends.

Abstract: Disclosed is a system for providing multiple window environments in a mobile computing system and a method thereof, which enables a user to conveniently and selectively use a window system suitable for the use environment. A plurality of sub-window systems having different user interfaces and application programs are installed in separate user partitions provided in a non-volatile memory. If a predetermined event occurs, a currently executing sub-window system, from among the plurality of sub-window systems, is terminated, and a user partition corresponding to the terminated sub-window system is dismounted. Then, a user partition from among the separate user partitions, designated corresponding to the predetermined event is mounted so that the sub-window system of the mounted user partition is executed.

Abstract: Described herein are systems and methods that reduce the latency which may occur when a level one (L1) cache issues a request to a level two (L2) cache, and that ensure that a translation requests sent to an L2 cache are flushed during a context switch. Such a system may include a work queue and a cache (such as an L2 cache). The work queue comprises a plurality of state machines, each configured to store a request for access to memory. The state machines can monitor requests that are stored in the other state machines and requests that the other state machines issue to the cache. A state machine only sends its request to the cache if another state machine is not already awaiting translation data relating to the that request. In this way, the request/translation traffic between the work queue and the cache can be significantly reduced.

Abstract: A data protection method suitable for a plurality of physical blocks mapped to a logical block in a non-volatile memory is provided. The data protection method includes recording data update information in each of the physical blocks for identifying an update relationship of the physical blocks and re-establishing the update relationship of the physical blocks according to the data update information. The data update information is composed of a plurality of words having a circular relationship, and the number of these words is greater than the number of the physical blocks. The data update information is sequentially recorded in each of the physical blocks according to the update relationship and the circular relationship.

Abstract: A computer-readable storage medium stores a program for causing a processor to perform a process including: acquiring a first address that specifies a start address of a first area on the main memory where a target data to be cached is stored and range information that specifies a size of the first area on the main memory; converting the first address into a second address that specifies a start address of a second area on the local memory, the second area having a one-to-n correspondence (n=positive integer) to a part of a bit string of the first address; copying the target data stored in the first area specified by the first address and the range information onto the second area specified by the second address and the range information; and storing the second address to allow accessing the target data copied onto the local memory.

Abstract: A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address.

Abstract: A computerized method for sharing removable storage media in a network, the method comprising associating, in an index entry, a first piece of removable storage media in a first storage device with at least a first storage policy copy and a second storage policy copy; copying, to the first piece of removable storage media, data associated with the first storage policy copy; and copying, to the first piece of removable storage media, data associated with the second storage policy copy.

Abstract: A serial in random out memory circuit has a number of memory cells integrated with write control circuitry for writing a sequence of data inputs to sequential locations in the memory cells. Read control circuitry is integrated to receive address signals from an external device and provide a random access read output from the memory cells, mapped into an address range of the external device. Compared to circuits using discrete components and conventional RAM chips, the integrated SIRO can enable some of the circuitry or external software to be dispensed with and so reduce costs or increase performance. The memory cells can be arranged in a number of blocks, selectable one at a time for mapping to the external device address range.

Abstract: Provided are a computer program product, system and method for managing Input/Output (I/O) requests to a storage device. A write request is received having write data for a logical address in the storage device. A determination is made as to whether preserve mode is enabled. A first entry is located in a volume control table for the logical address indicating a version number of the data in the storage device for the logical address and a first physical location in the storage device having the data for the logical address. The write data is written to a second physical location in the storage device. A second entry is added to the volume control table for the logical address to write in response to determining that the preserve mode is enabled.

Abstract: A method is for recovering a block mapping table in a system including a flash memory device, where the block mapping table utilizes address mapping in accordance with a wear-leveling scheme. The method includes reading block arrangement information from the flash memory device for the wear-leveling scheme, restoring the block mapping table with reference to allocation block information included in the block arrangement information and scanning address allocation information included in spare regions of erased blocks of the flash memory device with reference to erased block information included in the block arrangement information and updating the block mapping table in accordance with the scanned address allocation information.

Abstract: One or more removable storage devices inserted into a computing device store a number of different preinstalled operating system instances. The computing device has a number of logical partitions. Each logical partition is independently executed on the computing device. Each logical partition is mapped to and uses one of the different preinstalled operating system instances. As such, a given preinstalled operating system instance to which a given logical partition is mapped is used by the given logical partition without ever having to be installed on the given logical partition.

Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.

Abstract: A data access method for accessing a non-volatile memory module is provided. The data access method includes configuring a plurality of logical addresses and grouping the logical addresses into logical blocks to map to the physical blocks of the non-volatile memory module, and a host system formats the logical addresses into one partition by using a file system and the partition stores at least one file and a file description block corresponding to the file. The data access method further includes searching an end mark corresponding to entry values of the file description block, setting logical addresses storing the end mark as default pattern addresses, and setting values stored in the logical addresses as default values corresponding to the default pattern addresses. Accordingly, the data access method can divide one partition into a write protect area and a writable area by updating data stored in the default pattern addresses.

Abstract: A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing elements. The processing elements transfer data to and from the memory at the memory address. The memory interface can connect to a host configured to access data in a conventional SDRAM memory device so that the host can access data in the memory.

Abstract: A method for forward recovery of a catalog of a data storage system, comprising providing a recovery catalog and SMF records. In reverse chronological order, the (i)th entry of the record is checked for a data set change command. If none, the next entry is examined. Otherwise, the (j)th data set is identified and checked for inclusion in the recovery catalog. If it already is, the next entry is selected. If not, a data set location record is added. This process is repeated for each entry in the SMF record. Next, a (h)th data set on the (k)th volume is selected and checked for inclusion in the recovery catalog. If that (h)th data set has been added to the recovery catalog, a next data set is selected. Otherwise, a data set location record for the (h)th data set is added. The process is repeated for each data set on each volume.

Abstract: Centralized management of both host-side storage objects on multiple heterogeneous host-side servers and logical data containers on a storage system is performed by a management server. In one embodiment, the management server automatically provisions a logical data container on the storage server according to the storage virtualization strategy without administrator interaction at the storage system. In another embodiment, the management server automatically performs a snapshot operation on logical data containers on the storage system according to the storage virtualization strategy without administrator interaction at the storage system. In another embodiment, the management server centrally monitors for out-of-space events in the storage system and automatically correlates the out-of-space events in the storage system to out-of-space events for the host-side file systems.

Abstract: The invention provides a system and method for storing a copy of data stored in an information store. In one embodiment, a data agent reads one or more blocks containing the data from the information store. The data agent maps the one or more blocks to provide a mapping of the blocks, and transmits the one or more blocks and mapping to a media agent for a storage device. The media agent stores the one or more blocks in the storage device according to the mapping.

Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of any one of a region first table, a region second table, a region third table, or a segment table are obtained. Based on the obtained initial origin address, a segment table entry is obtained which contains a format control and DAT protection fields. If the format control field is enabled, obtaining from the translation table entry a segment-frame absolute address of a large block of data in main storage. The segment-frame absolute address is combined with a page index portion and a byte index portion of the virtual address to form a translated address of the desired block of data. If the DAT protection field is not enabled, fetches and stores are permitted to the desired block of data addressed by the translated virtual address.

Abstract: Methods and structures for mapping of logical to physical block addresses within a disk drive to provide independence of the logical block size and the physical disk block size. The independence of the logical and physical block sizes enables numerous beneficial features to improve disk drive capacity, performance and reliability. In one exemplary aspect, indirect mapping table structures and methods map an LBA to an associated IBA representing a block of the same size as the logical block. The IBA is then converted to a corresponding starting quantum unit of data identified by a QA. The QA is, in turn, converted to a disk block identified by a starting DBA and an offset within that DBA. The disk block may be of variable size and is independent of the size of the identified LBA. Numerous other features are enabled by the logical to physical mapping features hereof.

Abstract: The page table walker is moved from its conventional location in the memory management unit associated with the data processor to a location in main memory i.e. the main memory controller. As a result, an implementation is provided wherein the processing of requests for data could selectively avoid or bypass cumbersome caches associated with the data processor.

Abstract: Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.

Abstract: A configurable memory manager is configurable with various configuration parameters. The configurable memory manager has client ports for receiving requests for accessing memories and memory ports for accessing respective memories. The client and memory ports are each independently configurable to specify the parameter of a data width of the port. The configurable memory manager includes a switch and a translator. The translator translates a virtual address in each of the requests into an identifier of one of the memories and a physical address in the memory. The switch transfers each request from the client port receiving the request to the memory port for accessing the memory identified by the identifier for the virtual address in the request.

Abstract: A servicing daemon is described herein for providing servicing of a running computer system (such as a filer). The servicing daemon resides and executes on the operating system of the filer and communicates across a network with a debugger that resides and executes on a remote administering computer. A debugging session is performed that complies with a protocol relating to the remote accessing of files. The debugging session provides live servicing of an application executing on the filer without requiring an actual corefile (having copied filer memory data) to be created. Rather, the servicing daemon creates a simulated corefile header that is sent to the debugger, receives requests from the debugger, and maps addresses specified in the requests to filer memory addresses. The servicing daemon then reads and retrieves data directly from filer memory at the determined filer memory addresses and sends the data to the debugger for analysis.

Abstract: One embodiment of the invention relates to the transfer of content between a host computer that issues OAS access requests and a block I/O storage system. Specifically, a host computer may issue an access request for a content unit that identifies the content unit is an object identifier. The request may be received by a second server, which may determine the block address(es) on the block I/O storage system at which the content unit is stored. A request may then be sent to the block I/O storage system to retrieve the content stored at the requested block address(es) and the block I/O storage system may return the content.

Abstract: A method for reducing a memory map table search time when employing a semiconductor memory device as a temporary memory of large capacity storage device, and a semiconductor memory device therefore, are provided. A MAP RAM is prepared for storing map table data related to the nonvolatile memory area in the volatile memory area. At an initial power-up operation, it is determined whether a logical address is searched for from the map table data while the map table data existing in a map storage area of the nonvolatile memory area is loaded into the MAP RAM. A physical address corresponding to the logical address is provided as an output, when the logical address is searched for. Search time for a memory map table is reduced and read performance in a high speed map information search is increased.

Abstract: Systems and methods are provided for dynamically allocating a number of bits per cell to memory locations of a non-volatile memory (“NVM”) device. In some embodiments, a host may determine whether to store data in the NVM device using SLC programming or MLC programming operations. The host may allocate an erased block as an SLC block or MLC block based on this determination regardless of whether the erased block was previously used as an SLC block, MLC block, or both. In some embodiments, to dynamically allocate a memory location as SLC or MLC, the host may provide an address vector to the NVM package, where the address vector may specify the memory location and the number of bits per cell to use for that memory location.

Abstract: A signal processing circuit includes a signal processing section which generates first address data and second address data in accordance with data processing, reads data stored in an external memory based on the first address data and the second address data for performing a predetermined processing, and outputs processed data along with the first address data and the second address data, an address conversion section which, receiving the first address data and the second address data input thereto, holds at least 1 bit of the first address and outputs third address data, and also adds the at least 1 bit of the held first address data to the second address and outputs fourth address data, and a data interface which performs a writing operation or a reading operation of the data processed by the signal processing section with respect to the external memory on the basis of a time when the address conversion section outputs the third address data and the forth address data.

Abstract: A write command is received from a host computer at a disk drive having a disk. The write command is associated with a data block and a logical block address of the data block, and a logical sector size of the data block is smaller than a physical sector size of a physical sector on the disk associated with the logical block address. The data block is written to a staging sector located in non-volatile media of the disk drive based at least in part on the logical sector size being smaller than the physical sector size. A write response is sent to the host computer, the write response indicating that the write command has been completed. After sending the write response to the host computer, the data block is written to the physical sector on the disk.

Abstract: Embodiments of the present invention provide a system that maps an N-bit application to virtual memory. The N-bit application may be obtained by porting an M-bit application to an N-bit architecture where N is greater than M. During operation, the system receives a request to map an N-bit application to a computer's virtual memory. The system then maps the N-bit application to a section of virtual memory which begins at a memory address that is greater than or equal to 2M. If the N-bit application accesses a memory address which is less than 2M, the system can generate a trap, thereby facilitating the discovery of M-bit memory references in the N-bit application.

Abstract: Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit.

Abstract: A memory management and writing method for managing a plurality of physical units of a memory chip is provided. The present method includes grouping the physical units into a first physical unit group and a second physical unit group, recording and calculating a first erase count of the first physical unit group and a second erase count of the second physical unit group, and calculating an erase count difference between the first erase count and the second erase count. The present method also includes determining whether the erase count difference is larger than an erase count difference threshold when a write command is received. The method further includes executing a switched writing procedure to write data corresponding to the write command into the memory chip when the erase count difference is larger than the erase count difference threshold. Thereby, the lifespan of the memory chip is effectively prolonged.

Abstract: A device may include a group of requestors issuing requests, a memory that includes a set of memory banks, and a control block. The control block may receive a request from one of the requestors, where the request includes a first address. The control block may perform a logic operation on a high order bit and a low order bit of the first address to form a second address, identify one of the memory banks based on the second address, and send the request to the identified memory bank.

Abstract: A processor device has a data memory with a linear address space, the data memory being accessible through a plurality of memory banks. At least a subset of the memory banks are organized such that each memory bank of the subset has at least a first and second memory area, wherein no consecutive memory block is formed by the second memory areas of a plurality of consecutive memory banks. An address adjustment unit is provided which, when a predefined address range is used, translates an address within the predefined address range to access said second memory areas such that through the address a plurality of second memory areas form a continuous linear memory block.

Abstract: A distributed data processing system executes multiple tasks within a parallel job, including a first local task on a local node and at least one task executing on a remote node, with a remote memory having real address (RA) locations mapped to one or more of the source effective addresses (EA) and destination EA of a data move operation initiated by a task executing on the local node. On initiation of the data move operation, remote asynchronous data move (RADM) logic identifies that the operation moves data to/from a first EA that is memory mapped to an RA of the remote memory. The local processor/RADM logic initiates a RADM operation that moves a copy of the data directly from/to the first remote memory by completing the RADM operation using the network interface cards (NICs) of the source and destination processing nodes, determined by accessing a data center for the node IDs of remote memory.

Abstract: The present invention provides a mechanism for storing and accessing attributes of a data container (e.g., characteristics such as a name of a data container used to perform a lookup operation against the data container) in cache memory within storage systems in a cluster of storage systems. Further, a mechanism is provided so that an attribute of a data container is inserted into a cache memory of preferably one storage system (in the cluster) that caches metadata of the data container (e.g., information describing the data container). As a result, a lookup operation for a data container is directed to and served by the storage system that caches the metadata and the attribute of the data container.

Abstract: A memory access system for accessing a basic input output system (BIOS) program is provided. The memory access system includes a flash memory, a CPU, a peripheral component interconnect (PCI) slave, an address converter and a flash memory controller. The flash memory stores a number of BIOS data of the BIOS program, and each BIOS data corresponds to a default BIOS address and is allocated in a flash memory type BIOS address. The CPU delivers a BIOS access instruction. The BIOS access instruction corresponds to a default target address of the default BIOS addresses. After the PCI slave interprets the BIOS access instruction, the address converter converts the default target address into a flash memory type target address, which is one of the flash memory type BIOS address. The flash memory controller accesses the BIOS data allocated at the flash memory type target address accordingly.

Abstract: Access to a plurality of logical devices is enabled regardless of the number of ports provided in a storage system and the number of logical devices that can be allocated to a single port, thereby improving the usability of the logical devices. A storage system comprises a plurality of logical devices, a target device which is the object of access from a computer, and a juke box system for allocating one of the plurality of logical devices to the target device. The juke box system changes the logical device that is allocated to the target device in accordance with a request from the computer.

Abstract: An information system comprises a host computer; a management computer; and a storage system including a storage controller and a plurality of storage volumes, the storage system configured to provide thin provisioned volumes from the plurality of storage volumes to the host computer for input/output. Each thin provisioned volume includes a plurality of segments which are provided by chunks of the storage volumes in the storage system. The storage controller is configured to assign a chunk to a segment on demand, analyze effectiveness of different chunk sizes for a chunk to be assigned to a segment and provide a report of the analyzed effectiveness to the management computer, and determine a size of a chunk to be assigned to a segment based on input from the management computer after the management computer receives the report of analyzed effectiveness.

Abstract: A controller including an interface module and an index module. The interface module is configured to connect devices. The index module is configured to include, in a table stored in memory, an entry for each of the devices. Each entry includes an address field. The index module is configured to: receive a frame of data including an address of one of the devices; compare the address to the address fields associated with the entries in the table; in response to the address matching one of the address fields, access an index value identifying an entry of the table when the address matches one of the address fields; and in response to the address not matching one of the address fields, generate the index value. The index value is used to connect the device associated with the matching one of the address fields with the one of the devices.