Address Mapping (e.g., Conversion, Translation) Patents (Class 711/202)
  • Patent number: 7984233
    Abstract: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where the files are stored in the memory is maintained within the memory system by its controller, rather than by the host. The file based interface between the host and memory systems allows the memory system controller to utilize the data storage blocks within the memory with increased efficiency.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: July 19, 2011
    Assignee: SanDisk Corporation
    Inventor: Alan W. Sinclair
  • Patent number: 7979670
    Abstract: The present invention is directed toward methods and systems for data de-duplication. More particularly, in various embodiments, the present invention provides systems and methods for data de-duplication that may utilize a vectoring method for data de-duplication wherein a stream of data is divided into “data sets” or blocks. For each block, a code, such as a hash or cyclic redundancy code may be calculated and stored. The first block of the set may be written normally and its address and hash can be stored and noted. Subsequent block hashes may be compared with previously written block hashes.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: July 12, 2011
    Assignee: Quantum Corporation
    Inventors: George Saliba, Theron White
  • Patent number: 7979645
    Abstract: A memory mapping unit requests allocation of a remote memory to memory mapping units of other processor nodes via a second communication unit, and requests creation of a mapping connection to a memory-mapping managing unit of a first processor node via the second communication unit. The memory-mapping managing unit creates the mapping connection between a processor node and other processor nodes according to a connection creation request from the memory mapping unit, and then transmits a memory mapping instruction for instructing execution of a memory mapping to the memory mapping unit via a first communication unit of the first processor node.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: July 12, 2011
    Assignee: Ricoh Company, Limited
    Inventor: Hiroomi Motohashi
  • Patent number: 7979666
    Abstract: A system and method for context-independent coding using frequency-based mapping schemes, sequence-based mapping schemes, memory trace-based mapping schemes, and/or transition statistics-based mapping schemes in order to reduce off-chip interconnect power consumption. State-of-the-art context-dependent, double-ended codes for processor-SDRAM off-chip interfaces require the transmitter and receiver (memory controller and SDRAM) to collaborate using the current and previously transmitted values to encode and decode data. In contrast, the memory controller can use a context-independent code to encode data stored in SDRAM and subsequently decode that data when it is retrieved, allowing the use of commodity memories. A single-ended, context-independent code is realized by assigning limited-weight codes using a frequency-based mapping technique. Experimental results show that such a code can reduce the power consumption of an uncoded off-chip interconnect by an average of 30% with less than a 0.
    Type: Grant
    Filed: December 8, 2007
    Date of Patent: July 12, 2011
    Assignee: William Marsh Rice University
    Inventors: Scott Rixner, Kartik Mohanram, Mihir R. Choudhury
  • Patent number: 7979665
    Abstract: One embodiment of the present invention is directed to providing a software layer that provides a Content Addressable Storage (CAS) capability in a computer system in which the content units are ultimately stored on a block I/O storage system. An application program may issue access requests to content units referring to them via a content address, and the software layer can convert such access requests to block I/O commands to be processed by the block I/O storage system. Thus, a CAS capability can be provided despite the absence of a storage system that provides such a capability natively.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: July 12, 2011
    Assignee: EMC Corporation
    Inventors: Stephen Todd, Michael Kilian
  • Patent number: 7979663
    Abstract: A physical extent assurance unit manages correspondence of a logical disk accessed from a host computer with physical extents. A data pattern generation response unit generates a predetermined data pattern, and returns this data pattern in response to a data request from the host computer. A pattern matching unit checks the data pattern of a storage area every access to storage media or periodically. When the entire area of the assured physical extent defines the predetermined data pattern, the pattern matching unit deleted the logical disk allocation of the assured physical extent.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: July 12, 2011
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Solutions Corporation
    Inventor: Kazusa Tomonaga
  • Patent number: 7975113
    Abstract: The present invention provides a storage control device which enables the time between failures to prolong as much as possible, though it uses HDD's whose mean time between failures is relatively short. The storage control device controls spindle motors in a manner that a spindle motor is rotated regarding the HDD of data which can access from a host computer and a spindle motor is stopped regarding the HDD of data which are clearly judged that a host computer does not access the data. Whether the host computers can access the HDD or not is judged by the fact that whether the memory region (internal logical volume) provided by the HDD is in mapped to the host logical volume or not which is recognized by the host computer and is able to access thereby.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: July 5, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Seiichi Higaki, Hisao Honma
  • Patent number: 7975080
    Abstract: Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: July 5, 2011
    Inventors: Edwin Franklin Barry, Nikos P. Pitsianis, Kevin Coopman
  • Patent number: 7975109
    Abstract: A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses a node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: July 5, 2011
    Assignee: Schooner Information Technology, Inc.
    Inventors: Thomas M. McWilliams, Earl T. Cohen, James M. Bodwin, Ulrich Bruening
  • Patent number: 7975120
    Abstract: A method for allocating memory that is associated with a CAN (controller area network) controller, comprises receiving a data frame comprising an identifier (ID) and data; dynamically allocating a message buffer (MB) within the memory for queuing the data frame; and generating a pointer that points to the MB, where the pointer is accessed via a static location in the memory. A corresponding host interface for the CAN controller can be implemented in IC circuitry, is configured to be coupled to a host CPU and a CAN bus interface, and includes a memory allocation unit for dynamic memory allocation and a memory access controller, coupled to the memory allocation unit and the memory, that is configured to control access to the memory to facilitate transmitting and receiving a multiplicity of data frames over a CAN bus.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: July 5, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Narcizo Sabbatini, Jr., Antonio Mauricio Brochi
  • Publication number: 20110161560
    Abstract: Systems and methods are disclosed to reduce the number of partial logical groups that are erased by writing erase patterns to memory in a non-volatile memory system. When a non-aligned erase command is received, the logical addresses of data associated with the erase command may be marked as erased. If the logical group corresponds to the size of a physical metablock, the controller may also issue a physical erase command for complete logical groups within the erase command. For those parts of the erase command that encompass only partial logical groups, the ranges of the logical block addresses marked for erasure are stored. As subsequent erase commands are received the address ranges of the erase commands are added to the previously stored address ranges. When a set of erase commands spans an entire logical group, the logical group is marked for physical erasure in its entirety.
    Type: Application
    Filed: December 31, 2009
    Publication date: June 30, 2011
    Inventors: Neil D. Hutchison, Alan D. Bennett, Sergey A. Gorobets, Steven T. Sprouse
  • Publication number: 20110161618
    Abstract: A mechanism is provided in a multi-core environment for assigning a globally unique core identifier. A Power PC® processor unit (PPU) determines an index alias corresponding to a natural index to a location in local storage (LS) memory. A synergistic processor unit (SPU) corresponding to the PPU translates the natural index to a first address in a core's memory, as well as translates the index alias to a second address in the core's memory. Responsive to the second address exceeding a physical memory size, the load store unit of the SPU truncates the second address to a usable range of address space in systems that do not map an address space. The second address and the first address point to the same physical location in the core's memory. In addition, the aliasing using index aliases also preserves the ability to combine persistent indices with relative indices without creating holes in a relative index map.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: GREG H. BELLOWS, JASON N. DALE, BRIAN H. HORTON, JOAQUIN MADRUGA
  • Patent number: 7970977
    Abstract: A method of bridging a plurality of buses within a bus bridge can include determining whether a queue of the bus bridge includes a transaction request directed to a restricted address range and, for each received transaction request, determining whether an address to which the transaction request is directed is within the restricted address range. Each transaction request received by the bus bridge can be selectively rejected according to whether the address to which the transaction request is directed is within the restricted address range and whether the queue includes a transaction request directed to the restricted address range.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: June 28, 2011
    Assignee: Xilinx, Inc.
    Inventors: Kam-Wing Li, Ahmad R. Ansari, Sanford L. Helton, Tomai Knopp, Khang Kim Dao, Jeffrey H. Seltzer
  • Publication number: 20110153908
    Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Applicant: Intel Corporation
    Inventors: Andre Schaefer, Matthias Gries
  • Publication number: 20110153925
    Abstract: A memory controller that can determine a swizzling pattern between the memory controller and memory devices. The memory controller generates a swizzling map based on the determined swizzling pattern. The memory controller may internally swizzle data using the swizzling map before writing the data to memory so that the data appears in the correct order at the pins of the memory chip(s). On reads, the controller can internally de-swizzle the data before performing the error correction operations using the swizzling map.
    Type: Application
    Filed: December 22, 2009
    Publication date: June 23, 2011
    Inventors: KULJIT S. BAINS, Joseph H. Salmon
  • Patent number: 7962700
    Abstract: Compressed memory systems are provided to reduce latency associated with accessing compressed memory using stratified compressed memory architectures and memory organization protocols in which a region of compressed main memory is allocated as a direct access memory (DAM) region for storing uncompressed data items. The uncompressed data items in the DAM region can be directly accessed, speculatively, to serve access requests to main memory, requiring access to compressed memory in the event of a DAM miss.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Peter Anthony Franaszek, Luis Alfonso Lastras-Montano, Robert Brett Tremaine
  • Patent number: 7962715
    Abstract: A memory controller includes at least one interface adapted to be coupled to one or more first memory devices of a first memory type having a first set of attributes, and to one or more second memory devices of a second memory type having a second set of attributes. The first and second sets of attributes have at least one differing attribute. The controller also includes interface logic configured to direct memory transactions having a predefined first characteristic to the first memory devices and to direct memory transactions having a predefined second characteristic to the second memory devices. Pages having a usage characteristic of large volumes of write operations may be mapped to the one or more first memory devices, while pages having a read-only or read-mostly usage characteristic may be mapped to the one or more second memory devices.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: June 14, 2011
    Assignee: Rambus Inc.
    Inventor: Frederick A. Ware
  • Patent number: 7962685
    Abstract: A portable data storage device is disclosed which includes an Interface for enabling the portable data storage device to be used for data transfer with a host Computer, and an Interface controller for controlling the interface. There is also a master control unit for controlling the writing of data to and reading data from a non-volatile memory. The non-volatile memory includes at least one single layer cell flash memory and at least one multiple layer cell flash memory. Upon receiving a write instruction, the master control unit determines which of the memories data contained in the instruction should be written to, and writes the data as appropriate similarly, upon receiving a read instruction, the master control unit reads the data from the appropriate one of the memories and transmits the data out of the device.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: June 14, 2011
    Assignee: Trek 2000 International Ltd.
    Inventors: Tsz Kin Clifford Cheung, Teng Pin Poo, Henry Tan
  • Patent number: 7962645
    Abstract: An apparatus, system, and method are disclosed for automatically and transparently mapping tape drives within tape libraries to IP addresses. In one embodiment, the tape library includes, a DHCP server, a LAN to serial switch, and a library manager configured with the necessary modules to map the tape library devices to the proper IP addresses. The entire process may be transparent to users. The result is that the tape library is configured with the proper IP addressing without costly, time-consuming, and error-prone manual intervention. The tape library can be configured more quickly with accurate IP addressing and is able to operate efficiently and properly.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Joseph Whitney Dain, James Arthur Fisher, Raymond Anthony James, David Luciani
  • Publication number: 20110138123
    Abstract: System, method, computer program product embodiments and combinations and sub-combinations thereof for managing data storage as an in-memory database in a database management system (DBMS) are provided. In an embodiment, a specialized database type is provided as a parameter of a native DBMS command. A database hosted entirely in-memory of the DBMS is formed when the specialized database type is specified.
    Type: Application
    Filed: March 17, 2010
    Publication date: June 9, 2011
    Applicant: Sybase, Inc.
    Inventors: Aditya P. Gurajada, Amarnadh Sai Eluri, Vaibhav A. Nalawade, Jian Wu, Daniel Alan Wood, Yanhong Wang
  • Patent number: 7958374
    Abstract: A method for protecting digital information includes: converting a protected address range into a plurality of address blocks based on a preset conversion unit, and generating an address block rearranging rule using the address blocks as a parameter; when it is desired to load data into an address batch of the protected address range, converting the address batch into a plurality address blocks based on the conversion unit; and locating rearranged addresses of the address blocks in the protected address range according to the address block rearranging rule, and loading the data into the rearranged addresses. Thus, the data can be stored in the address batch scatteredly, and the protected data cannot be recomposed into the original correct data when stolen.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: June 7, 2011
    Assignee: Shansun Technology Company
    Inventors: Jing-Shiun Lai, Ling-Ying Nain, Po-Hsu Lin, Sheng-Kai Lin
  • Patent number: 7958330
    Abstract: A compiler program creates a program, which is executed on a platform where use of a pointer is limited and that can perform a pointer operation without specifying addresses allocated to a memory. When a source code, which is related with the pointer operation to be executed for data having references for simultaneously identifying respective data and offset information for simultaneously specifying positions in the data identified by the references, is read, a code for performing the pointer operation using a pseudo-pointer having a predetermined data length is created by the compiler program based on information simultaneously specified by the references for identifying the data and the offset information.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: June 7, 2011
    Assignee: Fujitsu Limited
    Inventor: Seiji Terunuma
  • Patent number: 7958300
    Abstract: Systems and methods for operating upon a mobile communications device. A system and method can be used with data operations with respect to the mobile communications device's memory, wherein the memory has sectors. Data structures are used with the data operations to determine whether a sector contains valid data or to locate a record's pointer in the memory. The data structures can be used for such operations as record creation, record movement, recovery, etc.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: June 7, 2011
    Assignee: Research In Motion Limited
    Inventors: John F. A. Dahms, Anthony F. Scian, Michael J. Carmody
  • Patent number: 7958331
    Abstract: A data storage device comprises storage media including physical data blocks. The data storage device comprises a storage circuit. The storage circuit compresses a user data block into a compressed user data block before storing the compressed user data in one of the physical data blocks, leaving an unused block portion of the physical data block. The data storage device comprises a remapping circuit that remaps the unused block portion to an opportunistic block address. The data storage device comprises a circuit that stores data in the unused block portion.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: June 7, 2011
    Assignee: Seagate Technology LLC
    Inventors: Sami Iren, Erik Riedel
  • Patent number: 7953953
    Abstract: A method and apparatus for reducing a page replacement time in a system using a demand paging technique are provided. The apparatus includes a memory management unit which transmits a signal indicating that a page fault occurs, a device driver which reads a page having the page fault from a nonvolatile memory, and a page fault handler that searches and secures a space for storing the page having the page fault in a memory. The searching and securing of the space in the memory is performed within a limited time calculated beforehand and a part of data to be loaded to the memory of the system is stored in the nonvolatile memory.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: May 31, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-hyun In, Il-hoon Shin, Hyo-jun Kim
  • Patent number: 7952589
    Abstract: A data processing apparatus generates a memory address corresponding to a first memory, and interpolates data read out from the first memory. The data processing apparatus selects a part of the memory address, checks if the first memory stores data corresponding to the selected part of the memory address, and transfers the data, for which it is determined that the first memory does not store the data, and which corresponds to the part of the memory address, from a second memory to the first memory. The data processing apparatus determines to change a part to be selected of the memory address based on the checking result indicating that the first memory does not store the data corresponding to the selected part of the memory address, and changes the part of the memory address corresponding to the characteristics of the memory address.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: May 31, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takayuki Tsutsumi
  • Patent number: 7949913
    Abstract: A method for storing a memory defect map is disclosed whereby a memory component is tested for defects at the time of manufacture and any memory defects detected are stored in a memory defect map and used to optimize the system performance. The memory defect map is updated and the system's remapping resources optimized as new memory defects are detected during operation.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: May 24, 2011
    Assignee: Dell Products L.P.
    Inventors: Forrest E. Norrod, Jimmy D. Pike, Tom L. Newell
  • Patent number: 7949851
    Abstract: Systems and/or methods that facilitate PBA and LBA translations associated with a memory component(s) are presented. A memory controller component facilitates determining which memory component, erase block, page, and data block contains a PBA in which a desired LBA and/or associated data is stored. The memory controller component facilitates control of performance of calculation functions, table look-up functions, and/or search functions to locate the desired LBA. The memory controller component generates a configuration sequence based in part on predefined optimization criteria to facilitate optimized performance of translations. The memory controller component and/or associated memory component(s) can be configured so that the translation attributes are determined in a desired order using the desired translation function(s) to determine a respective translation attribute based in part on the predefined optimization criteria. The LBA to PBA translations can be performed in parallel by memory components.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: May 24, 2011
    Assignee: Spansion LLC
    Inventors: Walter Allen, Sunil Atri, Robert France
  • Publication number: 20110119455
    Abstract: A method of managing data access of a storage medium includes establishing an address mapping table to record a physical address of a first data stored in the storage medium, where the physical address of the first data is mapped to a logical address of the first data; and when receiving a command for handling the first data stored in the storage medium internally, processing the address mapping table to serve the command without physically accessing the first data stored in the storage medium.
    Type: Application
    Filed: November 16, 2009
    Publication date: May 19, 2011
    Inventors: Jeng-Horng Tsai, Hong-Ching Chen
  • Publication number: 20110119464
    Abstract: A data storage system is disclosed comprising a non-volatile memory and a first interface operable to receive a write command from a host, the write command comprising a host write data block having a host logical block size. A block mapping bridge divides the host write data block into a plurality of transfer data blocks, wherein each transfer data block having a device logical block size smaller than the host logical block size. The transfer data blocks are transmitted through a second interface to control circuitry that accumulates the transfer data blocks into a physical data block having a device physical block size equal to a first integer multiple of the device logical block size, wherein the host logical block size is a second integer multiple of the device physical block size. The physical data block is then written to the non-volatile memory.
    Type: Application
    Filed: November 13, 2009
    Publication date: May 19, 2011
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Christopher P. Karr, Richard J. Procyk
  • Patent number: 7945731
    Abstract: Provided is a database management system obtains storage mapping information which associates addresses in a plurality of physical disk drives within the storage system and addresses in logical disk drives including these physical disk drives, to create queues individually for each of the plurality of physical disk drives. The database management system receives a plurality of read requests which request to read data out of the physical disk drives via the logical disk drives provided by the storage system, sorts the read requests by their destination, and accumulates the read requests in the respective queues associated with the request destination physical disk drives. The database management system reallocates the accumulated read requests into an order that shortens the data read time in each physical disk drive, and then issues the read requests to the storage system.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: May 17, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Seisuke Tokuda, Akira Shimizu
  • Patent number: 7945760
    Abstract: Techniques are described for efficient reordering of data and performing data exchanges within a register file or memory, or in general, any device storing data that is accessible through a set of addressable locations. In one technique, an address translator is placed in the path of all or a selected set of address busses to a storage device to provide a programmable translating of the storage device addresses. An effect of this translation is that the data stored in one pattern may be accessed and stored in another pattern or accessed, processed and stored in another pattern. The address translation operation may be carried out in a single cycle, does not involve the physical movement of data in swap operations, allows data to effectively be ordered more efficiently for algorithmic processing and therefore saves power. Address translation functions are shown to be useful for vector operations and a new type of storage unit using built in address translation functions is presented.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: May 17, 2011
    Assignee: Altera Corporation
    Inventors: Edwin Franklin Barry, Gerald George Pechanek
  • Publication number: 20110113213
    Abstract: A packed command can be received at a storage device. The packed command can include an indicator of a source data location in the storage device and an indicator of a destination data location in the storage device. In response to receiving the packed command, a storage map table in the storage device can be updated. Also, a storage processing guide can be sent to a storage device. The processing guide can include a stream indicator associating the processing guide with a storage command stream. A set of storage commands can also be sent to the storage device. One or more of the commands in the set can each include a stream indicator that matches the stream indicator in the processing guide and identifies the command with the stream.
    Type: Application
    Filed: November 9, 2009
    Publication date: May 12, 2011
    Applicant: Microsoft Corporation
    Inventors: Nathan Steven Obr, Andrew Herron
  • Publication number: 20110113183
    Abstract: A method for managing a non-violate memory is provided. The non-violate memory has a number of blocks, and each block has a number of sub-blocks. The method includes a number of steps. First, a last physical address is obtained. The last physical address corresponds to a sub-block which is close to another sub-block where data is newly stored. Next, it is determined, for each sub-block of at least one block, the validity of data being stored. The at least one block is at least one neighboring block of a block containing the corresponding sub-block of the last physical address. Then, a mapping table is produced according to the step of determining the validity of data.
    Type: Application
    Filed: November 9, 2009
    Publication date: May 12, 2011
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tsung-Hsi Lee, Wen-Jun Zeng, Chung-Ning Huang, Shin-Hui Huang
  • Patent number: 7941631
    Abstract: In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: May 10, 2011
    Assignee: Intel Corporation
    Inventors: David Champagne, Abhishek Tiwari, Wei Wu, Christopher J. Hughes, Sanjeev Kumar, Shih-Lien Lu
  • Patent number: 7941597
    Abstract: Embodiments of the present invention provide a media library controller that can communicate with multiple physical libraries that are physically separate from each other. The media library controller can maintain a virtualized aggregate media library representing the physical media libraries with which it is in communication. From the physical media libraries, the media library controller can establish a virtual media library and associate a host with the virtual media library. The virtual media library can represent the portions of a physical media library to which the host is allowed access.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: May 10, 2011
    Assignee: Crossroads Systems, Inc.
    Inventors: William H. Moody, II, Robert Sims
  • Patent number: 7941602
    Abstract: A method, apparatus and program storage device for providing geographically isolated failover using instant RAID swapping in mirrored virtual disks are disclosed. The closed loop control mechanism provides not only continuous self-tuning to the storage system, but also allows the system to perform the initial configuration better.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: May 10, 2011
    Assignee: Xiotech Corporation
    Inventor: Todd R. Burkey
  • Publication number: 20110107037
    Abstract: According to one embodiment, an information processing apparatus includes memory modules, a measuring module, a determination module, and a controller. The measuring module initializes the memory modules when the apparatus has been booted and an operating system of the information processing apparatus has not yet been started, measures a temperature of the memory modules at a time of the initialization, and measures a maximum temperature of each of the memory modules when the operating system is running. The determination module determines a first memory module, which has the least difference between the temperature at the time of the initialization and the maximum temperature at the time when the operating system is running, and a second memory module which has the lowest temperature at the time of the initialization. The controller maps memory addresses allocated to the first memory module in the second memory module, based on the temperatures.
    Type: Application
    Filed: July 28, 2010
    Publication date: May 5, 2011
    Inventor: Kazuhiko Yoshida
  • Patent number: 7937513
    Abstract: A method for controlling a storage system including a host computer, and a first and a second storage control apparatuses each receiving a data input/output request from the host computer and executing a data input/output process for a storage device in response to the request, comprises connecting a first communication path between the host computer and the first apparatus; connecting a second communication path between the first apparatus and the second apparatus; receiving by the first apparatus a first data input/output request from the host computer through the first path; when the first apparatus has judged that the first request is not for the first apparatus, transmitting by the first apparatus a second data input/output request corresponding to the first request, to the second apparatus through the second path; and by the second apparatus, receiving the second request and executing a data input/output process corresponding to the second request received.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: May 3, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Ohno, Kouji Arai, Toshio Nakano, Hideo Tabuchi, Akinobu Shimada, Ai Satoyama, Yasutomo Yamamoto, Yoshiaki Eguchi
  • Patent number: 7937527
    Abstract: A disk storage system containing a storage device having a record medium for holding the data, a plurality of storage sub-systems having a controller for controlling the storage device, a first interface node coupled to a computer using the data stored in the plurality of storage sub-systems, a plurality of second interface nodes connected to the storage sub-systems, a switch connecting to a first interface node and a plurality of second interface nodes to perform frame transfer therebetween based on node address information added to the frame. The first interface node has a configuration table to store structural information for the memory storage system and in response to the frame sent from the computer, analyzes the applicable frame, converts information relating to the transfer destination of that frame based on structural information held in the configuration table, and transfers that frame to the switch.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: May 3, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Naoto Matsunami, Takashi Oeda, Akira Yamamoto, Yasuyuki Mimatsu, Masahiko Sato
  • Publication number: 20110099348
    Abstract: Embodiments are disclosed herein that are related to controlling the visibility of a portion of memory in a hardware device. For example, one disclosed embodiment provides a hardware device comprising a communications interface configured to connect to a complementary communications interface on a computing device. The hardware device further comprises a portion of memory having a first ID configured to cause the portion of memory to be visible to a user of the computing device to which the hardware device is connected. Further still, the hardware device comprises instructions stored in the portion of memory which are executable by and transferable to the computing device to cause the installation of a computer program related to the hardware device, and to cause the portion of memory to be hidden from the user of the computing device upon transferring of the instructions to the computing device.
    Type: Application
    Filed: October 26, 2009
    Publication date: April 28, 2011
    Applicant: MICROSOFT CORPORATION
    Inventors: Garret J. Buban, Dominic Lai, Daniel Rosenfeld, Jonathan Westhues
  • Patent number: 7933993
    Abstract: The present invention provides for relocatable virtual ports for accessing external storage.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: April 26, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Harvey K. Skinner
  • Patent number: 7934073
    Abstract: A method for performing a jump and translation state change procedure at the same time is disclosed. The method includes: carrying out a series of instruction processing in a first function in a first translation state; and executing a jump instruction which jumps to a target address in a second function and initiates and completes a translation state change to a second translation state at the same time; wherein an address of a next instruction after the jump instruction is stored as a return address in a first register.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: April 26, 2011
    Assignee: Andes Technology Corporation
    Inventors: Chuan-Hua Chang, Hong-Men Su
  • Patent number: 7934067
    Abstract: Provided is a storage apparatus that stores data update histories using an existing file system without modifying the source code of the existing file system. The storage apparatus includes an I/O command catcher that changes, when an I/O command is issued from a program stored in a memory and arbitrary update data is stored in a data area address corresponding to a buffer address storing the arbitrary update data, authorized access set for the arbitrary update data in a page management unit to readable; and a page exception catcher that issues, when the authorized access of the arbitrary update data is changed to readable, a page exception report, acquires a data area address corresponding to the buffer address storing the arbitrary update data in the address management unit, and stores the update data and its update history in an update queue.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: April 26, 2011
    Assignee: Hitachi, Ltd.
    Inventor: Tadashi Takeuchi
  • Patent number: 7933162
    Abstract: Embodiments are provided that include a row decoder, including a row activation path, having a row address converter with an output coupled to an input of a section replacement detector. Further embodiments provide a method including mapping an external row address to an internal row address, wherein the internal row address comprises a section address, determining whether a section corresponding to the section address includes an error, and if the section includes an error, converting the internal row address to a redundant row address, wherein mapping the external row address to the internal row address is initiated prior to determining whether the section replacement should be performed. Further embodiments include a method for receiving a row address for a row in a memory section including a non-2^n number of normal rows and mapping the row address to a redundant row address by substracting a value from the row address.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: April 26, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Takuya Nakanishi, Takumi Nasu, Yoshinori Fujiwara
  • Patent number: 7934072
    Abstract: A method and apparatus are disclosed for reclaiming solid state storage with limited write cycles such as flash memory. Through the use of shared storage for common data patterns, physical space may be conserved or reclaimed in a solid state device. The apparatus may use internal mappings and/or external device drivers to handle the reclamation of unused space. By enabling reclamation of physical space, the disclosed systems, apparatus, and methods may provide more efficient read and write access and improved wear leveling.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: April 26, 2011
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Jeffrey Hobbet, Takashi Sugawara
  • Publication number: 20110093680
    Abstract: A memory controller implements flexible memory mapping for storage of data units in a memory. The memory controller logically partitions the memory into a plurality of blocks or block segments and manages the storage of data units among the plurality of blocks/block segments. The memory controller can operate in one of three modes: a monolithic mode whereby the memory is modeled as a plurality of blocks, whereby each block is treated as a “monolithic” block; a fragmented mode whereby the memory is modeled as a plurality of blocks segments of varying sizes; and a combined mode whereby the memory is initially partitioned into a plurality of equal-sized blocks, and whereby each block can be used as a monolithic block or a fragmented block comprising a plurality of block segments of different sizes, and wherein monolithic blocks can be converted to fragmented blocks and fragmented blocks can be converted back to monolithic blocks.
    Type: Application
    Filed: October 15, 2009
    Publication date: April 21, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Clovis Lacava Lordello, Jose M. Furtado, Reginaldo Hilario Gabarrao, Silvio Luiz Lima Nogueira
  • Publication number: 20110093675
    Abstract: A method for protecting redundant data is provided. In the present invention, when a working data area and a redundant data area are not destroyed, whether global unique identifiers (GUIDs) of both the working data area and the redundant data area are the same is determined when a power on self test (POST) is executed. If the GUIDs are different, the data of the working data area is synchronized to the redundant data area. Next, the working data area and the redundant data area are set to share the same memory address space. One of the working data area and the redundant data area is selected for mapping to the memory address space in case that an operating system is executed.
    Type: Application
    Filed: April 26, 2010
    Publication date: April 21, 2011
    Applicant: INVENTEC CORPORATION
    Inventors: Ying-Chih Lu, Yu-Hui Wang
  • Patent number: 7930689
    Abstract: Systems, methods, and storage media for accessing indirect memory in Java applications are provided. In some embodiments, a storage medium is provided that comprises Java application software that performs one or more operations on an indirect memory of a device. The software comprises instructions that create an instance of a Java class representing the indirect memory, and instructions that access a memory element of the indirect memory using an element unique identifier (“euid”) of the memory element. Other embodiments provide a method for accessing memory elements of a device that comprises creating an instance of a Java class representing the memory elements, and accessing a memory element of the memory elements using an element unique identifier (“euid”) of the memory element, wherein the memory elements are not mapped into the data memory space of the processor.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: April 19, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Gilbert Cabillic, Jean-Philippe Lesot, Gerard Chauvel
  • Patent number: 7930275
    Abstract: The present invention relates to a system for restoring a file from a snapshot, where a version of the file exists in both an active file system and the snapshot. A twin inode is created in the active file system and comparisons are made between block pointers of the twin inode and the snapshot. If there is a match, the block pointer of the twin inode is moved to the active file system. If there is not a match, a determination is made whether the snapshot block pointer exists in the active file system. If the snapshot block pointer does not exist in the active file system, it is copied to the active file system. If it does exist, then the actual data block pointed to by the snapshot block pointer is copied to the active file system. In this way, a file may be restored without the need to always copy every individual data block or inode from the snapshot.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: April 19, 2011
    Assignee: NetApp, Inc.
    Inventors: Raymond C. Chen, Kayuri Patel, Andy C. Kahn, John K. Edwards