Abstract: According to one embodiment, a memory controller comprises a counter and a setting module. The counter is configured to count the number of valid pages in a block includes a page to be invalidated, when data is written in a nonvolatile memory. The setting module is configured to set the block as an object of compaction when the number of valid pages counted by the counter is smaller than a predetermined number.

Abstract: Disclosed is a method and a SAS controller device that abstract access from one or more virtual machines operating on a host system to SAS physical devices connected to the SAS controller without a routing table for port-to-port messaging on the SAS controller. An embodiment may create a virtual expander for each physical port of the SAS controller and further create virtual ports within the virtual expanders to provide abstracted access to SAS physical devices for the virtual machines. The SAS physical devices may be replicated/cloned within the virtual ports. Each replicated/cloned SAS physical device may be assigned a unique SAS address for the SAS controller (i.e., unique for the SAS controller such that other replicates/clones on other virtual ports have a different SAS address).

Abstract: A magnetic disk device includes a disk that includes a plurality of tracks and magnetically stores therein data; a magnetic head that reads and writes data on the tracks; a data writing unit that classifies sectors along one track into a plurality of sector groups and writes to a physical address of each of the sector groups data of a logical address that is different from a logical address corresponding to the physical address in same track; and a first nonvolatile memory that stores therein a conversion table of the logical address and the physical address.

Abstract: A method can include associating a bin access value with each data storage bin of a plurality of data storage bins after a current time window ends; mapping each data storage bin of the plurality of data storage bins to a storage tier of a hierarchy of storage tiers, based on the bin access value associated with the data storage bin, such that a bin access value associated with each data storage bin mapped to a storage tier is greater than or equal to a bin access value associated with each data storage bin mapped to a next highest-performing storage tier; causing data associated with each data storage bin of the plurality of data storage bins to be migrated to the storage tier to which the data storage bin is mapped; and, when a data storage bin was not mapped to a current storage tier after a previous time window ended, automatically determining a time weighting factor to be applied to an access frequency associated with a time window.

Abstract: A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security.

Abstract: Systems and methods for consistent logical volume management of the storage subsystem. The present invention guarantees permanent identification data consistency while migrating, mirroring, creating, deleting LU and so on. It prevents the administrator from the change of management.

Abstract: A method and system for transferring data in a multi ordered memory array from a source memory array to a destination memory array, at least one of which is multi-ordered. A reading memory access unit reads data from the source memory array according to a source access template and a writing memory access unit writes the data to the destination memory array according to a destination access template.

Abstract: A programmable logic device includes a hard-logic portion that selectively aggregates bandwidth of data ports and maps logically and physically the transactions from these ports. The memory interface structure is a part of a hard-logic portion that includes random access memories (RAMs), multiplexers, and pointers that allow static or dynamic bandwidth configuration as function of instruments examining the system traffic using queues. The interface allows many initiators having many logical threads to share and use many physical threads in different queue modules.

Abstract: Systems and methods for storage devices are presented. More specifically, in one embodiment a storage device may comprise have an enclosure comprising an interface which may be coupled to an I/O bus of a computing system with which it is being utilized. Commands may be received through the interface and, invisibly to the computing system which issues the commands, translated into a set of commands configured to effectuate the received command in conjunction with one or more storage media coupled to the interface, where this set of commands may also be configured to implement additional functionality such as RAID or data encryption in conjunction with the storage media.

Abstract: Systems, devices and methods for interfacing a single bus with multiple buses invisibly to devices using the single bus are presented. More specifically, in one embodiment an I/O bus may be interfaced with multiple other I/O buses of the same or different formats. Commands may be received on the first I/O bus and invisibly to a computing device or processor which issues the commands, translated into a set of commands configured to effectuate a received command in conjunction with storage media coupled to the other I/O buses. This set of commands may also be configured to implement additional functionality in conjunction with the storage media such as RAID or data encryption.

Abstract: Method and system for supporting multiple byte order formats, separately or simultaneously, are provided and described. In one embodiment, a page attribute table (PAT), which is programmable, is utilized to indicate byte order format. In another embodiment, a memory type range register (MTRR), which is programmable, is utilized to indicate byte order format.

Abstract: The invention provides a system to reclaim space identified as no longer in use and comprises a vLUN, a thinly provisioned mapped LUN, a mapping layer, and a data reduction engine. Chunks of data are stored at logical chunk addresses (LCAs) in the vLUN and are mapped to corresponding physical chunk addresses (PCAs) in the thinly provisioned mapped LUN. The data reduction engine performs a data reduction process on a first logical chunk of data stored at a first LCA in the vLUN, where the first logical chunk has a size that is a nonzero integer multiple of the size of the storage extent of the thinly provisioned mapped LUN. After the data reduction process, the PCA associated with the first logical chunk is no longer needed, and the thinly provisioned mapped LUN is instructed to deallocate the PCA associated with the first logical chunk that is no longer needed.

Abstract: A non-volatile data storage system including a first non-volatile storage medium, a second non-volatile storage medium, and a microprocessor is provided. The first non-volatile storage medium includes a popular data address recording area for recording logic addresses of popular data in the first non-volatile storage medium. The microprocessor is coupled to the first non-volatile storage medium and the second non-volatile storage medium. When the non-volatile data storage system boots up, the microprocessor copies the popular data from the first non-volatile storage medium to the second non-volatile storage medium according to the popular data address recording area. The popular data is accessed in the second non-volatile storage medium instead of the first non-volatile storage medium.

Abstract: Described herein are method and apparatus for using an LLRRM device as a storage device in a storage system. At least three levels of data structures may be used to remap storage system addresses to LLRRM addresses for read requests, whereby a first-level data structure is used to locate a second-level data structure corresponding to the storage system address, which is used to locate a third-level data structure corresponding to the storage system address. An LLRRM address may comprise a segment number determined from the second-level data structure and a page number determined from the third-level data structure. Update logs may be produced and stored for each new remapping caused by a write request. An update log may specify a change to be made to a particular data structure. The stored update logs may be performed on the data structures upon the occurrence of a predetermined event.

Abstract: In a semiconductor memory computer equipped with a flash memory, use of backed-up data is enabled. The semiconductor memory computer includes an address conversion table for detecting physical addresses of at least two pages storing data by designating a logical address from one of logical addresses to be designated by a reading request. The semiconductor memory computer includes a page status register for detecting one page status allocated to each page, and page statuses to be detected include the at least following four statuses: (1) a latest data storage status, (2) a not latest data storage status, (3) an invalid data storage status, and (4) an unwritten status. By using the address conversion table and the page status register, at least two data s (latest data and past data) can be read for one designated logical address from a host computer.

Abstract: A method for rearranging a logical volume including arranging a logical volume rearranging program on a particular server and using the logical volume rearranging program to acquire server/storage mapping information from each server and performance information from each storage subsystem. Moreover, the logical volume rearranging program acquires request I/O (Input/Output) performance and a rearranging rule for each application set by a user. Furthermore, the logical volume rearranging program determines a destination by using the logical volume rearranging destination parity group specified by the user according to the aforementioned information, and rearranges the logical volume according to the storage subsystem performance and the request I/O performance of each application.

Abstract: A method and an apparatus for storing a copy of memory-mapped I/O (MMIO) register are provided for enhancing data processing efficiency. In a structure in which data processing is executed by associating a plurality of logical processors with a physical processor by timing sharing, a host OS stores copy information, namely, shadow, of the MMIO register corresponding to a logical processor in memory both in an active state where a physical processor is allocated to a logical processor corresponding to a guest OS and in an inactive state where no physical processor is allocated to a logical processor. This structure enables a guest OS to gain faster access to the MMIO register through the shadow by memory access, instead of a direct access to the MMIO register, so as to achieve efficient data processing.

Abstract: Methods, systems, and computer program products for improving the efficiency of data transfer within interconnected components of a virtual network, and in particular components of a single physical computing device, where the components exchange data as if they were communicating over an actual communications network using networking protocols. Data packets to be sent from one component to another are buffered by next-hop address (and optionally by final destination address as well) to improve efficiency of packet delivery.

Abstract: An apparatus, system, and method are disclosed for converting a storage request to an append data storage command. A storage request receiver module receives a storage request from a requesting device. The storage request is to store a data segment onto a data storage device. The storage request includes source parameters for the data segment. The source parameters include a virtual address. A translation module translates the storage request to storage commands. At least one storage command includes an append data storage command that directs the data storage device to store data of the data segment and the one or more source parameters with the data, including a virtual address, at one or more append points. A mapping module maps source parameters of the data segment to locations where the data storage device appended the data packets of the data segment and source parameters.

Abstract: A method for storing data in virtual system is described. The method includes selecting virtual blocks in the virtual disk for storage of data based on contiguous logical blocks, in a disk file residing on physical storage media, that are mapped to the virtual blocks.

Abstract: In an embodiment, a method is disclosed that includes, comparing, during a write back stage at an execution unit, a write identifier associated with a result to be written to a register file from execution of a first instruction to a read identifier associated with a second instruction at an execution pipeline within an interleaved multi-threaded (IMT) processor having multiple execution units. When the write identifier matches the read identifier, the method further includes storing the result at a local memory of the execution unit for use by the execution unit in the subsequent read stage.

Abstract: An address translation circuit includes an area address holding section, an invert flag holding section, a match detection section, and a bit conversion section. The area address holding section holds at least part of a translation target address as an area address. The invert flag holding section holds an invert flag specifying whether or not part of said translation target address is to be inverted. The match detection section detects a match between a predetermined part of at least one bit in an input address on the one hand, and said area address held by said area address holding section on the other hand. If a match is detected by said match detection section and if said invert flag held by said invert flag holding section specifies that part of said translation target address is to be inverted, the bit inversion section inverts a predetermined bit part in said input address before outputting the bit-inverted address.

Abstract: A system may comprise one or more source agents, target agents, and a plurality of directory agents, which may determine the target agent to which one or more transactions generated by the source agents is to be sent. A controller may identify one of a plurality of directory agents to process the transactions. The directory agent may determine the control and status registers of the target agents to which the transaction is to be sent. The target agent may complete the transaction after receiving the transaction from the directory agent. The directory agents may store a memory map to resolve the target agent to which the transactions is to be sent. The directory based distributed CSR access may provide scalability to ever increasing number of heterogeneous agents in the system.

Abstract: A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a first level register file having lower access latency and a second level register file having higher access latency. Each of the first and second level register files includes a plurality of physical registers for holding operands that is concurrently shared by a plurality of threads. The processor further includes a mapper that, at dispatch of an instruction specifying a source logical register from the instruction fetch unit to the issue queue, initiates a swap of a first operand associated with the source logical register that is in the second level register file with a second operand held in the first level register file. The issue queue, following the swap, issues the instruction to the execution unit for execution.

Abstract: Exemplary embodiments of the invention provide a method for creating a command device in a storage system in a server virtualization environment. The storage system is coupled to a host computer having a virtual machine. The host computer includes a memory and a processor. The method comprises receiving a command device registration request to register a command device as a storage device for command transmission, the command device to be used in a virtual machine of the host computer; creating a virtual device by allocating a storage area of the storage system to the virtual device; and mounting the virtual device as the command device to the virtual machine in which the command device is used.

Abstract: A flash memory based storage device may utilize magnetoresistive random access memory (MRAM) as at least one of a device memory, a buffer, or high write volume storage. In some embodiments, a processor of the storage device may compare a logical block address of a data file to a plurality of logical block addresses stored in a write frequency file buffer table and causes the data file to be written to the high write volume MRAM when the logical block address of the data file matches at least one of the plurality of logical block addresses stored in the write frequency file buffer table. In other embodiments, upon cessation of power to the storage device, the MRAM buffer stores the data until power is restored, after which the processor causes the buffered data to be written to the flash memory under control of the flash memory controller.

Abstract: The invention describes apparatus and method for receiving and decoding a multiplexed data stream organized in sectors containing payload portions individually destined for one of two or more decoders. The apparatus is connected to a memory device addressable in an address space. At least one of the decoders generates read and/or write addresses from within a predetermined address range that is a true subset of the address space. For avoiding additional memory accesses caused by moving data already contained in the memory into the decoder address range, the apparatus has an address translator which translates the decoder addresses into translated addresses and uses the translated addresses for accessing the memory device.

Abstract: A system configured to optimize access to stored chunks of data is provided. The system comprises a vLUN layer, a mapped LUN layer, and a mapping layer disposed between the vLUN and the mapped LUN. The vLUN provides a plurality of logical chunk addresses (LCAs) and the mapped LUN provides a plurality of physical chunk addresses (PCAs), where each LCA or PCA stores a respective chunk of data. The mapping layer defines a layout of the mapped LUN that facilitates efficient read and write access to the mapped LUN.

Abstract: A data processing apparatus has address translation circuitry which is responsive to an access request specifying a virtual address, to perform a multi-stage address translation process to produce, via at least one intermediate address, a physical address in memory corresponding to the virtual address. The address translation circuitry references a storage unit, with each entry of the storage unit storing address translation information for one or more virtual addresses. Each entry has a field indicating whether the address translation information is consolidated address translation information or partial address translation information. If when processing an access request, it is determined that the relevant entry in the storage unit provides consolidated address translation information, the address translation circuitry produces a physical address directly from the consolidated address translation information.

Abstract: A method for classifying a data packet containing a header is provided. The method may comprise parsing the header of a data packet into header elements. Rules in secondary lookup tables generated from a primary lookup table may be accessed. The respective header elements of the data packet may be compared to the respective fields of each of the secondary lookup tables, and rule results for each of the secondary lookup tables in a combinable format may be generated. In another embodiment, a method for generating secondary lookup tables from a primary lookup table is provided. The method may comprise accessing a primary lookup table defining packet classification rules and generating multiple secondary lookup tables from the primary lookup table. For each secondary lookup table, a selection of classification rules and a selection of fields of the multiple fields based on a rule set identifying predefined entries may be extracted.

Abstract: A pool is replicated in the unit of volume providing the pool, and when a physical device is blocked, any volume blocked in the pool is changed to the replicated volume so that the pool and a virtual volume can be recovered. With such a configuration, when any pool or virtual volume is blocked due to blockage of any volume providing the thin provisioning function, volume recovery can be swiftly performed without changing the virtual volume used by a host computer, and consumption of storage resources needed therefor can be suppressed.

Abstract: A memory architecture is presented. The memory architecture comprises a first memory and a second memory. The first memory has at least a bank with a first width addressable by a single address. The second memory has a plurality of banks of a second width, said banks being addressable by components of an address vector. The second width is at most half of the first width. The first memory and the second memory are coupled selectively and said first memory and second memory are addressable by an address space. The invention further provides a method for transposing a matrix using the memory architecture comprising following steps. In the first step the matrix elements are moved from the first memory to the second memory. In the second step a set of elements arranged along a warped diagonal of the matrix is loaded into a register. In the fourth step the set of elements stored in the register are rotated until the element originating from the first row of the matrix is in a first location of the register.

Abstract: Methods and apparatus for communicating between an access terminal (AT) and an Access Point (AP) are described. For communications over the air link, between an AP and an AT a PN (Pseudo-random Noise) code based address is used as an AP identifier, e.g., address. The PN code based address may be based on Pilot PN code based signals received from an AP. Thus, the PN based AP address may be determined from pilot signals received from an AP. The PN based AP address may be a shortened version of a PN code corresponding to an AP, a full PN code corresponding to an AP, or a value which can be derived in a known manner from a PN code corresponding to an AP.

Abstract: A semiconductor memory device comprises a memory unit having a first and a second port and including plural banks; a bank address conversion circuit operative to convert a first bank address fed from external into a second bank address different from the first bank address and operative to supply the first bank address to one of the first and second ports and supply the second bank address to the other of the first and second ports; and a write data conversion circuit operative to convert input data fed from external into write data different from the input data and operative to supply the input data to one of the first and second ports and supply the converted write data to the other of the first and second ports.

Abstract: A method and apparatus for implementation of error correction code (ECC) checking in non-ECC-compliant components. The method includes receiving a logical address, wherein the logical address maps to first and second physical addresses of a memory. The first and second physical addresses of the memory correspond to memory locations that store data and a corresponding ECC, respectively. The method further comprises translating the logical address into the first and second physical addresses, accessing the data over a data path, separately accessing the ECC over the same data path, and checking the integrity of the data using the ECC.

Abstract: A component of a computing device, such as the kernel of an operating system, is arranged to identify real time processes running on the device and transparently lock the memory owned by such processes to avoid them being paged out. The kernel is also able to inspect all inter-process communications originated by the real time threads running in such processes, in order to ascertain what other processes they invoke, and, if they have the potential to block a real time operation, the kernel is arranged to lock the areas of memory these processes reference. This procedure operates recursively, and ensures that page faults which might affect the operation of any real time process do not occur.

Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.

Abstract: A data item interval identifier lookup method and system is proposed, which is designed for integration to an information processing system for finding which predefined interval the value of an input data item, such as an IP (Internet Protocol) address, belongs. The proposed method and system is characterized by the use of a multi-stage lookup-table data structure having a number of cascaded lookup tables constructed by partitioning the data format of the input data item into a number of segments, each being mapped to one stage of lookup table data structure whose key-value relationships are predefined based on a predefined interval-and-identifier definition table. In operation, the values of the partitioned segments are sequentially used as lookup keys to search through the multi-stage lookup-table data structure until the corresponding interval identifier is found. This feature allows the implementation to have low memory requirement and enhanced system performance.

Abstract: A memory device is provided. The memory device includes a memory array formed by a plurality of multi level cells, a determining circuit and a data reading circuit. The memory array includes a plurality of page units, each including a main data and an auxiliary data corresponding to the main data, wherein the auxiliary data includes a plurality of flag bits. The determining circuit generates a determination bit according to the flag bits. The data reading circuit obtains information corresponding to the main data according to the determination bit.

Abstract: A parallel lookahead pruned bit-reversal interleaver algorithm and architecture have been proposed. The algorithm interleaves a packet of length N in at most log(N)?1 steps compared to N steps using existing sequential algorithms, and has a simple architecture amenable for high-speed applications. The proposed algorithm is valuable for emerging wireless standards especially those that employ PBRI channel (de-)interleavers on long packets in reducing interleaving latency on the transmitter side and deinterleaving latency on the receiver side.

Abstract: System and method for performing optimized restores of a multi-class file system. More actively accessed data may be assigned to higher storage classes and less actively accessed data may be assigned to lower storage classes in the multi-class file system. In a restore, the higher storage class(es) including more actively accessed data may be restored first. The multi-class file system may then be brought online for access by application(s). The lower storage class(es) may then be restored. In one embodiment, if a request for data that have not been restored is received, the file system may obtain an estimated time until restore of the requested data from the restore mechanism. The file system may then notify the application of the estimated time until restore. The application may notify a user of the estimated time, and may generate another request for the data after the estimated time has elapsed.

Abstract: A method of transmitting data between processors, including: establishing and storing an encoding method for each area of virtual address space of a first processor in a predetermined storage device; determining an area of virtual address space corresponding to data to be transmitted to a second processor; and determining the encoding method corresponding to the determined area of the virtual address space with reference to the storage device and transmitting the data to the second processor by using the determined encoding method.

Abstract: Read commands on a mirrored memory computer system are scheduled by utilizing information about pending memory access requests. A conflict queue is configured to track a read/write queue associated with each of a plurality of memory ports on the mirrored memory system. The conflict queue determines a predicted latency on each memory port based on the contents of each of the read/write queues. A compare logic unit is coupled to the conflict queue, wherein the compare logic unit compares a predicted latency of a primary memory and a mirrored memory and schedules read commands to the memory port with the lowest predicted latency.

Abstract: This invention provides a control technique of a data processing system, in which functions of a highly-functional high-performance storage system are achieved in an inexpensive storage system so as to effectively use the existing system and reduce the cost of its entire system. This system has a RAID system, an external subsystem, a management server, a management client and the like. The management server includes an information management table for storing mapping information of the RAID system and the external subsystem. When performing copy process, the pair creation in which a logical volume of the RAID system is set as a primary volume of copy source and a logical volume of a mapping object of the RAID system mapped from the logical volume of the external subsystem is set as a secondary volume of copy destination is executed from the management client by using the information management table.

Abstract: A storage device includes a host interface, a buffer memory, a storage medium, and a controller. The host interface is configured to receive storage data and an invalidation command, where the invalidation command is indicative of invalid data among the storage data received by the host interface. The buffer memory is configured to temporarily store the storage data received by the host interface. The controller is configured to execute a transcribe operation in which the storage data temporarily stored in the buffer memory is selectively stored in the storage medium. Further, the controller is responsive to receipt of the invalidation command to execute a logging process when a memory capacity of the invalid data indicated by the invalidation command is equal to or greater than a reference capacity, and to execute an invalidation process when the memory capacity of the invalid data is less than the reference capacity.

Abstract: There is provided an apparatus for controlling a flash memory, which includes a memory for storing a plurality of flash translation layers; and a control block for, when an access is requested from outside, determining a pattern of the access, selecting one of the flash translation layers stored in the memory based on the determination result, and managing mapping data of the flash memory based on the selected flash translation layer.

Abstract: A buffer management structure for processing systems is described. In one embodiment, the buffer management structure includes a storage module and a control module. The storage module includes a read position and can store a bit indicating a valid state of a transaction request in a write entry. The control module can receive an invalidation request and modify the bit to indicate an invalid state for the transaction request and discard the transaction request when the transaction request is in the read position.

Abstract: A diagnostic tool for identifying a configuration of a private network that may disrupt operations involving communication between two devices on the network. The tool, when run on a device in the network, can identify a “double NAT” configuration in which the device may be separated from other devices on the private network by a NAT device. The tool, when run on a computing device, identifies a NAT device, such as a router, to which the device is connected. The tool then identifies a list containing one or more other devices that may be connected to the NAT device. The tool tests whether these other devices also perform NAT functions and are on the private network. Both the NAT device and the devices that may be connected to the NAT device are identified and a determination is made of whether those devices are on the private network by sending requests using one or more protocols that devices on a private network conventionally use but are not conventionally used by devices on other networks.

Abstract: The present invention is a system and method which allows for a VTL system that supports thin provisioning to implicitly unmap unused storage. Such unmap operations may occur even though the VTL system does not receive any explicit unmap requests from its initiators. For example, if a system administrator knows that once a virtual tape drive of the VTL system has been partially overwritten, all previously written data sets on that virtual tape drive will never again be accessed, the system administrator may configure the VTL system so that it unmaps the entire remainder of the virtual tape drive on the first data overwrite.

Abstract: A method for data distribution, including distributing logical addresses among an initial set of devices so as provide balanced access, and transferring the data to the devices in accordance with the logical addresses. If a device is added to the initial set, forming an extended set, the logical addresses are redistributed among the extended set so as to cause some logical addresses to be transferred from the devices in the initial set to the additional device. There is substantially no transfer of the logical addresses among the initial set. If a surplus device is removed from the initial set, forming a depleted set, the logical addresses of the surplus device are redistributed among the depleted set. There is substantially no transfer of the logical addresses among the depleted set. In both cases the balanced access is maintained.