Abstract: A hybrid recording device having a non-volatile semiconductor memory and a recording magnetic disk includes a mapping unit that maps a first recording area in the recording magnetic disk and a second recording area in the non-volatile semiconductor memory, and a controller that controls an access to the second recording area mapped by the mapping unit when there is an access instruction to the first recording area.

Abstract: Some embodiments provide for a method of mapping a user design to a configurable integrated circuit (IC). The method is for a configurable IC that implements a user design with an associated user design clock cycle. The IC operates on a sub-cycle clock that has multiple sub-cycle periods within a user period of the user design clock cycle. The method identifies multiple port accesses to a first multi-port memory defined in the user design. The accesses are in a single user design clock cycle. The method maps the multiple port accesses to the first multi-port memory to multiple physical-port memory accesses to a second physical-port memory in the configurable IC during multiple sub-cycles associated with a single user design clock cycle.

Abstract: A data backup method for backing up data temporarily stored in a cache memory of a flash memory storage device is provided, where the flash memory storage device has a plurality of physical units. The data backup method includes logically grouping a portion of the physical units into a data area and a cache area. The data backup method also includes determining whether a trigger signal is received; and when the trigger signal is received, copying the data temporarily stored in the cache memory into the cache area. Accordingly, the data backup method can quickly write the data temporarily stored in the cache memory into the physical units, thereby preventing a time out problem which may occur in the flash memory storage device.

Abstract: A flash memory storage system including a flash memory chip, a connector, and a flash memory controller is provided. The flash memory controller configures a plurality of logical addresses and maps the logical addresses to a part of the physical addresses in the flash memory chip, and a host system uses a file system to access the logical addresses. Besides, the flash memory controller identifies a deleted logical address among the logical addresses and marks data in the physical address mapped to the deleted logical address as invalid data.

Abstract: An image processing device includes an input filter configured to control an input process of data to be input as a subject of an image process, an output filter configured to control an output process of data to be output to an outside of the image processing device, a processing filter configured to process the data between the input filter and the output filter, and a pipe configured to transmit the data among the input filter, the processing filter, and the output filter.

Abstract: A method implemented in a computer infrastructure having computer executable code having programming instructions tangibly embodied on a computer readable storage medium. The programming instructions are operable to determine whether a target disk of a map contains data unavailable to a downstream disk from an upstream disk in a FlashCopy cascade and detect whether the downstream disk has a copy of the data. Additionally, the programming instructions are operable to copy the data from the target disk to the downstream disk, if the target disk of the map contains data unavailable to the downstream disk from the upstream disk and the downstream disk does not have the copy of the data. Furthermore, the programming instructions are operable to refrain from copying the data from the target disk to the downstream disk, if the target disk of the map does not contain data unavailable to the downstream disk from the upstream disk or the downstream disk does have the copy of the data.

Abstract: A system, method, and computer program product are provided for sending de-allocation status information. In use, a de-allocation status of at least a portion of memory associated with a logical block address is determined. Additionally, de-allocation status information is generated, based on the determination. Furthermore, the de-allocation status information is sent to a device.

Abstract: Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a user-level request and a logic circuitry (e.g., present in an OSF) may determine the physical address from the shadow address. Other embodiments are also disclosed.

Abstract: A device may include a group of requestors issuing requests, a memory that includes a set of memory banks, and a control block. The control block may receive a request from one of the requestors, where the request includes a first address. The control block may perform a logic operation on a high order bit and a low order bit of the first address to form a second address, identify one of the memory banks based on the second address, and send the request to the identified memory bank.

Abstract: An adapter having a plurality of functions and a plurality of ports, in which the mapping between functions and ports is configurable. In certain embodiments, device memory can be programmed with a desired mapping scheme that overrides a default mapping scheme for the adapter. In certain embodiments, device memory can be reprogrammed with a different desired mapping to enable the adapter to dynamically respond to system conditions.

Abstract: A virtual memory system implementing the invention provides concurrent access to translations for virtual addresses from multiple address spaces. One embodiment of the invention is implemented in a virtual computer system, in which a virtual machine monitor supports a virtual machine. In this embodiment, the invention provides concurrent access to translations for virtual addresses from the respective address spaces of both the virtual machine monitor and the virtual machine. Multiple page tables contain the translations for the multiple address spaces. Information about an operating state of the computer system, as well as an address space identifier, are used to determine whether, and under what circumstances, an attempted memory access is permissible. If the attempted memory access is permissible, the address space identifier is also used to determine which of the multiple page tables contains the translation for the attempted memory access.

Abstract: A multi level cell (MLC) NAND flash memory storage system is provided. A controller of the MLC NAND flash memory storage system declares it a signal level cell (SLC) NAND flash memory chip to a host system connected thereto and provides a plurality of SLC logical blocks to the host system. When the controller receives a write command and a user data from the host system, the controller writes the user data into a page of a MLC physical block and records the page of the SLC logical block corresponding to the page of the MLC physical block. When the controller receives an erase command from the host system, the controller writes a predetermined data into the page of the MLC physical block mapped to the SLC logical block to be erased, wherein the predetermined data has the same pattern as a pattern of the erased page.

Abstract: A request is received from a client machine via a web interface for content presented on a web page. A globally unique identifier (GUID) that is associated with the user is accessed and a number is generated based on the GUID. The generated number is utilized as an index to locate the storage device from the number of storage devices. Here, the storage device stores a user profile associated with the user. The user profile is read from the located storage device and the web page is personalized based on this user profile. The personalized web page is then communicated to the client machine. Other techniques for locating a storage device are also described.

Abstract: Described herein are method and apparatus for using an LLRRM device as a storage device in a storage system. At least three levels of data structures may be used to remap storage system addresses to LLRRM addresses for read requests, whereby a first-level data structure is used to locate a second-level data structure corresponding to the storage system address, which is used to locate a third-level data structure corresponding to the storage system address. An LLRRM address may comprise a segment number determined from the second-level data structure and a page number determined from the third-level data structure. Update logs may be produced and stored for each new remapping caused by a write request. An update log may specify a change to be made to a particular data structure. The stored update logs may be performed on the data structures upon the occurrence of a predetermined event.

Abstract: Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a processor configured to run a multiprocessing, virtual memory operating system. The processor may be operably connected to a memory and may include a cache and a translation lookaside buffer (TLB) configured to store TLB entries. The exemplary system may include a context control logic configured to selectively copy data from the TLB to the data store for a first process being swapped out of the processor and to selectively copy data from the data store to the TLB for a second process being swapped into to the processor.

Abstract: Described embodiments provide logical-to-physical address translation for data stored on a storage device having sectors organized into blocks and superblocks. A flash translation layer maps a physical address in the storage device to a logical sector address. The logical sector address corresponds to mapping data that includes i) a page index, ii) a block index, and iii) a superblock number. The mapping data is stored in at least one summary page corresponding to the superblock containing the physical address. A block index and a page index of a next empty page in the superblock are stored in a page global directory corresponding to the superblock. A block index and a page index of the at least one summary page and the at least one active block table for each superblock are stored in at least one active block table of the storage device.

Abstract: Disclosed are techniques for allowing an increase in topology size of a serial attached SCSI expander network, as well as limiting entries in content addressable memory that are used to store address locations relating to the system topology. In accordance with one method, addresses are provided in the OAF request to reduce lookup table entries. In accordance with another embodiment, address ranges are provided in the lookup table. In addition, virtual memory techniques are used, so that either a software lookup process can be used, or a hardware process can be used, so that only the most recently used addresses are stored in the lookup table.

Abstract: A network element that includes multiple memory types and memory sizes translates a logical memory address into a physical memory address. A memory access request is received for a data structure with a logical memory address that includes a region identifier that identifies a region that is mapped to one or more memories and is associated with a set of one or more region attributes whose values are based on processing requirements provided by a software programmer and the available memories of the network element. The network element accesses the region mapping table entry corresponding to the region identifier and, using the region attributes that are associated with the region, determines an access target for the request, determines a physical memory address offset within the access target, and generates a physical memory address. The access target includes a target class of memory, an instance within the class of memory, and a particular physical address space of the instance within the class of memory.

Abstract: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where the files are stored in the memory is maintained within the memory system by its controller, rather than by the host. The file based interface between the host and memory systems allows the memory system controller to utilize the data storage blocks within the memory with increased efficiency.

Abstract: A method of transferring data from a virtual machine (VM) to a storage virtual appliance (SVA) is disclosed. In this method, the data is transferred to an iSCSI (Internet Small Computer System Interface) device that is coupled to the VM and has a zero copy data mover implementation of a TCP socket interface. The method further includes sending a memory address of the data to the SVA. The SVA includes an iSCSI device having a zero copy data mover implementation of a TCP socket interface to receive the memory address of the data. The VM and the SVA are running in a same hypervisor host.

Abstract: A method and a processing device are provided for mapping a non-page aligned memory buffer to an address space of a process. A beginning portion of a non-page aligned memory buffer and an ending portion of the non-page aligned memory buffer may be copied from respective original memory pages to new memory pages. Unused portions of the new memory pages may be initialized to zeros, ones, or other values. A safe buffer may be created, which resides in the new memory pages and all original memory pages of the non-page aligned memory buffer, except for the original memory pages including either the beginning portion or the ending portion of the non-page aligned buffer. The safe buffer may then be mapped to an address space of a process while avoiding unintended information disclosure.

Abstract: Described are techniques for intermodule communication between a first code module and a second code module wherein one of the first and second code modules executing in user space and the other of the first and second code modules executing in kernel space. A shared memory portion includes storage for one or more commands. A first first-in-first-out (FIFO) structure is used to send a location in the shared memory portion from the first to the second code module. A second FIFO structure is used for sending a location in the shared memory portion from the second to the first code module. The first code module stores command data for a command at a first location in the shared memory portion. A command is issued from the first to the second code module by sending the first location using the first FIFO structure.

Abstract: In one embodiment, in response to receiving a topology change notification at a network bridge having ports identified as either a network port or an edge port, address learning may be disabled on the network bridge. Once address learning is disabled, an association of all entries of a forwarding table of the network bridge having addresses previously forwarded on a particular network port of the network bridge may be changed to forward those addresses on all network ports of the network bridge (e.g., flooding the frames not addressed to edge ports on all network ports only). Subsequently, address learning may be enabled on the network bridge, thus repopulating the network port entries of the forwarding table in response to the topology change.

Abstract: In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described.

Abstract: Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.

Abstract: In certain systems, local requests require corresponding associated information to be present in order to be serviced. A local memory stores some of the associated information. There is latency associated with retrieval of associated information that is not immediately available. Logic operates for each local request to access the local memory to ascertain whether the associated information corresponding to the local request is present. If the associated information is present, a request is placed in an output request queue to service the local request. If the associated information is not present, a request is placed on a bypass path to retrieve the associated information. Requests issue from the bypass path with priority over requests from the output request queue. Useful work is thereby done during the latency of associated information retrieval. The arrangement is useful in a TLB in an MMU.

Abstract: A storage device realizing an improvement in rewrite endurance of a nonvolatile memory and an improvement in data transfer rate of write and read operations is provided including a nonvolatile memory; a volatile memory for storing file management information of the nonvolatile memory; a controller for controlling the nonvolatile memory and the volatile memory; and a power supply maintaining unit for supplying power to the nonvolatile memory, the volatile memory, or the controller upon power shutdown. The controller reads the file management information in the nonvolatile memory upon power-on and writes the same in the volatile memory, and read and write operations are performed based on the file management information in the volatile memory, and the file management information in the volatile memory is written in the nonvolatile memory upon power shutdown.

Abstract: A system and method provides a single system image for a clustered storage network including techniques for processing data access commands between storage appliances over the cluster interconnect. The system is configured such that the cluster is assigned a single world wide nodename. Requests coming to the cluster from client initiators are directed to one or the storage appliances in the cluster, i.e. the “receiving” storage appliance. Commands received by the receiving storage appliance are examined to determine LUN value(s) in the request. If the LUN value is associated with a local storage device, the request is processed by the receiving storage appliance. If the LUN value is not associated with the receiving storage appliance, the request is conveyed over the cluster interconnect to the partner storage appliance to be processed and the appropriate data written or retrieved.

Abstract: An auto-commit memory is capable of implementing a pre-configured, triggered commit action in response to a failure condition, such as a loss of power, invalid shutdown, fault, or the like. A computing device may access the auto-commit memory using memory access semantics (using a memory mapping mechanism or the like), bypassing system calls typically required in virtual memory operations. Since the auto-commit memory is pre-configured to commit data stored thereon in the event of a failure, users of the auto-commit memory may view these memory semantic operations as being instantly committed. Since operations to commit the data are taken out of the write-commit path, the performance of applications that are write-commit bound may be significantly improved.

Abstract: A method for managing a memory stack provides mapping a part of the memory stack to a span of fast memory and a part of the memory stack to a span of slow memory, wherein the fast memory provides access speed substantially higher than the access speed provided by the slow memory.

Abstract: The present disclosure includes methods for transaction log recovery in memory. One such method includes examining a number of entries saved in a transaction log to determine a write pattern, reading the memory based on the write pattern, updating the transaction log with information associated with data read from the memory based on the write pattern, and updating a logical address (LA) table using the transaction log.

Abstract: An apparatus, system, and method are disclosed for efficiently mapping virtual and physical addresses. A forward mapping module uses a forward map to identify physical addresses of data of a data segment from a virtual address. The data segment is identified in a storage request. The virtual addresses include discrete addresses within a virtual address space where the virtual addresses sparsely populate the virtual address space. A reverse mapping module uses a reverse map to determine a virtual address of a data segment from a physical address. The reverse map maps the data storage device into erase regions such that a portion of the reverse map spans an erase region of the data storage device erased together during a storage space recovery operation. A storage space recovery module uses the reverse map to identify valid data in an erase region prior to an operation to recover the erase region.

Abstract: A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.

Abstract: The invention provides a method for handling data updating of a flash memory. In one embodiment, the flash memory comprises a mother block comprising a plurality of updated pages to be updated. First, a spare block, recording no data, is popped as a file allocation table (FAT) block corresponding to the mother block. Data for updating the updated pages of the mother block is then written to a plurality of replacing pages of the FAT block. Finally, a plurality of mapping relationships between the replacing pages and the updated pages are recorded in a page mapping table stored in the FAT block.

Abstract: This invention is a system and a method for operating a storage server to provide read or write access to a data in a data network using a new architecture. The method of creating virtual block mapping pointer in response to a request by a client of the storage server to de-duplicate the file system data block or to allow compression of one or more file system data blocks into one or more physical data blocks. Further, the method relocates one or more file system data blocks from one part of the file system address space to another by using one or more virtual block mapping pointers that provides the mapping information for the one or more file system data blocks that are being relocated. The virtual block mapping pointer allows relocating of file system data blocks by same number of metadata operations regardless of number of files sharing the block that are being relocated and the state of those blocks (compressed or not).

Abstract: A calculator includes a main TLB that stores therein a plurality of address translation pairs indicating a correspondence of a virtual address and an absolute address as a page table and a micro TLB that stores therein part of the page table stored in the main TLB. In the micro TLB, a TLB virtual address [63:13] and a TLB absolute address [46:13] are registered in a correlated manner. With such configuration, when registering an address translation pair in the micro TLB, the calculator chops the address translation pair to a page size of a first size or a fourth size to register it in the micro TLB. Upon receiving an address translation request, the calculator searches for an address corresponding to the page size of the first size or the fourth size registered in the micro TLB, so that address comparison conditions can be reduced, enabling to improve a processing performance.

Abstract: Machine-readable media, methods, apparatus and system for managing sectors of a non-volatile memory are described. In some embodiments, a plurality of file segments may be written to a plurality of memory sectors (501), each memory sector of the plurality of memory sectors for each file segment of the plurality of file segments. Then, a plurality of flags may be searched from a first section of a sector table (502), each flag of the plurality of flags corresponding to the each file segment. A section may be selected from a second section and a third section of the sector table, wherein the section may be indicated by the plurality of flags (505,507). A plurality of physical addresses for the plurality of memory sectors may be written to the section (506,508).

Abstract: Adaptive write leveling in limited lifetime memory devices including performing a method for monitoring a write data stream that includes write line addresses. A property of the write data stream is detected and a write leveling process is adapted in response to the detected property. The write leveling process is applied to the write data stream to generate physical addresses from the write line addresses.

Abstract: A multi-processor computer system is described in which transaction processing in each cluster of processors is distributed among multiple protocol engines. Each cluster includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller in each cluster comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.

Abstract: Transparency of resources is provided and ordering in an access is guaranteed between nodes on a computer network. In an information processing system in which a plurality of processor units are connected to each other by a switch, a global address space is introduced into which effective addresses of the processor units are mapped and which is shared by the plurality of processor units. In response to an access request packet issued by a processor unit and designating an effective address of a target node, a bridge for routing an input and output bus of a processor unit to an input and output bus of the switch converts the effective address of the target node into a global address by appending to the packet a node identification number identifying the target node, and outputs the access request packet designating the global address to the switch. After an access request packet for a write operation is output, the bridge confirms whether the write operation is completed in a target node.

Abstract: A method for setting a memory address space is provided. A memory access frequency of an application program is obtained under execution of an operating system (OS). And a mapping of a memory region is decided according to the memory access frequency. Next, an interrupt signal is used for executing an interrupt handler routine. The mapping of the memory region is set under execution the interrupt handler routine. And the application program is loaded into the memory region for executing in the OS.

Abstract: A computing system is provided. A flash memory device includes at least one mapping block, at least one modification block and at least one cache block. A processor is configured to perform: receiving a write command with a write logical address and predetermined data, loading content of a cache page from the cache block corresponding to the modification block according to the write logical address to a random access memory device in response to that a page of the mapping block corresponding to the write logical address has been used, the processor, reading orderly the content of the cache page stored in the random access memory device to obtain location information of an empty page of the modification block, and writing the predetermined data to the empty page according to the location information. Each cache page includes data fields to store location information corresponding to the data has been written in the pages of the modification block in order.

Abstract: During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages.

Abstract: A memory system for transmitting data to and receiving data from a host apparatus includes a semiconductor memory and an access-controlling part. The semiconductor memory has storage areas identified by physical addresses, stores data in each of the storage areas, performs data write in accordance with a request made by the host apparatus. The access-controlling part selects a recommended address, which is recommended to be used in a next data write, on the basis of operation information about a factor that influences time consumed for data write in the semiconductor memory, and outputs the recommended address to the host apparatus.

Abstract: A data accessing method for accessing data in a plurality of physical page addresses of a plurality of physical blocks in a flash memory chip is provided. The data accessing method includes proving a plurality of logical page addresses for a host system, creating a logical page to physical page mapping table and a physical page to logical page mapping table to record the mapping between the logical page addresses and the physical page addresses. The data accessing method also includes writing data into the physical page addresses, and updating the logical page to physical page mapping table and the physical page to logical page mapping table. The data accessing method further includes determining whether the physical page addresses are valid or invalid based on the logical page to physical page mapping table and the physical page to logical page mapping table.

Abstract: Storage expansion for a virtual machine operating system is reduced. In one embodiment, virtual machines are run on a host and accessed by remote clients over a network. When a guest operating system on one of the virtual machines deletes a file, a VM storage manager on the host detects a special write performed by the guest operating system that writes zeros into a logical block of the file. The VM storage manager links the logical block to a designated block, and de-allocates the disk block that is mapped to the logical block. The de-allocation allows the disk block to be reused by the virtual machines.

Abstract: The present invention provides a mechanism for storing and accessing attributes of a data container (e.g., characteristics such as a name of a data container used to perform a lookup operation against the data container) in cache memory within storage systems in a cluster of storage systems. Further, a mechanism is provided so that an attribute of a data container is inserted into a cache memory of preferably one storage system (in the cluster) that caches metadata of the data container (e.g., information describing the data container). As a result, a lookup operation for a data container is directed to and served by the storage system that caches the metadata and the attribute of the data container. The lookup request is not relayed to a storage system that maintains a central directory of attributes of all data containers in the cluster.

Abstract: An adapter card for testing the functionality of a particular interface configuration may include an interface core. The interface core may comprise an electric circuit including electronic components and control logic for interfacing with an information handling system device. The adapter card may include a front end data channel coupled with the interface core for transmitting data between the electronic components and the information handling system device. The adapter card may include firmware for setting an indicator and causing the control logic to report a memory requirement to the information handling system device larger than a programmed memory space expected by the control logic.

Abstract: When receiving a file access from the client, the file access program refers to the mapping table, and processes an access to files of on volumes of RAID groups. The file server analyzes the file access states, and groups the files depending on the access time period, defines the file migration pattern based on the grouping, migrates the files, and then carries out a power management operation like a spin-down/-up operation on the RAID groups based on the migration pattern.

Abstract: Since both a physical storage place and a logical storage place in a storage system are separately managed as a directory structure, or a hierarchical structure, even in such a case that the physical storage place has been changed, the logical storage place which is displayed to the user is not changed, and thus, the user can use the file while the user need not become aware of the change of the file. When the contents of a file is displayed, a physical storage destination of the file is acquired based upon both a reference path and a relative path of the file, and then, the file is acquired from the physical storage destination.