Abstract: In one illustrative embodiment, an apparatus for controlling a translation lookaside buffer is provided. The apparatus comprises a translation unit, a buffer, and a comparator. The translation unit is adapted to initiate a table walk process to convert a virtual memory address to a physical address. The buffer is adapted to store pending memory access requests previously processed by the translation unit. The comparator is adapted to determine if a physical address generated by the table walk process of the translation unit conflicts with a physical address of at least one of the pending memory access requests, and deliver a control signal to the translation unit for canceling the table walk process in response to determining that a conflict exists.

Abstract: N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30; upon startup of the host computers 10, 20, 30, when the storage controller 40 receives a frame issued, then the microprocessor 42 operates to perform comparison for determining whether the N_Port_Name information stored in the frame has been already set in the microprocessor 42 and registered to the N_Port_Name list within a control table maintained. When such comparison results in match, then continue execution of processing based on the frame instruction; if comparison results in failure of match, then reject any request.

Abstract: A device is presented including a processor. A local memory is connected to the processor. The processor includes a hot way cache accessing process. A method is presented that includes accessing a memory. The method includes processing a first plurality of memory cells and a second plurality of memory cells in the memory. The method determines if a memory block is a last recently accessed memory block. The method determines whether a memory block accessed is a hit or a miss. The method accesses a lower memory level if the memory block accessed is a miss. Also, processing the second plurality of memory cells for an exact block if the block accessed is a hit but not the last recently accessed memory block. And, providing the memory block for additional access if the memory block accessed is a hit and is a last recently accessed memory block.

Abstract: The present invention has for its object to provide a data processing apparatus which improves the point that in data processing employing an associative storage device, performing the high speed processing has been impossible in the full-associative constitution since each way (entry) is subjected to the sequential processing respectively in search processing. The data processing apparatus includes a TLB comprising an information pair specifying information means (RP), a first information holding means (PTE-Hi), and a second information holding means (PTE-Lo). The high speed processing against information held in a TLB memory section is realized by performing the search processing employing information held in the above-mentioned means.

Abstract: An embodiment of a memory controller that improves main memory bandwidth utilization during graphics translational lookaside buffer fetch cycles is disclosed. The memory controller includes a first request path and a second request path. The memory controller further includes a graphics translational lookaside buffer that includes a cache. The graphics translational lookaside buffer issues an address fetch request to a memory interface when a graphics memory request received from the first request path or from the second request path misses the cache. The memory controller also includes a memory arbiter that includes a first request path cycle tracker and a second request path cycle tracker. The memory arbiter allows a request received from the second request path to be issued to the memory interface when a graphics memory request received from the first request path is stalled due to a graphics translational lookaside buffer cache miss.

Abstract: A method for maintaining an instruction in a pipelined processor using inuse fields. The method involves receiving a read request for an instruction, sending the instruction in response to the read request and setting an inuse field associated with the instruction to inuse. Alternate embodiments of the method involve transmitting the instruction in response to the read request, receiving a notification of instruction retirement and resetting the inuse field in the ITLB. The method can also be used in the ICACHE in which inuse fields are associated with each instruction stored in the ICACHE. Other embodiments of the method can be used concurrently in the ITLB and the ICACHE as a resource tracking mechanism to maintain resources.

Abstract: An apparatus and method are provided for determining initial information about a macro instruction prior to decoding of the macro instruction by translation logic within a pipeline microprocessor. The apparatus includes an instruction cache divided into a number of cache ways, each of the cache ways storing a number of cache lines that have been retrieved from memory. As a linear address within a next instruction pointer is provided to retrieve a the macro instruction from the cache, indexed cache lines from each of the cache ways are predecoded by predecode logic. Predecoding is performed in parallel with translation of the linear address to a physical address by translation lookaside buffer logic. The bytes of the indexed cache lines, along with corresponding predecode information fields, are provided to way selection logic.

Abstract: A method for accessing a cache memory within a data processing system is disclosed. The cache memory includes a memory array and a directory along with a translation lookaside buffer. The cache memory may be accessed by an effective address that includes a byte field, a line field, and an effective page number field. In order to facilitate the cache access process, a translation array is provided that has the same number of rows as the translation lookaside buffer. Each row of the translation array has the same number of array entries as the product of the number of lines per page of a system memory and the set associativity of the cache. The translation array is updated after the contents of the directory or the translation lookaside buffer have been updated. The translation array can be accessed with the contents of a line field of an effective address to determine whether or not the cache memory stores data associated with translated address.

Abstract: A memory-access management method and system is provided for use with an DRAM (Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations. The memory-page management system has a managing device for managing the N memory pages. According to the embodiment, the managing device further comprises a page register unit. The page register unit is used for storing K storage units, each of which stores an address data of the memory page. The utilization-rate register unit is coupled to the page register circuit, and used for monitoring utilizations of the storage units. In practical design, the number K of the storage units can be designed to be less than the number N of the memory pages.

Abstract: The present invention generally relates to a memory device. More particularly, the present invention relates to a memory system for receiving chip selecting signals and a plurality of control signals from a memory controller. The memory system comprises: a chip selecting determiner for deciding whether the chip selecting signals are enabled; a main operation command table for defining a predetermined operation corresponding to combination of the control signals when the chip selecting signals are enabled; a preliminary operation command table for defining a predetermined operation corresponding to combination of the control signals when the chip selecting signals are disabled; and a logic circuit unit for decoding the combination of the control signals into a predetermined operation, based on the main operation command table or the preliminary operation command table according to enable conditions of the chip selecting signals from the chip selecting determiner.

Abstract: To support a new processor control bit, the Real Space Control (RSC) bit, in a processor system with an existing translation lookaside buffer, an existing control bit, the Private Space bit, in the translation lookaside buffer is redefined as an Ignore Common segment bit to create new non-overlapping translation lookaside buffer entries.

Abstract: A cache structure for computer architecture evaluates the subblocks actually used in the cache to modify the granularity of subsequent refreshes of the cache. When many subblocks are used, then subsequent fetches will load the entire block. If only a few subblocks are used, subsequent fetches will fetch only a single subblock. Discontinuous subblock fetching is provided for in a second embodiment in which an entire block is fetched if there is no correlation in the pattern of the subblock usage over time whereas a pattern of discontinuous subblocks is fetched if an historical pattern is revealed. A combination of these two embodiments may also be used.

Abstract: Methods of managing a cache memory system in a data processing system are disclosed. The data processing system executes instructions and stores and receives data from a memory having locations in a memory space. The entries of the cache memory are in locations in a register space separate from the memory space. A first instruction that operates only on locations in a register space but not on locations in memory space may be executed to obtain address information from at least one entry of the cache memory. The obtained address information be compared with target address information. If the comparison between the obtained address information and the target address information results in a correspondence, then a first operation may be performed on the entry of the cache memory. If the comparison between the obtained address information and the target address information does not result in a correspondence, then the fit first operations not performed on the entry of the cache memory.

Abstract: A microprocessor is equipped with an address translation mechanism for performing dynamic address translation from a virtual address to a physical address on a page-by-page basis. The microprocessor includes a large-capacity low-associativity address translation buffer, and is capable of avoiding limitations imposed on a TLB entry lock function, while reducing the overhead for address translation. The address translation mechanism comprises an address translation buffer having an entry lock function, and control logic for controlling the operation of the address translation buffer. The address translation buffer includes a lower-level buffer organized as a lower-level hierarchy of the address translation buffer and having no entry lock function, and a higher-level buffer organized as a higher-level hierarchy of the address translation buffer and having an entry lock function, the higher-level buffer having higher associativity than the associativity of the lower-level buffer.

Abstract: A searching system allowing high-speed data searching and operation is disclosed. A search table is provided which stores a copy of an entry that has been retrieved from a database to retrievably store a plurality of retrieved entries. Further, an address pointer table is provided which stores a list of retrieved entries which are linked from a leading one to a bottom one. A search processor can access a plurality of retrieved entries by referring to the list stored in the address pointer table so as to be consistent with a corresponding entry stored in the database when the corresponding entry has been updated.

Abstract: The present invention relates to a technique for accessing memory units in a data processing apparatus. The data processing apparatus comprises of plurality of memory units for storing data values, a processor core for issuing an access request specifying an access to be made to the memory units in relation to a data value, and a memory controller for performing the access specified by the access request. Attribute generation logic is provided for determining from the access request one or more predetermined attributes verifying which of the memory units should be used when performing the access. However, the memory controller does not wait until such determination has been performed by the attribute generation logic before beginning the access.

Abstract: N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30; upon startup of the host computers 10, 20, 30, when the storage controller 40 receives a frame issued, then the microprocessor 42 operates to perform comparison for determining whether the N_Port_Name information stored in the frame has been already set in the microprocessor 42 and registered to the N_Port_Name list within a control table maintained. When such comparison results in match, then continue execution of processing based on the frame instruction; if comparison results in failure of match, then reject any request.

Abstract: A cache memory system (e.g., a translation-lookaside buffer 100) utilizing a reduced overhead entry selection process for overwriting and updating entries. The disclosed embodiment of the present invention uses a match bit, a detection operation (such as a status probe operation), and an efficient control mechanism to identify a particular translation in a translation-lookaside buffer 100 to be updated or overwritten. Based on the results of the probe operation, the match bit is selectively set or cleared. Next, a control mechanism selects one of two possible indices 110 and 114 (locations) in the translation-lookaside buffer 100 to perform a write operation. The first index 110 corresponds to an existing entry, while the second index 114 corresponds to a random entry to be overwritten. The selection process is essentially completed in a single step via dedicated logic. In this manner, overhead associated with selecting an entry to be updated is minimized.

Abstract: When reading or writing data from or to a flash memory, a table indicating the correspondence between physical addresses of physical blocks composing together a storage area of the flash memory and logical addresses of logical blocks written in the physical blocks, is generated in segments of the flash memory.

Abstract: An embodiment of the present invention includes a tag array, a valid vector, and a detector. The tag array stores N tag entries. Each of the N tag entries contains a one-hot tag having K bits. Each of the K bits of the one-hot tag corresponds to a translation look-aside buffer (TLB) entry in a TLB array having K TLB entries. The valid vector stores N valid entries corresponding to the N tag entries. The detector detects an error when a tag entry is read out upon a fetch read operation.

Abstract: The present invention, in various embodiments, provides techniques for managing memory in computer systems. One embodiment uses a memory table having entries to locate data residing in different types of storage areas, such as physical memory, hard disc, file servers, storage devices, etc. Upon a program accessing memory for a particular piece of data, the memory table translates the data's physical address to an address used to find the table entry pointing to the requested data. In one embodiment, if the data is in physical memory, then the requested data is returned to the program. However, if the data is not in physical memory and it is determined that the data will be used frequently, then the data, in addition to being returned, is also brought to the physical memory for later use. This is because accessing the data from physical memory usually takes less time than accessing the data from other storage devices.

Abstract: A method for adding compressed page tables to an operating system is disclosed. An embodiment provides for a method in which a single entity, for example, an operating system has control of the compression and decompression of data and where the data is stored. When a data access is desired, the method accesses a table specifying the physical memory location of uncompressed data to determine if specified data is in uncompressed memory. The method of this embodiment accesses a table specifying the physical memory location of data in compressed memory to determine if the data is in the compressed memory. The method also access a page directory table to determine the location of the data in virtual memory in the event of a page fault. Then, this embodiment accesses the data based on the table look-up results.

Abstract: A cache is coupled to receive an access which includes a cache allocate indication. If the access is a miss in the cache, the cache either allocates a cache block storage location to store the cache block addressed by the access or does not allocate a cache block storage location in response to the cache allocate indication. In one implementation, the cache is coupled to an interconnect with one or more agents. In such an implementation, the cache accesses may be performed in response to transactions on the interconnect, and the transactions include the cache allocate indication. Thus, the source of a cache access specifies whether or not to allocate a cache block storage location in response to a miss by the cache access. The source may use a variety of mechanisms for generating the cache allocate indication.

Abstract: A virtual memory page table wherein each entry specifies the size of an optional larger block of pages which is optionally associated with any particular page. This achieves a backward-compatible way to achieve variable page size with minimal added overhead.

Abstract: The present invention relates to a cache mechanism of a browser apparatus as a World Wide Web (WWW) client and aims at the improvement of utilization efficiency and the shortening of an information acquisition delay time. A cache is constituted in an HDD or DVD-RAM under the control of a Web cache program. A copy of acquired information is stored in the cache. A directory of the cache is managed by a Web cache management table, and the control is made so that the writing of the cache contents and necessary entries of the management table is completed before the DVD-RAM is removed from the browser apparatus. A browsing work can be continued smoothly by loading the DVD-RAM to another browser apparatus. Also, if an information provider provides information in a form stored in a disk in the form of a Web cache, the browsing of the information becomes possible with the same URL as that in WWW access.

Abstract: A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses, for example into physical addresses. The mechanism supports sharing of TLB entries among logical processors, which may access address spaces in common.

Abstract: A semiconductor disk drive using a non-volatile memory of MGM such as flash memory, allowing swift access of nondefective sectors or blocks, and shortening the time for creating a logical/physical conversion table, and a method of creating the logical/physical address conversion table for the semiconductor disk drive. According to the disk drive and the method, the addresses of all defective sectors are stored in predetermined sectors or in a predetermined block during manufacturing process, and a CPU for internal control creates a logical/physical address conversion table in a memory for CPU, based on the sector addresses of all defective sectors.

Abstract: A memory unit is presented employing a least recently used (LRU) replacement strategy. The memory unit may include a memory subunit for storing data items, circuitry coupled to the memory subunit for determining if the memory subunit contains a needed data item, and a control unit for controlling the storing of data items within the memory subunit. The memory subunit may include n entry locations where n≧2. The memory unit may generate a first signal indicating which of the n entry locations are currently in use (i.e., contain valid data items), and the circuitry coupled to the memory subunit may produce a second signal indicating which of the n entry locations contains the needed data item. A new data item to be stored within the memory subunit may be accompanied by a control signal identifying which of the n entry locations is to be used to store the new data item. The control unit may receive the first and second signals and produce the control signal dependent upon the first and second signals.

Abstract: In a system in which data are stored in an interleaved fashion in a memory consisting of a plurality of memory banks, a method and means are provided for mapping a given address into a memory bank and an internal memory bank address. Lookup table means (LUT1; LUT2) are provided for furnishing not only a bank number but also a part (MSP) of the internal bank address, in response to selected portions (X, Y) from the given address, while the remainder (LSP) of the internal bank address is directly taken from the given address. Two implementations are disclosed in which either two lookup tales are provided, or two sections in a single lookup table, for separately generating the bank number and a part of the internal bank address. Another implementation provides two lookup tables which are accessed sequentially and which provide different intermediate outputs (m, n, p, q, r) which are selectively combined (B, C) to obtain bank number as well as part of the internal bank address.

Abstract: The inventive mechanism has a run-time optimization system (RTOS) embedded in hardware. When the code is first moved into Icache, a threshold value is set into a counter associated with the instruction or instruction bundle of the particular cache line of the Icache. Each time the instruction or instruction bundle is executed and retired, the counter is decremented by one. When the counter reaches zero, a trap is generated to inform that the code is hot. A trace selector will form a trace starting from the hot instruction (or instruction bundle) from the Icache line. The Icache maintains branch history information for the instructions in each cache line which is used to determine whether a branch should be predicted as taken or fall through. After the trace is formed, it is optimized and stored into a trace memory portion of the physical memory. The mapping between the original code of the trace and the optimized trace in the trace memory is maintained in a mapping table.

Abstract: An apparatus including an input/output control device and an associated method are disclosed. The method includes a list with read requests recorded therein in the order of generation thereof is provided for each client, and a read request from a client is added to an end of a list for the client, when the request is generated within a specified period of time after generation of the previous read request from the same client. When the request is generated after passage of the specified period of time, it is added to a header of a new list. Common sections of the two lists are recorded in a common table, and information instructing to refer to the common table is inserted into the lists in place of the common sections in the lists. Data is prefetched from the disk device and stored in a cache memory based on the content of the lists. Data corresponding to common sections between the two lists may be relocated or written in a continuous empty area of the disk device in a continuous state.

Abstract: This invention is memory system including plural memory banks logically disposed into an array of X rows and Y columns. A first decoder selectively powers one of the Y columns corresponding to a first predetermined set of address bits. A second decoder selectively powers one of the X rows corresponding to a second predetermined set of address bits. Multiplexers select the powered memory bank for data access. Thus one of the plural memory banks is powered and selected for memory access corresponding to the first and second predetermined sets of bits of the received address. This memory system is preferably a cache memory including a further column of memory banks for cache addresses and cache control data including at least a cache valid tag. A multiplexer selects one row corresponding to the second predetermined set of address bits.

Abstract: A calculating part performs calculation. A storing part stores data from the calculating part. An address converting part converts an address corresponding to data requested by the calculating part. A first comparing part compares an address from the address converting part and data stored in the storing part. A second comparing part compares the address corresponding to the data requested by the calculating part with an address of said storing part. A selecting part selects the data stored in the storing part to be provided to the calculating part when an address comparison result of the first comparing part is coincidence and also an address comparison result of the second comparing part is coincidence.

Abstract: A data structure and method implemented in accordance with the invention enable reading a cache to get a type information corresponding to an address of interest more reliably than with volatile read operations and faster than scanning tables or walking along linked lists. Reliably reading the cache enabled by the invention does not require locks, although, the type information and the address together require more bits than those present in one machine word.

Abstract: A method of operating a multi-level memory hierarchy of a computer system and apparatus embodying the method, wherein instructions issue having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit.

Abstract: The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Page Table (VHPT), an extension of the Translation Lookaside Buffer (TLB) hierarchy, is designed to enhance virtual address translation performance. Virtual Hash Page Table (VHPT) efficiently supports two different methods of operating systems use to translate virtual addresses to physical addresses. This directly benefits the highly frequented path of address resolution.

Abstract: The inventive mechanism provides fast profiling and effective trace selection. The inventive mechanism partitions the work between hardware and software. The hardware automatically detects which code is executed very frequently, e.g. which code is hot code. The hardware also maintains the branch history information. When the hardware determines that a section or block of code is hot code, the hardware sends a signal to the software. The software then forms the trace from the hot code, and uses the branch history information in making branch predictions.

Abstract: A fully-associative translation lookaside buffer structure for a computer system includes a first-level TLB0 memory having a plurality of entries and a second-level TLB1 memory operatively coupled to the first level TLB0 memory. The second-level TLB1 memory also has a plurality of entries. Entries are placed in the TLB0 and TLB1 structure as a result of software controlled translation register operations and hardware controlled translation cache operations. Logic controlling TLB0 treats both operations the same way and uses a hardware replacement algorithm to determine the entry index. Logic controlling TLB1 uses a hardware replacement algorithm to determine the entry index for translation cache entries, and use an index provided within the insertion instruction to determine the entry index for translation register operations.

Abstract: A method of maintaining translation context for instructions translated from instructions designed for a target microprocessor to run on a host microprocessor including storing translation context related to each translated host instruction, indicating a translation context for host instructions presently being executed by the host processor, comparing translation context stored for a next host instruction with the translation context for a host instruction presently being executed, executing the next host instruction if the translation context of the next host instruction and the presently executing host instruction compare, and searching for an instruction with translation context which compares to the translation context of the host instruction presently executing if the translation context of the next host instruction and the presently executing host instruction do not compare.

Abstract: Disclosed is a server farm or MetaServer environment in which thin servers or server appliances each include a programmable network interface card providing logic required for implementing service processor functions. The combined implementation of the network interface and service processor hardware and software substantially eliminates redundancies, which previously existed when both were separate components. Service processor functions that are provided on the programmable network interface card includes gathering sensor data about the hardware, forwarding alerts regarding hardware state, initiating shutdown and restart on command, and responding to operating system service processor inquiries and commands. Additionally, other low-level management and control functions are provided on the programmable network interface card. Also, in one embodiment, a re-partitioning of the functions between the service processor (or probes) and the network interface is provided.

Abstract: A computer system comprises a nonuniform access memory distributed in several places of residence. The memory accesses a physical resource of the memory at a physical address constituted by a field of i bits and a field of j bits. The memory comprises a table with a number of rows equal to a power (i−j) of two, each row being accessible by a field of (i−k) bits of the physical address containing an identifier of the place of residence of the resource. The process for identifying a place of residence of a physical memory resource thereof consists of simply reading the identifier in the row of the table referenced by the field of (i−k) bits.

Abstract: The present invention discloses a method and apparatus that uses extensions to the TLB entry to dynamically identify pages of memory that can be weakly ordered or must be strongly ordered and enforces the appropriate memory model on those pages of memory. Such identification and memory model enforcement allows for more efficient execution of memory instructions in a hierarchical memory design in cases where memory instructions can be executed out of order. From the page table, the memory manager constructs TLB entries that associate page frame numbers of memory operands with page-granular client usage data and a memory order tag. The memory order tag identifies the memory model that is currently being enforced for the associated page of memory. The memory manager updates the memory order tag of the TLB entry in accordance with changes in the client usage information. In the preferred embodiment, the TLB structure is a global TLB shared by all processors.

Abstract: An improved method and apparatus for utilizing Translation Lookaside Buffers (TLB) for maintaining page tables in a paging unit on a computer system. TLB contents for executing tasks are retained when the task is swapped out. The contents are then reloaded into the TLB when the task is again scheduled for execution. Spare memory cycles are utilized to transfer outgoing TLB data into memory, and incoming TLB data for a next scheduled task from memory.

Abstract: A set-associative cache memory having a built-in set prediction array is disclosed. The cache memory can be accessed via an effective address having a tag field, a line index field, and a byte field. The cache memory includes a directory, a memory array, a translation lookaside buffer, and a set prediction array. The memory array is associated with the directory such that each tag entry within the directory corresponds to a cache line within the memory array. In response to a cache access by an effective address, the translation lookaside buffer determines whether or not the data associated with the effective address is stored within the memory array. The set prediction array is built-in within the memory array such that an access to a line entry within the set prediction array can be performed in a same access cycle as an access to a cache line within the memory array.

Abstract: A magnetic disc control apparatus detects a near sequential I/O and pre-reads data from a magnetic disc drive into a cache memory. The control apparatus includes a near sequential I/O processor, which has an I/O history storage table for storing a transfer end address of I/O requested by a host computer, a near sequential I/O identifier for calculating an address difference between the transfer end address read out from this I/O history storage table and the current I/O transfer start address and identifying the I/O as a near sequential I/O if the address difference is within a predetermined value, and a pre-read executor for pre-reading data from the magnetic disc drive to the cache memory when a near sequential I/O is detected.

Abstract: System and method for reducing data access latency for cache miss operations in a computer system implementing main memory compression in which the unit of compression is a memory segment. The method includes steps of providing common memory area in main memory for storing compressed and uncompressed data segments; accessing directory structure formed in the main memory having entries for locating both uncompressed data segments and compressed data segments for cache miss operations, each directory entry including index for locating data segments in the main memory and further indicating status of the data segment; and, checking a status indication of a data segment to be accessed for a cache miss operation, and processing either a compressed or uncompressed data segment from the common memory area according to the status.

Abstract: A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or by concatenating the values from two registers. Hierarchical translation of a linear address to a physical address is performed in which the number of levels in the hierarchy depends upon whether the linear address is an extended linear address.

Abstract: A portion of the global memory of a multiprocessing computer system is allocated to each node, called local memory space. Data from a remote node may be copied to local memory space of a node such that accesses to the data may be performed locally rather than globally. The global address of the data is translated to a local physical address for the node to which the data is copied. To reduce the size of the translation tables for converting between global addresses and local physical addresses, multiple pages of the address space are mapped to an entry in a translation table. To decrease the probability that an entry is not available for a page, the translation table may be implemented as a skewed-associative cache that implements an insertion algorithm that realigns the translations in the table to maximize the utilization of the available entries is implemented.

Abstract: As a program is replaced by the operating system running within a microprocessor, only those entries associated with the replaced program and resident within effective-to-real address translation units will be replaced. Those entries within the effective-to-real address translation units associated with the operating system and shared libraries, and any other software units operating within the microprocessor will not be invalidated.

Abstract: A method and apparatus includes processing for modifying memory accesses, which begins by receiving a memory transaction. The processing continues by determining whether a translation look-aside table (TLB) entry exists for the memory access transaction. If a TLB entry does not exist, one is generated. Once a TLB entry exists for the memory access transaction, a transaction tag within the TLB is interpreted to identify an exception or a memory address space from a plurality of memory address spaces. The processing continues by interpreting the TLB entry to obtain a physical address when the tag identifies the memory address space. Having obtained the physical address, the memory address transaction is processed utilizing the physical address within the corresponding memory address space.