Abstract: A method and apparatus for manipulating data in a storage device that is coupled to a host computer. Manipulations that can be performed by the storage device include moving non-contiguous blocks of data between the host computer and the storage device in a single operation. Other manipulations can be performed directly by the storage device without passing data to or from the host computer and include copying data from one logical object that is defined on the host computer to another, initializing, backing-up, transforming, or securely deleting a logical object that is defined by the host computer with a single command. In one embodiment, an application programming interface is provided that allows a relationship between logical objects on a host computer and storage locations on a storage device to be communicated between the host computer and the storage device.

Abstract: An assigning system and an assigning method are provided for assigning a storage device or a unitary logical unit of the storage device. A VLU-LU correspondence table is provided which shows a correspondence between virtual logical units (VLU) virtually set in a host computer and logical units (LU) of a plurality of storage devices connected to a network. This table stores evaluation items of each storage device such as a delay time and an access frequency. An evaluation unit calculates an evaluation value of each evaluation item in the table, and a unitary logical unit of the storage is assigned in accordance with the evaluation value.

Abstract: A fast translation look-aside buffer for translating a linear address RL=A+B to a physical address, where A and B are two N bit operands. Inputs to the translation look-aside buffer are the n highest-order bits of A and B, where n<N, and the carry-out term from the sum of the first N−n bits of A and B. The TLB may provide a hit without the need for the sum of A and B.

Abstract: A storage unit comprises a plurality of storage modules, each of which is dynamically assigned to and used as each area in a main storage (MS) or an extended storage (ES). The storage unit or a system controller has address arrays for MS and for ES which store information indicating which of the storage modules comprised in the storage unit each area in the MS and the ES corresponds to. When the contents of the MS/ES address arrays are rewritten to change a storage module belonging to the ES to a storage module belonging to the MS, a page-in operation is realized without executing an actual data move operation. Similarly, a page-out operation is realized without executing an actual data move operation by changing a storage module belonging to the MS to a storage module belonging to the ES.

Abstract: Physical page information PA(a) corresponding to logical page information VA(a) as a cache tag address is retained in a logical cache memory 10 and in the event of a cache miss when a shared area is accessed, the physical page information PA (a) retained in the cache memory is compared with physical page information PA (b) resulting from the translation of a search address by TLB. When the result of the comparison is proved to be conformity, the cache entry is processes as a cache hit, so that the problem of a synonym arising from a case where the same physical address is assigned to different logical addresses is solved in such a manner that the number of times access is provided to TLB is halved as compared with the conventional arrangement.

Abstract: Source data is more efficiently copied to log structured target storage by pre-configuring the target storage. The invention may be practiced in a system including a host, a storage controller, and the target storage. The host maintains a directory identifying logical units of stored data, and the storage controller maintains records classifying storage space as uncollected free space, collected free space, or space-in-use. First, the host receives input including source data and specification of a logical unit for the source data. In response, the host directs the storage controller to classify any storage space of the log target storage containing data of the specified logical unit as uncollected free space. This pre-configures the log structured storage to more efficiently receive the source data.

Abstract: A portion of the global memory of a multiprocessing computer system is allocated to each node, called local memory space. Data from a remote node may be copies to local memory space of a node such that accesses to the data may be performed locally rather than globally. The copies data is referred to as a shadow page. The global address of the data is translated to a local physical address for the node to which the data is copied. To reduce the size of the translation tables for converting between global addresses and local physical addresses, the page to which shadow copies may be stored and which global addresses may be converted to local physical addresses may be restricted. Multiple page of local memory space may be allocated to one entry of a local physical address to global address (LPA2GA) table. When a page is allocated to store shadow pages, an entry in the LPA2GA table associated with that page is marked as unavailable.

Abstract: An address look-up mechanism in a multi-port bridge for controlling use of a memory as a look-up table for appropriately filtering and directing packets. The look-up table includes learned look-up tables, permanent look-up tables and linked lists. As a data packet originating from a node (source node) is received by a corresponding one of the ports (source port) of the multi-port bridge, a look-up cycle and then a learning cycle are each performed. During the learning cycle, an identification of the source port for the packet is stored in the learned look-up tables in association with a hashed node address of the source node. Each existing entry is examined to ensure that the appropriate port identification is stored and to determine whether two or more nodes share a same hashed node address. If two nodes have the same hashed node address, then a linked entry in the linked lists is formed.

Abstract: A page table entry management method and apparatus provide the Microkernel System with the capability to program the memory management unit on the PowerPC family of processors. The PowerPC processors define a limited set of page table entries (PTEs) to maintain virtual to physical mappings. The page table entry management method and apparatus solves the problem of a limited number of PTEs by segment aliasing when two or more user processes share a segment of memory. The segments are aliased rather than duplicating the PTES. This significantly reduces the number of PTEs. In addition, the method provides for caching existing PTEs when the system actually runs out of PTEs. A cache of recently discarded PTEs provides a fast fault resolution when a recently used page is accessed again.

Abstract: A portion of the global memory of a multiprocessing computer system is allocated to each node, called local memory space. Data from a remote node may be copies to local memory space of a node such that accesses to the data may be performed locally rather than globally. The copies data is referred to as a shadow page. The global address of the data is translated to a local physical address for the node to which the data is copied. To reduce the size of the translation tables for converting between global addresses and local physical addresses, the page to which shadow copies may be stored and which global addresses may be converted to local physical addresses may be restricted. Multiple page of local memory space may be allocated to one entry of a local physical address to global address (LPA2GA) table. When a page is allocated to store shadow pages, an entry in the LPA2GA table associated with that page is marked as unavailable.

Abstract: A data processing system and method are described for generating virtual memory descriptors which include pretranslated physical addresses. The data processing system has a virtual memory address space and a main memory. The main memory includes a first plurality of physical addresses. A temporary association is established between a region of the main memory and a segment of the virtual memory address space. The region of main memory is addressed utilizing a second plurality of physical addresses. The segment of virtual memory is addressed utilizing a plurality of virtual addresses. In response to the establishment of the temporary association, a virtual memory descriptor is generated and is utilized to address the segment. Each of the plurality of virtual addresses is translated to one of the second plurality of physical addresses. Each translated one of the second plurality of physical addresses is stored in the memory descriptor.

Abstract: A method of generating a lookup table includes receiving an input address; generating a compressed address from the input address, the compressed address having fewer bits than the input address; selecting a first set of bits from the compressed address; determining whether a memory location pointed to by the first set of bits in an address lookup table includes an unoccupied memory slot; determining whether the input address matches any address stored in the memory location pointed to by the first set of bits in the address lookup table; and selecting a second set of bits from the compressed address in response to there not being an unoccupied memory slot in the memory location pointed to by the first set of bits and the input address not matching any address stored in the memory location pointed to by the first set of bits. A lookup table generator includes an address compressor, a barrel shifter, and an address lookup table that includes a memory location that is pointed to by the first set of bits.

Abstract: In a high-speed address translation system provided in a computer system including a logical address space storing logical addresses, a physical address space for storing physical addresses and a microprocessor unit connected to both address spaces, and the microprocessor unit including a memory management unit (MMU), the system according to the present invention includes; a TLB provided in the MMU for translating the logical address to the physical address; and a unit for adjusting a size of each section formed of a file to a predetermined page size in an offline process in accordance with memory allocation designed in the offline process.

Abstract: A novel on-chip cache memory and method of operation are provided which increase microprocessor performance. The on-chip cache memory has two levels. The first level is optimized for low latency and the second level is optimized for capacity. Both levels of cache are pipelined and can support simultaneous dual port accesses. A queuing structure is provided between the first and second level of cache which is used to decouple the faster first level cache from the slower second level cache. The queuing structure is also dual ported. Both levels of cache support non-blocking behavior. When there is a cache miss at one level of cache, both caches can continue to process other cache hits and misses. The first level cache is optimized for integer data. The second level cache can store any data type including floating point. The novel two-level cache system of the present invention provides high performance which emphasizes throughput.

Abstract: A microprocessor employs a branch prediction unit including a branch prediction storage which stores the index portion of branch target addresses and an instruction cache which is virtually indexed and physically tagged. The branch target index (if predicted-taken, or the sequential index if predicted not-taken) is provided as the index to the instruction cache. The selected physical tag is provided to a reverse translation lookaside buffer (TLB) which translates the physical tag to a virtual page number. Concatenating the virtual page number to the virtual index from the instruction cache (and the offset portion, generated from the branch prediction) results in the branch target address being generated. In one embodiment, the process of reading an index from the branch prediction storage, accessing the instruction cache, selecting the physical tag, and reverse translating the physical tag to achieve a virtual page number may require more than a clock cycle to complete.

Abstract: A method and apparatus link translation lookaside buffer (TLB) purge operations to cache coherency transactions, thereby allowing the TLB purge operations to be performed by hardware without significant software intervention. Computer systems having cache memories associated with multiple cache modules, such as a CPU or an I/O device, typically use a cache coherency protocol to ensure that the cache memories remain consistent with each other and with main memory. Popular cache coherency protocols usually include an INVALIDATE transaction that signals cache memories to invalidate a cache line associated with the address contained in the transaction. A TLB in accordance with the present invention will observe the physical address contained in an INVALIDATE request and determine whether address lies within the page table. If it does, the physical address into the page table will be converted into a virtual page number. The TLB will then be accessed to see if the TLB contains an entry for the virtual page number.

Abstract: The memory device includes an auxiliary memory and a useful memory. Both memories are provided with a plurality of memory entries. The auxiliary memory is intended for storing regions of an address space therein. This includes a plurality of addresses with which the useful memory may be addressed. A write/read access to a useful memory entry is not possible if a status field associated with the useful memory entry signals a restricting status and the address with which the useful memory entry is addressed lies within at least one of the address space regions stored in the auxiliary memory. Efficient region-selective flushing of the useful memory is possible with this procedure.

Abstract: A microprocessor capable of predecoding variable-length instructions and storing them in a three-dimensional instruction cache is disclosed. The microprocessor may comprise a predecode unit, an instruction cache, and an address translation table. The predecode unit receives variable-length instructions from a main memory subsystem. These instructions are then predecoded by detecting instruction field boundaries within each variable-length instruction. Instructions fields that are not present in a particular instruction may be added by inserting padding constants so that the instruction matches a predetermined format having all instruction fields. The predecoded instruction is stored in the instruction cache, which may be logically and physically structured as a three-dimensional array. Each instruction is stored in the cache so that it has a fixed length in two dimensions. The address translation table maintains address translations for each instruction stored in the instruction cache.

Abstract: A method is provided for guiding virtual-to-physical mapping policies in a computer system including a processor and a memory. State information is randomly sampled from selected memory references in a stream of memory references issued by the processor to the memory. Cache hit/miss status, translation-look-aside buffer hit/miss status, and effective virtual and physical memory addresses of the sampled memory references are recorded in a profile record. The recorded information is aggregated by virtual memory address, and a new virtual-to-physical mapping is choosen to reduce cache and translation-look-aside buffer miss rates.

Abstract: A method of reproducing digital signals recorded on a disk having first and second recording surfaces. The digital signals are in the form of a data frame including a lead-in block and n data blocks. The lead-in block has a same format as the n data blocks. n block addresses are assigned to the n data blocks. Information identifying an area on the disk in which the n data blocks is recorded is assigned to the n data blocks. m data blocks (0<m<n) are recorded on the first recording surface, and remaining (n−m) data blocks are recorded on the second recording surface. The lead-in block is recorded at the head of the data frame, and includes recording area identifying information identifying an area on the disk in which the lead-in block is recorded, and disk information identifying (1) a number of recording surfaces, (2) the block address of one of the m data blocks recorded last on the first recording surface, and (3) the block address of a last one of the n data blocks in the data frame.

Abstract: A disk storage system with a RAID architecture includes a write buffer having a storage capacity corresponding to one stripe, a buffer management table, and a controller. The controller stores, in the write buffer, logical blocks whose data lengths are changed, as needed, and delays updating of the logical blocks stored in the write buffer in data update processing until the number of stored logical blocks reaches N*K−1 The controller then performs a continuous write operation to sequentially write N*K logical blocks, obtained by adding a logical address tag block to the N*K−1logical blocks, in contiguous areas of empty areas different from the areas in which the old data are stored.

Abstract: A cache memory within a data processing system. The cache memory includes a number of cache lines over which data may be transferred. The cache memory also includes a translation lookaside buffer for associating real addresses with virtual addresses. Virtual segment identifiers are stored within the translation lookaside buffer. In addition, the cache memory includes a comparison array for cross referencing virtual segment identifiers with effective addresses. The comparison array includes spaces populated with indications of whether or not a particular virtual segment identifier maintained within the translation lookaside buffer corresponds to a particular effective address. The comparison array allows a comparison to be performed in advance between effective addresses within the cache memory and all possible virtual segment identifiers maintained in the translation lookaside buffer prior to any conversion of virtual addresses to real addresses.

Abstract: An apparatus and method for accessing a memory. A source address that includes a page address and a page offset is received. The page address requires translation in order to form a first address that can be used to transfer data from a row of memory cells into a sense amplifier array in a memory. The page address is compared to contents of one or more page registers to determine if the data is present in the sense amplifier array as a result of a previous memory access. A second address is asserted to access a portion of the data if the data is determined to be present in the sense amplifier array.

Abstract: A central processor uses virtual addresses to access data via cache logic including a DAT and ART, and the cache logic accesses data in the hierarchical storage subsystem using absolute addresses to access data, a part of the first level of the cache memory includes a translator for virtual or real addresses to absolute addresses. When requests are sent for a data fetch and the requested data are not resident in the first level of cache the request for data is delayed and may be forwarded to a lower level of said hierarchical memory, and a delayed request may result in cancellation of any process during a delayed request that has the ability to send back an exception. A delayed request may be rescinded if the central processor has reached an interruptible stage in its pipeline logic at which point, a false exception is forced clearing all I the wait states while the central processor ignores the false exception.

Abstract: The present invention generally relates to a system and method for a message protocol to extend cache coherence management of scalable shared memory multiprocessing computer systems having a plurality of processors connected to an interconnection over which the plurality of processors communicate with each other. Each processor communicates with other interconnection processors by sending and receiving messages on the interconnection by means of a messaging protocol which can be used for shared-memory computer systems, shared nothing computer systems, and hybrid computer systems in which some processors are sharing memory while others are not. With this invention a processor node is able to tell whether an incoming message is from within the same coherence group (in which case it is completely unprotected) or whether it is from outside the coherence group (in which case the shared-nothing protections apply).

Abstract: In a storage device in which data is read ahead and stored in a cache memory during reading of data from a medium, a data buffer is managed so that the probability that data to be read is found in the cache memory will improve. The memory area in the cache memory is divided so that a DIR-associated data buffer area used to store a leading address and file name of each file, a FAT-associated data buffer area used to store an address of each file in the next sector, and a data division-associated data buffer area used to store data can all be defined. Addresses referring to the FAT-associated data buffer area and DIR-associated data buffer area are fixed. As a result, as more and more data is read, more and more valid data corresponding to the data residing in the FAT and DIR in a storage medium is found in the cache memory. Consequently, when data reading is requested, data can be transferred without the necessity of reading the storage medium. This results in a shortened reading time.

Abstract: An address translation unit for supporting multiple page modes, with each page mode having a different page size.

Abstract: A distributed-memory multiprocessor system uses fast and main coherency directories to implement cache coherency. The main directory is stored with user data in main memory and includes sufficient information to determine which memory cells have cached copies of user data stored in main memory. In addition, the main directories specify the states of the cached data. The fast directories cache only some of the main-directory information for only a fraction of the main-memory locations at any given time. The fast directories are tagless in one mode and use partial tags in another mode. The fast-directory information is accessed concurrently with main-directory information in response to data requests. Directory information is retrieved first from the fast directory and is used to launch predictive recalls. Subsequently received main-directory information is used to validate or invalidate the predictive recalls.

Abstract: An apparatus and method for selecting a row of memory devices. A row value that indicates one of a plurality of chip select signals is stored in a storage element that is associated with a first address. A memory access request is received that includes the first address. The one of the plurality of chip select signals indicated by the row value is asserted to select one of a plurality of rows of memory devices.

Abstract: A method for implementing a graphics address remapping table as a virtual register in system memory. The remapping table includes virtual registers that each store a target index that references a block of the system memory that stores graphics data. The method uses an indirect addressing scheme that enables the individual virtual registers of the remapping table to be accessed in response to a transaction request. Accessing a selected virtual register indirectly requested by the transaction request enables the method to access graphics data pointed to by the selected virtual register.

Abstract: A memory cache method and apparatus with two memory execution pipelines, each having a translation lookaside buffer (TLB). Memory instructions are executed in the first pipeline (324) by searching a data cache (310) and a prefetch cache (320). A large data TLB (330) provides memory for storing address translations for the first pipeline (324) A second pipeline (328) executes memory instructions by accessing the prefetch cache (320). A second micro-TLB (340) is associated with the second pipeline (328). It is loaded in anticipation of data that will be referenced by the second pipeline (328). A history file (360) is also provided to retain information on previous instructions to aid in deciding when to prefetch data. Prefetch logic (370) determines when to prefetch data, and steering logic (380) routes certain instructions to the second pipeline (328) to increase system performance.

Abstract: A recovery mechanism to eliminate the need to re-fetch cache entries during virtual-to-physical memory re-mapping by reducing accesses and thus the demand on the table lookaside buffer (TLB) during the re-mapping recovery. Once one data block in a given page has been revalidated, the other blocks in the same page can be revalidated without accessing the TLB. If the virtual-to-physical mapping of one data block in a page has not changed, then the other data blocks within the same page also have not changed. Therefore, if a virtual tag was previously valid and a data block on the same page as the data block associated with the virtual tag has been revalidated, the virtual tag is valid and the virtual address can be validated. To identify which virtual tags are currently valid and which virtual tags were valid prior to the last re-mapping, a pair of valid registers is employed. A toggle circuit alternates between the valid registers.

Abstract: A linearly addressed cache capable of fast linear tag validation after a context switch or a translation lookaside buffer (TLB) flush. The cache is configured to validate multiple linear address tags to improve performance in systems which experience frequent context switches or TLB flushes. The cache comprises: a data array configured to store a plurality of cache lines, a linear tag array, a physical tag array, and a TLB. Each array is configured to receive a portion of a requested address. Each linear tag stored in the linear tag array corresponds to one cache line stored within the data array. Each physical tag stored in the physical tag array also corresponds to one cache line stored within the data array. The TLB is configured to store linear to physical address translations, while the linear tag array is configured to store status information for each linear tag. The status information comprises a linear tag valid bit and an enable compare bit.

Abstract: A multifunction access circuit for use with first and second digital computers each having an address bus for supplying addresses and a data bus for supplying data. The access circuit has an address decoder with inputs for the address bus from the first computer, and an address translator circuit having address inputs for addresses supplied by the address bus of the first computer and outputs for translated addresses to the address bus of the second computer. The address translator circuit also has registers selectable by the address decoder and data inputs to program the registers so selected with data from the data bus from the first computer. Also in the access circuit is a port circuit with registers controlled by the address decoder for entry of address information from the data bus of the first computer and assertion of the address information on the address bus of the second computer.

Abstract: A cluster controller for controlling access to local memory and remote data cache in a multiple cluster computer system. In a multiple cluster computer system, a local memory in a cluster is part of the overall system address space. In order to manage local access as well as remote access to the local memory, the cluster controller maintains the responsibility of arbitrating the access to memory. Likewise, data from remote memory stored in the remote data cache is controlled by the cluster controller.

Abstract: In accordance with one aspect of the current invention, the system comprises a memory for storing instruction sequences by which the processor-based system is processed, where the memory includes a physical memory and a virtual memory. The system also comprises a processor for executing the stored instruction sequences. The stored instruction sequences include process acts to cause the processor to: map a plurality of predetermined instruction sequences from the physical memory to the virtual memory, determine an offset to one of the plurality of predetermined instruction sequences in the virtual memory, receive an instruction to execute the one of the plurality of predetermined instruction sequences, transfer control to the one of the plurality of predetermined instruction sequences, and process the one of the plurality of predetermined instruction sequences from the virtual memory.

Abstract: A computer processor that uses an AAHT to provide a guess at the real (absolute) address bits used to access the cache and directories that is more accurate in a high-frequency design which prevents any sort of full or large partial adds of ranges of base, index, or displacement has two index values generated and two AAHT arrays, one each for instruction and operand logical requests. It handles cases in which the data is not directly from the GPR array. For designs that aim at improving performance data for some operations that update GPR's may be used for address generation prior to the execution and write to the GPR array, these include data bypass for Load Address (LA) and Load (L). The system handles instruction fetches, relative branches, other special instruction address instruction fetch requests, and those started as a result of a branch history table (BHT) predicted instruction fetch.

Abstract: Physical page information PA(a) corresponding to logical page information VA(a) as a cache tag address is retained in a logical cache memory 10 and in the event of a cache miss when a shared area is accessed, the physical page information PA (a) retained in the cache memory is compared with physical page information PA (b) resulting from the translation of a search address by TLB. When the result of the comparison is proved to be conformity, the cache entry is processes as a cache hit, so that the problem of a synonym arising from a case where the same physical address is assigned to different logical addresses is solved in such a manner that the number of times access is provided to TLB is halved as compared with the conventional arrangement.

Abstract: A system, method and computer program product for virtual memory support for TLBs with multiple page sizes that require only minor revisions to existing operating system code and remains compatible with existing applications. The virtual memory support provided herein is transparent to many existing operating system procedures and application programs. Various page sizes such as 4 KB, 64 KB, 256 KB, 1 MB, 4 MB and 16 MB page sizes can be used by application programs and each process can use multiple page sizes. Base page sized PTEs and data structures associated with physical pages (PFDATs) are maintained. Maintaining PFDATs and PTEs at a base page level facilitates upgrading and downgrading of memory pages. In addition, different processes can have different views of the same data. Support is provided for upgrading and downgrading memory pages. Examples of operating system methods that can be used for virtual memory support for multiple page sized TLBs are provided herein.

Abstract: A virtual memory system including a local-to-global virtual address translator for translating local virtual addresses having associated task specific address spaces into global virtual addresses corresponding to an address space associated with multiple tasks, and a global virtual-to-physical address translator for translating global virtual addresses to physical addresses. Local-to-global virtual translation is performed by either mapping local virtual addresses to a single global virtual address space or to multiple global virtual address spaces. The local-to-global virtual translator includes a cell which corresponds to each local address space for performing the translations. In a memory system in which both data and instruction address accesses are performed, separate cache and tag structures are employed for handling each of the data and instruction memory accesses. In addition, the cache is configurable such that it can be configured into a buffer portion or a cache portion for faster cache accesses.

Abstract: A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.

Abstract: A unified array access for two logically different arrays is provided. The first array includes CAM cells arranged in n rows and x columns. At least one CAM cell is coupled to a match line, a CAM word line, and to a CAM bit line. The second array includes first RAM cells arranged in n rows and y columns and second RAM cells arranged in n rows and z columns. At least one first RAM cell is coupled to a RAM word line, and to a first RAM bit line. At least one second RAM cell is coupled to the same RAM word line, and a second RAM bit line. RAM word line drivers are provided to activate the first and second RAM cells during a read or write access thereof. At least one RAM word driver has an output coupled to first and second RAM cells. N match sense amplifiers are provided, at least one of which has an input coupled to one of the CAM cells via a match line, and an output coupled to at least one RAM word driver.

Abstract: A microprocessor employs a branch prediction unit including a branch prediction storage which stores the index portion of branch target addresses and an instruction cache which is virtually indexed and physically tagged. The branch target index (if predicted-taken, or the sequential index if predicted not-taken) is provided as the index to the instruction cache. The selected physical tag is provided to a reverse translation lookaside buffer (TLB) which translates the physical tag to a virtual page number. Concatenating the virtual page number to the virtual index from the instruction cache (and the offset portion, generated from the branch prediction) results in the branch target address being generated. In one embodiment, the process of reading an index from the branch prediction storage, accessing the instruction cache, selecting the physical tag, and reverse translating the physical tag to achieve a virtual page number may require more than a clock cycle to complete.

Abstract: A utility that defines additional attributes that would cater to a user's needs provides dynamically extended printing capabilities. The system architecture allows the information to be pushed down transparently to the receiving end, which understands the semantics of the given information. One possible function of the system administrators can be to define information to monitor for accounting purposes. The utility allows additional printer features to be incorporated without disrupting the existing system.

Abstract: A distributed-memory multiprocessor system uses fast and main coherency directories to implement cache coherency. The main directory is stored with user data in main memory and includes sufficient information to determine which memory cells have cached copies of user data stored in main memory. In addition, the main directories specify the states of the cached data. The fast directories cache only some of the main-directory information for only a fraction of the main-memory locations at any given time. The fast directories are tagless in one mode and use partial tags in another mode. The fast-directory information is accessed concurrently with main-directory information in response to data requests. Directory information is retrieved first from the fast directory and is used to launch predictive recalls. Subsequently received main-directory information is used to validate or invalidate the predictive recalls.

Abstract: A system for reducing query traffic in multi-processor shared memory system utilizes the inclusion of an unshared bit in translation table entries in the address translation system. A query system does not generate queries when the unshared bit indicates that the data has not been shared between the processors.

Abstract: A new digital data storage system comprises at least one storage device, a memory and a control device. The storage device retrievably stores a series of records. The memory stores at least one descriptor for describing at least one selected format attribute of the records stored by the storage device, the selected format attribute having a plurality of formatting characteristics. The descriptor includes a series of record format flags, each of which is associated one of the series of records in the storage device. Each record format flag has a first condition indicating that the selected format attribute of the associated record has a predetermined format characteristic, and a second condition indicating that the selected format attribute of the associated record has a format characteristic which is identified elsewhere in the descriptor. The control device uses the record format flags of the descriptor in connection with retrievals of ones of the records from the storage device.

Abstract: A content-addressable memory (CAM) is implemented by using otherwise-unused memory management unit (MMU 102) and cache memories (104, 105) of a program-controlled microprocessor (100). A program stored in an instruction cache (104) and executed by the microprocessor causes the microprocessor to respond to receipt of a word of data (200), which is illustratively the VPI/VCI of an ATM network connection, by applying the most-significant bits (MSBs 202) of the received word as a comparand to tags (203) of entries (206) of a fully-associative translation buffer (103) of the MMU to obtain an index (204) indicative of which translation buffer entry's corresponding tag matches the comparand.

Abstract: A fast, fully associative translation lookaside buffer (TLB) with the ability to store and manage information pertaining to at least two different page sizes is disclosed. The TLB utilizes a tag array with tag lines and a data array with corresponding data lines. Within the tag array, each tag line incorporates a control cell which selectively enables or disables comparisons of tag bits to corresponding bits from an input address to the TLB. Within the data array, each data line incorporates control cells and multiplexing data cells to selectively determine whether bits in the physical address output of the TLB will be the derived from of the contents of the multiplexing data cells or bits from the input address. The use of control cells in the tag array and control cells and multiplexing data cells in the data array thereby provides for the ability to store and manage information pertaining to at least two different page sizes in a single TLB.

Abstract: A computer processor with a mechanism for improved prefetching of instrucns into a local cache includes an instruction pointer multiplexer that generates one of a plurality of instruction pointers in a first pipeline stage, which is used to produce a physical address from an ITLB lookup. A comparison is performed by compare logic between the physical address (and tags) of a set in the local cache and the set associated with the selected instruction pointer. A way multiplexer selects the proper way output from either the compare logic or an instruction streaming buffer that stores instructions returned from the first cache, but not yet written into the local cache. An instruction is bypassed to the way multiplexer from the instruction streaming buffer in response to an instruction streaming buffer hit and a miss signal by the compare logic.