Abstract: A method and apparatus for implementing a page table walker that uses a sliding field in the virtual addresses to identify entries in a page table. According to one aspect of the invention, an apparatus for use in a computer system is provided that includes a page size storage area and a page table walker. The page size storage area is used to store a number of page sizes selected for translating a number of virtual addresses. The page table walker includes a selection unit coupled to the page size storage area, as well as a page entry address generator coupled to the selection unit. For each virtual address received by the selection unit, the selection unit positions a field in that virtual address based on the page size selected for translating that virtual address. In response to receiving the bits in the field identified for each of the virtual addresses, the page entry address generator identifies an entry in a page table based on those bits.

Abstract: A translation lookaside buffer (TLB) for use of a microprocessor, using a content address memory (CAM), includes a block for generating a control clock for precharging a clock and an enable clock for driving data; a CAM block for comparing a linear address with stored data and generating hit signals representing whether or not its comparison result is a coincidence therebetween; a block for decoding the linear address applied from the outside, the linear address being for a distinction of respective entries; a hit signal generating block for outputting selection signals indicating where the hit signals inputted from the CAM block are generated; a block for storing a physical address; a block for selecting one out of the physical addresses outputted from each area of the storing block in response to the selection signal provided from the hit signal generating block; and a block for sensing a signal applied from the selection block.

Abstract: A cache memory holds data of a disk unit on a track unit basis. Recording format information of the track in each disk unit is held in an LTD. For a write request from an upper apparatus, in case of a hit of the cache memory, a write cache control unit finishes a writing process on the cache memory and reports an end of process to the upper apparatus. In case of a mishit of the cache memory, a recording format is analyzed with reference to the LTD and a record position on the track to be developed in the cache memory is recognized, the writing process is finished on the cache memory and an end of process is reported to the upper apparatus.

Abstract: An integrated XNOR flip-flop is provided which is faster than conventional XNOR flip-flop combinations. The integrated XNOR flip-flop is faster and uses less area than conventional XNOR flip-flop combinations. The integrated circuit has few gates along the critical path and takes advantage of the set up times inherent in the flip-flop. Accordingly, the integrated XNOR flip-flop is able to perform the same function in an expedient manner. In one illustrative embodiment, a plurality of the integrated XNOR flip-flops are used to compare a tag of a cache memory with an address to determine whether the desired address is available in the cache.

Abstract: A logical address and a pointer entry for a file in an indirect address file system are translated into a physical address. A decision module tests a pointer flag in a present pointer entry. The pointer entry has a pointer and a pointer flag to identify whether the pointer points to a data storage area or a metadata storage area. The decision module indicates whether the pointer is a data pointer or a metadata pointer. In response to the decision module indicating the pointer is a data pointer, a set module combines the data pointer with the logical address to generate a physical address. A split module, in response to the decision module indicating the pointer is a metadata pointer, divides the logical address into a first portion as an index value and a remaining portion as an offset value. An update module then sets the logical address to the offset value. A retrieve module combines the metadata pointer with the index value to get the next pointer entry.

Abstract: An empty block table is constructed by 64 words.times.8 bits and has 512 memory positions 000H(A0) to IFFH(A511) one-to-one corresponding to 512 blocks BL0 to BL511 within a flash memory FMi. Empty data [a] of 1 bit is stored to each memory position (Aj). This empty data has value "1" when a block BLj corresponding to this memory position (Aj) is in an empty state at present. The empty data also has value "0" when no block BLj corresponding to this memory position (Aj) is in the empty state at present (when data are included in this block).

Abstract: An apparatus and method for translating a virtual address to a physical address utilizing an address translation unit implemented within a network interface card is described. The address translation unit of the present invention is utilized in a computer system. The computer system comprises a first bus; processors with embedded caches and memory coupled to the first bus; a second bus; a network logic coupled to the second bus, wherein the network logic includes an address translation unit; and a bus bridge coupled to the first bus and to the second bus.

Abstract: The method and apparatus are employed within a microprocessor capable of generating speculative memory accesses instructions. Certain instructions access memory locations containing speculatable information while others access memory locations containing non-speculatable information. Memory-type values indicating the speculatability or non-speculatability of memory locations are stored within a translation lookaside buffer. Prior to executing a speculative memory instruction, the microprocessor accesses the translation lookaside buffer to determine whether the memory location targeted by a memory instruction contains speculatable or non-speculatable information. Then, depending upon the memory-type value found in the translation lookaside buffer, execution of the speculative memory instruction is performed immediately or is deferred until the instruction is no longer speculative.

Abstract: Index prediction is used to access data in a memory array. A virtual address is received at an input. The virtual address is translated to a physical address. The memory array is accessed at a predicted address. A portion of the predicted address is compared to a portion of the physical address. If the portion of the predicted address is different from the portion of the physical address, then the predicted address was an incorrect prediction. The memory array is accessed at the physical address.

Abstract: A fetching apparatus (20) is for use in a data processing equipment comprising a processor (11) and a main memory (12). The main memory has a page structure comprising a plurality of pages each of which has a plurality of page data. The fetching apparatus is located between the processor and the main memory. The fetching apparatus fetches the page data of a specific one of the pages as fetched page data from the main memory and supplies the fetched page data to said processor. The fetching apparatus comprises a plurality of registers (23-1 to 23-K) each of which is for memorizing the fetched page data. A table section (24) is for memorizing addresses corresponding the page data in each of the page. The table section further memorizes, as data transfer locations, the memory areas corresponding to the addresses.

Abstract: A semiconductor storage device connectable to a host information processing apparatus having a flash memory section that stores data in sectors and wherein the flash memory section includes an address management table that stores information about the relation between logical sector numbers for data management in a host information processing apparatus and physical sector numbers for data management in the flash memory section. The flash memory section also includes a table state map that stores information about the physical locations at which the sector number information in the address management tables is stored. The semiconductor storage device also includes a flash memory control circuit for controlling data write and data read processing for the flash memory section.

Abstract: A data recording disk drive includes a system and method for mapping around skip sectors, both bad sectors and spare sectors. A received logical block address is converted to a corresponding physical block address by mapping through a set of tables. A first table includes entries for virtual tracks which group together LBAs having shared high order bits. A second table contains entries for the skip sectors. The high order bits of a given LBA are used to select an entry in the first table, which entry is an index into the second table. Starting from the index point, the second table is searched, using the low order bits of the LBA, for a skip sector beyond the LBA value. Once the appropriate skip sector is found, the index of this skip sector within the second table is added to the LBA to compute the PBA. The PBA is then mapped to a zone, cylinder, head, sector location on the disk drive.

Abstract: A computer system includes a memory requester that interfaces with a memory module that includes memory portions. A remapping table that maps each of the defective memory portions to a respective non-defective memory portion in the memory module is created and then stored. Also, a usage table that maps each of a subset of the defective memory portions to a respective non-defective memory portion is created and stored. The defective memory portions of the subset are selected based on which defective memory portions have been most recently used, i.e., requested. In response to receiving from the memory requester a request for access to a requested memory portion of the memory module, a determination is made whether the requested memory portion is one of the defective memory portions mapped in the usage table or remapping table.

Abstract: Apparatus and method for enabling substantially simultaneous access to consecutive entries in an addressable translation memory. The addressable translation memory may be either direct mapped or multi-way set associative. An address decoder receives input address signals and generates output select signals. Each input address signal and each output select signal corresponds to one of the registers in the translation memory. The invention includes a plurality of primary select lines, each of which transmits one of the output select signals to its corresponding register. The invention also includes a plurality of secondary select lines, each of which transmits an output select signal corresponding to a particular register to a second register, the particular register and the second register storing consecutive entries in the translation memory. The particular register and the second register receive the output select signal substantially simultaneously.

Abstract: A method and apparatus for streamlining the installation of virtual to physical address translations into a translation unit. According to one aspect of the invention, an apparatus for use in a computer system is provided that generally includes a translation unit, a default attribute storage area, and a preload unit. The translation unit stores translations for translating virtual addresses into physical addresses, and each of these translations includes an attribute field. The default translation attribute storage area stores a number of default translation attributes. The preload unit is coupled to the default translation unit and the translation unit. In response to receiving a signal from the translation unit indicating a translation for a virtual address is not stored in the translation unit, the preload unit transmits the appropriate default translation attribute to the translation unit.

Abstract: A method and apparatus for installing translations in a translation look-aside buffer. According to the method, each translation contains either a first attribute or a second attribute. Either the first attribute or the second attribute is selected as a default attribute to be preloaded into a translation installation storage area. When it is determined that a translation for translating a virtual address into its corresponding translated address is not stored in the translation look-aside buffer, the attribute area of the translation installation storage area is loaded with the selected default attribute (This translation installation storage area also contains a virtual address area and a translated address area). Then, the translation for the virtual address is determined. The data stored in the translation installation storage area is altered as necessary, to represent the determined translation.

Abstract: An apparatus and method for reducing the number of programming states (threshold voltage levels) required to be traversed when programming a multistate memory cell with a given set of data. The invention first determines the average programming state (corresponding to an average threshold voltage level) for the set of data which is to be programmed into the memory cells. This is accomplished by counting the number of programming states which must be traversed in programming the cells with the data. If the majority of the data requires programming the memory cell(s) to the upper two programming states (in the case of a two bit per cell or four state system), then the data is inverted and stored in the memory in the inverted form. This reduces the amount of programming time, the number of programming states traversed, and the power consumed in programming the memory cell(s) with the data field.

Abstract: An apparatus and method for reducing the cache miss penalty in a virtual memory system is provided. The virtual memory system includes a processor core which generates virtual addresses and a cache configured to supply information in response to receipt of physical addresses. The apparatus includes a logical-to-physical translation unit which converts the virtual addresses generated by the processor core to physical addresses. The logical-to-physical translation unit includes an accurate translation unit, a speculative translation unit, and a comparing unit. The accurate translation unit accurately converts logical addresses to physical addresses. The speculative translation unit generates and transmits a speculative physical address to the cache before the accurate translation unit completes generation of the accurate physical address.

Abstract: A data processing system with a look-up table means for implementing a transfer function with non-uniform resolution comprises a memory to store a plurality of function data; an input to receive external address words for operating on the memory; and an output to provide the function data. The look-up table means comprises a converging means between the input and the memory for mapping specific ones of the external address words onto a specific one of internal address words to access the memory. This greatly reduces memory size. If the transfer function has a symmetry property, a symmetry-handling means further reduces the memory size.

Abstract: A method for performing predictive translation of a data address in a computer processing system includes organizing a translation lookaside buffer in a set associative manner having each set associated with multiple entries, wherein the multiple entries store consecutively ordered selections. Further, the method includes selecting a set of entries in the translation lookaside buffer in response to a base operand for the predictive translation. The method also includes comparing each entry in the selected set with an input address for determining whether or not the predictive translation failed. The method further includes the step of adding the base operand with an offset operand to produce the effective address. A system in accordance with the present invention includes effective address generation logic, including a base operand register to hold a base operand, and a translation lookaside buffer, translation lookaside buffer.

Abstract: A circuit for transferring a logic value from a content addressable memory (CAM) having a plurality of match lines to a random access memory (RAM) having a plurality of word lines. A first logic gate has an input coupled to a first match line of the plurality of match lines, and a second logic gate has an input coupled to a second match line of the plurality of match lines. A first switch is coupled between an output of the first logic gate and a first word line, and a second switch is coupled between an output of the second logic gate and a second word line. The first switch is controlled by the output of the second logic gate such that the first switch is opened when the second match line has a second logic value and closed when the second match line has a first logic value. The second switch is controlled by the output of the first logic gate such that the second switch is opened when the first match line has the second logic value and closed when the first match line has the first logic value.

Abstract: An addressing method and computer system for sharing a large memory address space using address space within an operating system's virtual address space. The system provides sharing the SSB over many processes without the disadvantages associated with process based global sections. For instance, the novel system does not require that each process maintain its own dedicated page table entries (PTEs) in order to access the SSB thereby requiring less operating system virtual memory to maintain the PTE data structures. The system uses a process to switch to kernel mode, then identifies those sections of the operating system virtual memory space that are not being used; in some cases the unused address space can be 1.5-1.8 gigabytes in size. The unused address space is linked together to form the SSB. The system alters the privileges of the PTEs corresponding to the SSB so that user mode processes can access this usually protected operating system virtual memory space.

Abstract: The present invention provides a method and apparatus for providing memory coherency among an L1 and an L2 cache memory devices and a main memory device. In an embodiment of the invention, a memory controller generates an address snoop for locating modified copies of a data residing in the main memory. As a result of the snoop, the memory controller is notified as to whether a modified copy of the data is in the cache memory devices. If both cache memory devices have a modified copy of the data, the modified copy in the L2 cache will not be allowed to be transferred since modified copies of data in the L1 cache memory are considered to always be the most recent copies of the data. Thus, if the L1 cache memory is unable to transfer the data, The memory controller will continue to snoop the address until the L1 cache memory transfers the data.

Abstract: Memory system for internally rearranging fields in database records. The memory is separated into modules, each module separately addressable. Each memory module is addressed by selectively modifying a supplied address, for example by the output from exclusive-OR gates, having inputs from the address supplied to the memory system and another inputs from address modification registers. The address modification registers are selectively set by the external utilization device to permit reading different rows in the memory modules. The data output columns from the memory modules can be rearranged using selector devices such as demultiplexors. Data can be masked by precluding certain selector control signals.

Abstract: A system and method for representing a network according to a hierarchy of views of varying detail. The system models networks as a plurality of interconnected nodes. The display is made more simple by combining network elements (i.e., nodes and connections) in two ways. Nearby nodes within a user-selectable proximity are displayed as a single "supernode." Similarly, connections between all the nodes represented by two supernodes are displayed as a single connection between the supemodes. The system adjusts the relative size of each supernode in proportion to the number of nodes each supernode represents. Similarly, the thickness of each inter-supernode connection is adjusted in proportion to the number of inter-node connections it represents. The system allows a user to conveniently "zoom-in" or "zoom-out," and to adjust the level of detail depicted in the display.

Abstract: A memory management unit (MMU) includes a translation lookaside buffer capable of simultaneously servicing three requests supplied to the MMU by an instruction cache and two data caches, respectively. Also, an arbiter selects one of several pending requests from sources of different priorities for immediate processing by the MMU, using a process which avoids undue delay in servicing requests from sources of lower priority.

Abstract: A tag hit enable method for low power cache operation is provided which comprises inactivating all output buffers during all cache operations generating a tag hit enable signal, enabling/disabling dataram output buffers with said tag signal, activating only said output buffers receiving a hit state from a tag ram in order to transfer data from dataram to a CPU data bus, pre-charging said tag hit signals to tag miss signals, and disabling all data output buffers with said tag miss signals.

Abstract: A cluster controller for controlling access to local memory and remote data cache in a multiple cluster computer system. In a multiple cluster computer system, a local memory in a cluster is part of the overall system address space. In order to manage local access as well as remote access to the local memory, the cluster controller maintains the responsibility of arbitrating the access to memory. Likewise, data from remote memory stored in the remote data cache is controlled by the cluster controller.

Abstract: Allocation circuitry for allocating entries within a set-associative cache memory is disclosed. The set-associative cache memory comprises N ways, each way having M entries and corresponding entries in each of the N ways constituting a set of entries. The allocation circuitry has a first circuit which identifies related data units by identifying a probability that the related data units may be successively read from the cache memory. A second circuit within the allocation circuitry allocates the corresponding entries in each of the ways to the related data units, so that related data units are stored in a common set of entries. Accordingly, the related data units will be simultaneously outputted from the set-associative cache memory, and are thus concurrently available for processing. The invention may find application in allocating entries of a common set in a branch prediction table (BPT) to branch prediction information for related branch instructions.

Abstract: A system and method for reducing access latency to stable storage are described. A technique referred to as fault trickling is used to improve access latency to stable storage such as flash memory. In particular, data requests from a central processing unit are preferentially satisfied by a memory management unit providing access to a main memory. When the requested data does not reside in the main memory, however, the memory management unit satisfies the request by providing direct fine-grain access to the flash memory. In addition, concurrently with satisfying the data request directly from the flash memory, a block transfer is initiated from the flash memory to the main memory. Once the block transfer is completed, a memory map, such as an address translation table, is updated to indicate that the data now resides in the more convenient source of data--the main memory. Accordingly, subsequent data requests, for that or proximately located data, can be satisfied by accessing the main memory.

Abstract: With the present invention, the page table of the program code non-continuously placed in an external storage device using randomly accessible and rewritable memory is built into an executable sequence in a virtual address space of the CPU according to the execution order. By referring to the address translation tables, including the page table, the system is able to read the program from the external storage device, thereby executing the program. Therefore, the program can be executed without being loaded into main memory. Furthermore, the program and data can be managed without distinction.Further, with the randomly accessible memory according to the present invention, since a sequence of real addresses of the CPU are assigned to the data area, control over the direct execution of the program can be simply achieved. Furthermore, since data and ECC parity can also be read and written sequentially, the system has good compatibility with a hard disk system.

Abstract: A computer system having virtual memory that can be mapped using multiple page sizes onto logically addressable physical memory. An intermediate addressing scheme permits the mapping of several non-contiguous small pages in physical memory onto a bigger sized virtual memory page. Rather than translating a virtual address directly into a physical address, a virtual address is translated into an intermediate address that may or may not be a physical address. If the virtual page is backed by physical memory that is contiguous and aligned on a proper boundary for the page size, then the intermediate address will be the physical address and no second translation is required. If the intermediate address is not a physical address, it is then translated into a physical address. This is the case where a big page in virtual memory is backed by more than one smaller page in physical memory.

Abstract: Address translation means for distributed memory massively parallel processing (MPP) systems include means for defining virtual addresses for processing elements (PE's) and memory relative to a partition of PE's under program control, means for defining logical addresses for PE's and memory within a three-dimensional interconnected network of PE's in the MPP, and physical addresses for PE's and memory corresponding to identities and locations of PE modules within computer cabinetry. As physical PE's are mapped into or out of the logical MPP, as spares are needed, logical addresses are updated. Address references generated by a PE within a partition in virtual address mode are converted to logical addresses and physical addresses for routing on the network.

Abstract: Disclosed is a frame processing engine for receiving and processing a data frame having a header and a payload, comprising a first memory for receiving at least a portion of the header of the data frame; a second memory for receiving the payload of the data frame; and a controller, upon receipt of the data frame, for storing the header (at least most of it) in the first memory and the remainder of the data frame (including the payload) in the second memory, with the first memory having a shorter access time than the second memory.

Abstract: A method is disclosed for reusing directory search handles in a manner that minimizes the possibility that a handle allocated for a directory search request that is not yet complete will be reused. This method is implemented by assigning a block of system memory at the time of system initialization for the creation of a set of directory search and information retrieval handle structures. Handle structures within the set are allocated as they are needed. When all have been allocated, they are reused, one at a time in a least-recently-used fashion which gives preference to handle structures which have the lowest probability of being associated with an incomplete search request.

Abstract: The present invention relates to computer systems utilizing a TLB with variable sized pages. This invention detects conflicts between address tags stored in the TLB and a prospective address tag. In particular this invention detects conflicts when the prospective tag represents an address space that overlaps, wholly includes or is included in the address space represented by a tag stored in the TLB. By detecting tag conflicts utilizing hardware, a tremendous performance gain is achieved over systems utilizing prior art software systems.

Abstract: An apparatus and method for disk mapping and data retrieval includes a data storage medium on which has been stored a plurality of data records. Each record includes at least a record identification portion, for uniquely identifying each record from among the plurality of data records. The apparatus builds a record locator table or high speed semiconductor memory which comprises the unique record identifiers for the records on the storage medium as well as a record locator index generated by the apparatus, which indicates the address of the data record on the storage medium. Data retrieval is facilitated by first searching the record locator table in high speed semiconductor memory for a requested data record. Utilizing the record locator index associated with the requested data record, the system directly accesses the requested data record on the storage medium thereby minimizing storage medium search time.

Abstract: A method of caching I/O requests permits caching in the MVS environment independent of the access method protocol used to initiate an I/O request (e.g., QSAM, VSAM, Media Manager). In addition, objects can be user-prioritized for residence in the cache.