Abstract: An apparatus for bypassing an invalidate search of a lookaside buffer includes a filter circuit that directs an invalidate command to a LPID/PID filter of an MMU of a processor and searches for an identifier targeted by the invalidate command. The MMU is external to cores of the processor. The apparatus includes an LPID/PID miss circuit that bypasses searching the lookaside buffer for addresses targeted by the invalidate command and returns a notification that the invalidate command did not identify the identifier targeted by the invalidate command in response to the filter circuit determining that the identifier targeted by the invalidate command is not stored in the LPID/PID filter.

Abstract: Techniques for enabling communication between a virtual machine and the host of the virtual machine are disclosed. An example computing device includes a host operating system and a virtual machine running on the host operating system. The storage device also includes a split driver. The split driver includes a frontend driver residing on the virtual machine and a backend driver residing on the host. The split driver processes messages received from the virtual machine and passes the messages from the frontend driver to the backend driver.

Abstract: Multiprocessor clusters in a virtualized environment conventionally fail to provide memory access security, which is frequently a requirement for efficient utilization in multi-client settings. Without adequate access security, a malicious process may access what might be confidential data that belongs to a different client sharing the multiprocessor cluster. Furthermore, an inadvertent programming error in the code for one client process may accidentally corrupt data that belongs to the different client. Neither scenario is acceptable. Embodiments of the present disclosure provide access security by enabling each processing node within a multiprocessor cluster to virtualize and manage local memory access and only process access requests possessing proper access credentials. In this way, different applications executing on a multiprocessor cluster may be isolated from each other while advantageously sharing the hardware resources of the multiprocessor cluster.

Abstract: To increase the speed with which the hierarchical levels of a Second Layer Address Table (SLAT) are traversed as part of a memory access where the guest physical memory of a virtual machine environment is backed by virtual memory assigned to one or more processes executing on a host computing device, one or more hierarchical levels of tables within the SLAT can be skipped or otherwise not referenced. While the SLAT can be populated with memory correlations at hierarchically higher-levels of tables, the page table of the host computing device, supporting the host computing device's provision of virtual memory, can maintain a corresponding contiguous set of memory correlations at the hierarchically lowest table level, thereby enabling the host computing device to page out, or otherwise manipulate, smaller chunks of memory. If such manipulation occurs, the SLAT can be repopulated with memory correlations at the hierarchically lowest table level.

Abstract: An embodiment of the invention includes a packet processing pipeline. The packet processing pipeline includes match and action stages. Each match and action stage in incurs a match delay when match processing occurs and each match and action stage incurs an action delay when action processing occurs. A transport delay occurs between successive match and action stages when data is transferred from a first match and action stage to a second match and action stage.

Abstract: A memory system includes a nonvolatile memory device including a plurality of memory blocks; and a controller including a command queue adapted to store a plurality of commands from the host, wherein the controller is suitable for managing mapping information for mapping logical addresses of the commands to physical addresses of the nonvolatile memory device, storing partial mapping information into an internal cache memory, storing the whole mapping information into the memory blocks, selecting a piece of victim mapping information among the partial mapping information stored in the internal cache memory, and removing the piece of victim mapping information based on logical addresses of the commands stored in the command queue.

Abstract: Power-fail safe compression and dynamic capacity for a storage device in a computer system is provided. Metadata stored with each logical block in non-volatile memory in the storage device ensures that the mapping table may be recovered and stored in volatile memory for use by the computer system after power is restored to the computer system. In addition, the metadata ensures that a list of free logical block addresses written to the storage device prior to shutting down the computer system to provide access to the additional capacity that is available in the storage device by storing compressed data in the storage device may also be recovered.

Abstract: According to one embodiment, a memory system is provided with a nonvolatile memory, a controller, a volatile memory and an address translation table. The address translation table includes a high level and a plurality of low levels. The high level indicates positions in the nonvolatile memory in which the low levels are recorded. The low levels indicate positions in the nonvolatile memory in which data is recorded. The controller holds the high level of the address translation table in the first area of the volatile memory, and shuts off the supply of power to the second area of the volatile memory based on a transition from a normal-power state to a low-power state.

Abstract: A method for accessing an entry in a translation lookaside buffer and a processing chip are provided. In the method, the entry includes at least one combination entry, and the combination entry includes a virtual huge page number, a bit vector field, and a physical huge page number. The physical huge page number is an identifier of N consecutive physical pages corresponding to the N consecutive virtual pages. One entry is used to represent a plurality of virtual-to-physical page mappings, so that when a page table length is fixed, a quantity of entries in the TLB can be increased exponentially, thereby increasing a TLB hit probability, and reducing TLB misses. In this way, a delay in program processing can be reduced, and processing efficiency of the processing chip can be improved.

Abstract: A guarded storage facility sets up a boundary indicating a range of addresses to be guarded or protected. When a program attempts to access an address in a guarded section defined by the boundary, a guarded storage event occurs. Use of this facility facilitates performance of certain tasks within a computing environment, including storage reclamation.

Abstract: An “RDMA-Based Memory Allocator” applies remote direct memory access (RDMA) messaging to provide fast lock-free memory allocations and de-allocations for shared memory distributed across multiple servers in an RDMA-based network. Alternately, in various implementations, the RDMA-Based Memory Allocator combines RDMA messaging and remote procedure call (RPC) requests to provide fast lock-free memory allocations and de-allocations for shared memory distributed across multiple servers in an RDMA-based network. In either case, any of the networked servers can act as either or both a client for requesting (or releasing) memory allocations and a host for hosting a portion of the distributed memory. Further, any server (including the requesting client) may act as the host for the distributed memory being allocated or de-allocated by any client via RDMA messaging. Advantageously, being lock-free improves overall performance of memory access between networked computers by reducing overall system latency.

Abstract: A method and arrangement are disclosed involving receiving a read-type command at a data storage arrangement, calculating a command span of the received read-type command and performing a look-up command, through use of a processor, for data located in each extent at a condensed logical block address state table for the read-type command, wherein the condensed logical block address state table describes a logical to physical table and at least one of transmitting data and displaying data related to the read-type command found in the condensed logical block address state table.

Abstract: A client application of a content management system provides instructions for synchronizing content items and placeholder items using a local file journal and updated file journal. The client application compares entries in the updated file journal to entries in the local file journal to determine modifications to make to content items or placeholder items stored in a shared content storage directory on the client device. Based on the result of the comparison, the client application replaces placeholder items with content items or replaces content items with placeholder items.

Abstract: According to one embodiment, a memory system copies content of a first logical-to-physical address translation table corresponding to a first region of a nonvolatile memory to a second logical-to-physical address translation table corresponding to a second region of the nonvolatile memory. When receiving a read request specifying a logical address in the second region, the memory system reads a part of the first data from the first region based on the second logical-to-physical address translation table. The memory system detects a block which satisfies a refresh condition from a first group of blocks allocated to the first region, corrects an error of data of the detected block and writes the corrected data back to the detected block.

Abstract: A computer-implemented method according to one embodiment includes identifying a host within a container environment, and mapping a volume of a container to the host within the container environment, utilizing small computer system interface (SCSI) second level addressing.

Abstract: In one embodiment, an apparatus includes a page miss handler to receive a full address including a linear address portion having a linear address and a key identifier portion having a key identifier for a key. The page miss handler may insert an entry including this key identifier in a translation storage. The apparatus further may include a remapping table having a plurality of entries each to store information regarding a key identifier. Other embodiments are described and claimed.

Abstract: In accordance with embodiments of the present disclosure, a system may include a processor and a storage interface configured to sequentially select, one at a time, member storage resources of a virtual storage resource as a source storage resource for redirection of write input/output (I/O) and for each member storage resource, when selected as the source storage resource, in response to write I/O, redirect the write I/O to a spare storage resource available to the virtual storage resource.

Abstract: An operating method for a data storage device is provided. The operating method includes steps of: dividing a mapping table into a plurality of sub-mapping tables; receiving an access command comprising a data address and a command category; determining whether a target sub-mapping table corresponding to the data address has been cached, wherein the target sub-mapping table is one of the sub-mapping tables; and if false, reading and caching the target sub-mapping table from the sub-mapping tables.

Abstract: An apparatus and method are provided for controlling use of bounded pointers. The apparatus has a plurality of bounded pointer storage elements, each bounded pointer storage element being used to store a bounded pointer and associated permission attributes indicative of allowed uses of the bounded pointer. In accordance with the present technique, the associated permission attributes include a copy permission attribute indicating whether the bounded pointer is allowed to be subjected to a copy operation. Processing circuitry is then responsive to at least one instruction that specifies the copy operation, to generate, from a source bounded pointer and associated permission attributes of a source bounded pointer storage element, a destination bounded pointer and associated permission attributes to be stored in a destination bounded pointer storage element.

Abstract: An electronic device and a method for managing memory thereof are disclosed. According to an embodiment of the present disclosure, a method for an electronic device to manage memory, comprising: determining whether a physical address mapped to a virtual address is consecutive with respect to at least two entries belonging to a plurality of entries having virtual addresses and physical addresses mapped and including a consecutive virtual address; merging entries in which the virtual address and the physical address are consecutive into one entry if, as a result of the determination, the physical addresses of the at least entries are consecutive; and storing the merged entry in first memory.

Abstract: An example method of scanning a guest virtual address (GVA) space generated by a guest operating system executing in a virtual machine of a virtualized computing system includes setting, in a scan of the GVA space by a hypervisor that manages the virtual machine, a current GVA to a first GVA in the GVA space; executing, on a processor allocated to the virtual machine, an address translation instruction, which is in an instruction set of the processor, to perform a first address translation of the current GVA; reading a register of the processor to determine a first error resulting from the first address translation; determining, in response to the first error, a level of a faulting page table in a first page table hierarchy generated by the guest operating system; and setting the current GVA to a second GVA based on the level of the faulting page table.

Abstract: A storage device includes a nonvolatile storage and a controller. The controller is configured to compress data received from a host in association with a write command designating a first data length as a length of the data and a starting logical address of the data, into compressed data of a second data length shorter than the first data length, write the compressed data in the nonvolatile storage. Further, the controller is configured to generate an address mapping for the data, such that a first logical address range that starts at the starting logical address is mapped to a physical region of the nonvolatile storage having a size equal to the second data length, and a second logical address range that directly follows the first logical address range is not mapped to any physical region of the nonvolatile storage.

Abstract: A computer program product for optimizing page table manipulations is provided and includes a computer readable storage medium having program instructions that are readable and executable by a processing circuit to cause the processing circuit to create and maintain a translation table with a translation look-aside buffer (TLB) disposed to cache priority translations, update the translation table upon de-registration of a DMA address, allocate entries in the translation table from low to high memory addresses during memory registration, maintain a cursor for identifying where to search for available entries upon performance of a new registration, advance the cursor from entry-to-entry in the translation table and wrap the cursor from an end of the translation table to a beginning of the translation table and issue a synchronous TLB invalidation instruction to invalidate the TLB upon at least one wrapping and an entry being identified and updated.

Abstract: An aspect includes receiving a request to access data in a memory, the request from a requesting processor and including a virtual address of the data. It is determined, based on contents of a page table that a plurality of physical addresses in the memory corresponds to the virtual address. The physical addresses include a first physical address of a primary memory location in a first partition accessed via a bus that is communicatively coupled to a port of a first processor, and a second physical address of a secondary memory location in a second partition accessed via a bus that is communicatively coupled to a port of a second processor. Contents of the primary memory location in the first partition were previously copied into the secondary memory location. Based on the requesting processor, one of the physical addresses is selected and data at the selected physical address is accessed.

Abstract: An aspect includes receiving a request to access data in a memory, the request from a requesting processor and including a virtual address of the data. It is determined, based on contents of a page table that a plurality of physical addresses in the memory corresponds to the virtual address. The physical addresses include a first physical address of a primary memory location in a first partition accessed via a bus that is communicatively coupled to a port of a first processor, and a second physical address of a secondary memory location in a second partition accessed via a bus that is communicatively coupled to a port of a second processor. Contents of the primary memory location in the first partition were previously copied into the secondary memory location. Based on the requesting processor, one of the physical addresses is selected and data at the selected physical address is accessed.

Abstract: Method, system and product for direct access to de-duplicated data units in memory-based file systems. The method comprising: updating a page entry in a page table of a process to include a direct access pointer to a de-duplicated data unit retained by the memory-based file system, wherein the page entry is set to be write protected; detecting a page fault occurring due to the process performing a store instruction to the de-duplicated data unit; and in response to said detecting: allocating a new data unit; copying content of the de-duplicated data unit to the new data unit; and replacing the direct access pointer to the de-duplicated data unit with a direct access pointer to the new data unit.

Abstract: A method is provided for providing access to a data block in a device of a processing system. The device is connected to a processor of the processing system via an extension bus, and the processing system includes a memory connected to the processor via a memory bus, an operating system and hardware and/or firmware components for controlling access to the device. The method includes adding by the operating system for the data block a first entry in a page table of the processing system. The added entry represents the data block. A memory management unit (MMU) of the processing system may receive a request of the data block. Upon receiving the request, the MMU may instruct one of the hardware or firmware components to provide access to the data block using the added entry.

Abstract: Systems and methods for enabling a user space process of a guest operating system to initiate hardware operations in a security-enhanced manner. An example method may comprise: configuring a storage unit to store one or more resource requests, the storage unit being accessible to a user space process managed by a guest operating system and to a hypervisor; determining, by a processing device, that the user space process managed by the guest operating system is authorized to store a resource request at the storage unit; and transmitting to the hypervisor a signal associated with the storage unit comprising the resource request, the signal being initiated by a hypercall executed by the user space process.

Abstract: Techniques for virtualizing NVDIMM WPQ flushing with minimal overhead are provided. In one set of embodiments, a hypervisor of a computer system can allocate a virtual flush hint address (FHA) for a virtual machine (VM), where the virtual flush hint address is associated with one or more physical FHAs corresponding to one or more physical memory controllers of the computer system. The hypervisor can further determine whether one or more physical NVDIMMs of the computer system support WPQ flushing. If so, the hypervisor can write protect a guest physical address (GPA) to host physical address (HPA) mapping for the virtual FHA in the page tables of the computer system, thereby enabling the hypervisor to trap VM writes to the virtual FHA and propagate those write to the physical FHAs of the system.

Abstract: Methods, computer program products, and systems are presented. The methods computer program products, and systems can include, for instance: determining an insertion interval of a row for insertion into a decision table; and guiding insertion of the row for insertion into the decision table based on a result of the determining.

Abstract: Embodiments of the present invention provide memory optimization by phase-dependent data residency. Application programs are profiled a priori or in real time for temporal memory usage. Memory regions such as initialization data are proactively removed from memory when the application transitions to a new phase. A hypervisor monitors application activity and coordinates the removal of memory regions that are no longer needed by the application. Additionally, memory regions that are anticipated to be needed in the future are proactively preloaded.

Abstract: An information processing apparatus includes a memory and a processor configured to obtain information on a relation between virtual volumes used by a virtual machine and physical volumes provided in a storage apparatus from a management machine configured to manage allocations of the virtual volumes to the physical volumes; store the obtained information into a management information stored in the memory; and in response to receiving a copy request, obtain information on a first physical volume allocated to the first virtual volume designated as a copy participant in the copy request from the management information when the information on the first virtual volume is present in the management information, and send the storage apparatus a copy instruction designating the first physical volume as a copy participant. Obtain the information on the relation is performed when the information on the first virtual volume is not present in the management information.

Abstract: An apparatus and method for best effort quality of service scheduling in a graphics processing architecture. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) to perform graphics processing operations for a plurality of guests; a plurality of buffers to store one or more graphics commands associated with each guest to be executed by the GPU; and a scheduler to evaluate commands in the buffers of a first guest to estimate a cost of executing the commands, the scheduler to select all or a subset of the buffers of the first guest for execution on the GPU based on a determination that the selected buffers can be executed by the GPU within a remaining time slice allocated to the first guest.

Abstract: In one non-limiting embodiment, a method is disclosed for performing a storage device operation on a die is provide having steps of choosing a storage device operation to perform, estimating which die is related to the storage device operation chosen to be performed and performing the storage device operation at the die based on the estimating.

Abstract: A health-monitoring system and method are disclosed. The health-monitoring system and method comprise a sensory system and a sensory to front-end communication (SFCM) protocol coupled to the sensory system. The health-monitoring system and method include a front-end system coupled to the sensory system and a front-end to back-end communication (FBCM) protocol coupled to the front-end system. The health-monitoring system and method include a back-end system. The SFCM protocol communicates with the front-end system using a first state awareness link and the FBCM protocol communicates with the back-end system using a second state awareness link.

Abstract: Implementations of the present disclosure include receiving a sorted list of pages, each page corresponding to a fixed-length contiguous block of virtual memory, and being associated with a respective state, each state indicating a number of off-chip accesses determined for a respective page, and executing an application, which queries an in-memory database provided with a hybrid memory system, and, during execution of the application: identifying at least one page in the sorted list of pages as a page that is to-be-locked during execution of the application based on a threshold, and locking the at least one page in main memory to inhibit swapping of the at least one page by an operating system.

Abstract: Processing a request for delivery of data sent by a customer terminal to a remote server via a telecommunication network. The terminal accesses the network by at least two links of distinct access types. The data is encoded in a stream with a predetermined bit rate, which is cut into segments. Processing includes, for a segment of the stream: determining a sub-segment size based on the number of links and a size of the data stream to be delivered; calculating a partitioning of the segment into sub-segments according to the set size and a distribution of the sub-segments on the plurality of links, according to a scheduling of the sub-segments in the partitioning and a time constraint; and sending a plurality of sub-segment transmission requests to the server over the plurality of links, each request including an identifier of the segment and indexes of a sub-segment start and end.

Abstract: This technology relates to a memory system for processing data into a memory device and an operating method of the same. The memory system may include a memory device comprising a plurality of memory blocks, each memory block comprising a plurality of pages each page having a plurality of memory cells coupled to a plurality of word lines, the memory device being suitable for storing data requested by a host, and a controller suitable for programming data corresponding to a first write command received from the host into a first memory block of the memory blocks, receiving a second write command for the data programmed into the first memory block from the host, performing an update program on the data programmed into the first memory block into the memory blocks, and generating a map list for the first memory block according to the update program.

Abstract: A hardware forwarding element is provided that includes a group of unit memories, a set of packet processing pipelines, and an error signal fabric. Each packet processing pipeline includes several of match action stages. Each match action stage includes a set of match action tables stored in a set of unit memories. Each unit memory is configured to detect an error in the unit memory and generate an error output when an error is detected in the memory unit. The error signal fabric, for each match action stage, combines error outputs of the unit memories storing match tables into a first bit in the error signal fabric. The error signal fabric, for each match action stage, combines error outputs of the unit memories storing action tables into a second bit in the error signal fabric.

Abstract: In an aspect, an apparatus that includes a first security domain and at least a second security domain obtains, at a virtual machine of the first security domain, a stream identifier associated with the second security domain. The apparatus generates, at the virtual machine of the first security domain, a command to map the stream identifier associated with the second security domain to a first address translation context. The apparatus maps, at a hypervisor device, the first address translation context to a second address translation context that is associated with the second security domain of the stream identifier. The apparatus processes a stream of memory access transactions that includes the stream identifier based on at least the first address translation context or the second address translation context.

Abstract: Relationships between data in database tables are obfuscated. An input data set is divided into two database tables with corresponding rows. A key field if created in a second one of the tables, and for each row, the field is populated with a value generated with a one-way function, using a unique value associated with the corresponding row of the first one of the tables as an input. The two tables are stored in a data store, so that the data in corresponding rows may be associated only with access to the one way function, and the unique value associated with a row of the first table.

Abstract: Embodiments of an invention for address translation for scalable I/O device virtualization are disclosed. In one embodiment, an apparatus includes PASID table lookup circuitry. The PASID table lookup circuitry is to find a PASID-entry in a PASID table. The PASID-entry is to include a PASID processing mode (PPM) indicator and a first pointer to a first translation structure. The PPM indicator is to specify one of a plurality of translation types, the one of the plurality of translation types to use the first translation structure.

Abstract: A method and system for enabling Non-Volatile Memory express (NVMe) for accessing remote solid state drives (SSDs) (or other types of remote non-volatile memory) over the Ethernet or other networks. An extended NVMe controller is provided for enabling CPU to access remote non-volatile memory using NVMe protocol. The extended NVMe controller is implemented on one server for communication with other servers or non-volatile memory via Ethernet switch. The NVMe protocol is used over the Ethernet or similar networks by modifying it to provide a special NVM-over-Ethernet frame.

Abstract: Described herein are enhancements for managing multi-host Peripheral Component Interconnect Express (PCIe) switching. In one implementation, a system includes one or more PCIe devices and a PCIe switch configured to receive a first interrupt corresponding to a first interrupt vector from a PCIe device, wherein the first interrupt vector comprises at least a virtual address and a first data value. The switch is further configured to translate the first interrupt vector into a second interrupt vector, wherein the second interrupt vector comprises a second address and a second data value, and transfer a second interrupt using the second interrupt vector to a host of a plurality of hosts that corresponds to the second interrupt vector.

Abstract: A system and method is provided for managing computing resources of a physical server executing a plurality of virtual machines (VMs) including a first virtual machine (VM). The first VM executes a guest block device driver configured to provide a guest operating system of the first VM an interface to a memory-mapped virtual storage device. A virtual machine monitor maintains a disk cache associated with the virtual storage device. The disk cache resides in a host physical memory of the physical server outside of portions of the host physical memory associated with guest physical memory of the first VM. The virtual machine monitor is configured to, responsive to determining that available host physical memory satisfies a threshold condition, reclaim a target portion of the host physical memory allocated to the disk cache.

Abstract: Decentralized deduplication operations in a computer system employ a hash index that is a variant of a B+ tree to support both efficient sequential updates as well as efficient random updates. Sequential update is selected when deduplication is infrequently performed, such as on the order of days, and random update is selected when deduplication is performed more frequently, such as on the order of seconds. More frequent deduplication may be beneficial during periods when large amounts of temporary duplicate data are created, and the system may not have enough storage space to accommodate the temporary spike in demand.

Abstract: There is described a method and data processing apparatus configured to translate a virtual address into a physical address, the virtual address comprising an offset for a memory page, an index and a tag with the memory page having a variable size.

Abstract: A method for retrieving a virtual address from a physical address accesses in a memory of a computing system, to which that virtual address was previously mapped to, may include: using a monitor to intercept transmissions to and from a memory of a computing system; using a processor: identifying in the intercepted transmissions page table address calls relating to mapping of a virtual address to a physical address; and retrieving the virtual address from the identified page table address calls.

Abstract: According to an embodiment, a semiconductor storage device includes a detection circuit configured to detect an error in data read from a first memory cell array. The read data of a size corresponding to a page unit is subjected to detection of an error for each of a plurality of first units into which the page unit is divided. When performing a first operation of concurrently executing outputting of first data read from the first memory cell array to an outside and reading of second data different from the first data from the first memory array, an interface circuit is configured to output information based on the error detected with respect to the first data to the outside.

Abstract: In a computer system having virtual machines, one or more unused bits of a guest physical address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a common memory page. When one bit is allocated for aliasing, dirty bit information can be provided at a granularity that is one-half of a memory page. When M bits are allocated for aliasing, dirty bit information can be provided at a granularity that is 1/(2M)-th of a memory page.