Abstract: The storage system comprises a plurality of flash packages configuring one or more RAID groups, and a controller coupled to the plurality of flash packages. Each flash package comprises a plurality of flash chips configured from a plurality of physical blocks. The controller identifies a target area related to an unnecessary area, unmaps a physical block allocated to a logical block belonging to this target area from this logical block, and manages the unmapped physical block as a free block.

Abstract: A method for data storage includes, in a memory that includes multiple memory blocks, specifying at a first time a first over-provisioning overhead, and storing data in the memory while retaining in the memory blocks memory areas, which do not hold valid data and whose aggregated size is at least commensurate with the specified first over-provisioning overhead. Portions of the data from one or more previously-programmed memory blocks containing one or more of the retained memory areas are compacted. At a second time subsequent to the first time, a second over-provisioning overhead, different from the first over-provisioning overhead, is specified, and data storage and data portion compaction is continued while complying with the second over-provisioning overhead.

Abstract: Solid-state storage management for a system that includes a main board and a solid-state storage board separate from the main board is provided. The sold-state storage board includes a solid-state memory device and solid-state storage devices. The system is configured to perform a method that includes a correspondence being established, by a software module located on the main board, between a first logical address and a first physical address on the solid-state storage devices. The correspondence between the first logical address and the first physical address is stored in a location on the solid-state memory device. The method also includes translating the first logical address into the first physical address. The translating is performed by an address translator module located on the solid-state storage board and is based on the previously established correspondence between the first logical address and the first physical address.

Abstract: Embodiments of the invention include systems and methods for auto-tiering multiple file systems across a common resource pool. Storage resources are allocated as a sub-LUN auto-tiering (SLAT) sub-pool. The sub-pool is managed as a single virtual address space (VAS) with a virtual block address (VBA) for each logical block address of each data block in the sub-pool, and a portion of those VBAs can be allocated to each of a number of file systems. Mappings are maintained between each logical block address in which file system data is physically stored and a VBA in the file system's portion of the virtual address space. As data moves (e.g., is added, auto-tiered, etc.), the mappings can be updated. In this way, multiple SLAT file systems can exploit the full resources of the common SLAT sub-pool and maximize the resource options available to auto-tiering functions.

Abstract: A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: providing at least one block of the memory apparatus with at least one local page address linking table within the memory apparatus, wherein the local page address linking table includes linking relationships between physical page addresses and logical page addresses of a plurality of pages; and building a global page address linking table of the memory apparatus according to the local page address linking table. More particularly, the step of providing the block with the local page address linking table further includes: building a temporary local page address linking table for the local page address linking table corresponding to programming/writing operations of the memory apparatus; and temporarily storing the temporary local page address linking table in a volatile memory of the memory apparatus, and updating the temporary local page address linking table when needed.

Abstract: A cache entry replacement unit can delay replacement of more valuable entries by replacing less valuable entries. When a miss occurs, the cache entry replacement unit can determine a cache entry for replacement (“a replacement entry”) based on a generic replacement technique. If the replacement entry is an entry that should be protected from replacement (e.g., a large page entry), the cache entry replacement unit can determine a second replacement entry. The cache entry replacement unit can “skip” the first replacement entry by replacing the second replacement entry with a new entry, if the second replacement entry is an entry that should not be protected (e.g., a small page entry). The first replacement entry can be skipped a predefined number of times before the first replacement entry is replaced with a new entry.

Abstract: A memory management device, an image forming apparatus, and an image forming method include an OS-management-memory-region managing unit configured to divide a physical memory space into a management region managed by an OS and a non-management region that is not managed by the OS, assign the management region to the virtual memory space, and acquire and/or free a memory space of the management region. The image forming apparatus includes an OS-non-management-memory-region managing unit assigning the non-management region to the virtual memory space so that an application program acquires and/or frees a memory space of the non-management region. The OS-management-memory-region managing unit includes a window region provided so that the OS refers to the non-management region. Data is read and/or written from and/or into the OS-non-management region via the window region.

Abstract: A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: building at least one local page address linking table containing a page address linking relationship between a plurality of physical page addresses and at least a logical page address, wherein the local page address linking table includes a first local page address linking table containing a first page address linking relationship of a plurality of first physical pages, and a second local page address linking table containing a second page address linking relationship of a plurality of second physical pages that are different from the first physical pages; building a global page address linking table according to the local page address linking table; and accessing the memory apparatus according to the global page address linking table.

Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A size of the partition control area of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.

Abstract: The invention pertains to a memory management unit for a microprocessor system, the memory management unit being connected or connectable to at least one processor core of the microprocessor system and being connected or connectable to a physical memory of the microprocessor system. The memory management unit is adapted to selectively operate in a hypervisor mode or in a supervisor mode, the hypervisor mode and the supervisor mode having different privilege levels of access to hardware The memory management unit comprises a first register table indicating physical address information for mapping at least one logical physical address and at least one actual physical address onto each other; a second register table indicating an allowed address range of physical addresses accessible to a process running in or under supervisor mode; wherein the memory management unit is adapted to prevent write access to the second register table by a process not in hypervisor mode.

Abstract: Techniques described enable efficient swapping of memory pages to and from a working set of pages for a process through the use of large writes and reads of pages to and from sequentially ordered locations in secondary storage. When writing pages from a working set of a process into secondary storage, the pages may be written into reserved, contiguous locations in a dedicated swap file according to a virtual address order or other order. Such writing into sequentially ordered locations enables reading in of clusters of pages in large, sequential blocks of memory, providing for more efficient read operations to return pages to physical memory.

Abstract: A content addressable memory system, method and computer program product is described. The memory system comprises a location addressable store having data identified by location and multiple levels of content addressable stores each holding ternary content words. The content words are associated with references to data in the location addressable store. The content store levels might be implemented using different technologies that have different performance, capacity, and cost attributes. The memory system includes a content based cache for improved performance and a content addressable memory management unit for managing memory access operations and virtual memory addressing.

Abstract: A technique is provided for handling dynamically linked subject function calls arranged pass subject control flow to an intermediate control structure such as a procedure linkage table, then to subject linker code for modifying link information associated with the subject function calls during translation of subject code into target code in a dynamic binary translator. The subject code for execution on a subject processor is received by a translator, and corresponding target code for execution on the target processor is generated. The translator is arranged to build a function linkage table containing an entry giving the location of each function called by the subject code, so that code can be generated by the translator in which subject function calls are associated with code for performing the function, without generating target code corresponding to the intermediate control structure.

Abstract: A computer implemented method optimizes memory page sizes during runtime. A process is identified from a policy file. The policy file contains at least one policy based threshold. A resource usage profiler monitors the process during runtime. The resource usage profiler determines whether the process exceeds the set of stated desired policies from the at least one policy based threshold. If the process exceeds the set of stated desired policies from the set of policy based thresholds, a performance projection for the process is executed to determine whether the process would experience a performance benefit from a different page size. Responsive to determining that the process would experience the performance benefit from the different page size, the page size for the process is changed.

Abstract: An apparatus and method for processing data in a Massively Parallel Process Array (MPPA) system are provided, in which a scheduling processor determines an array processor and an initial memory, and requests halt release to the array processor, which requests allocation of an additional memory or return of used memory to an address conversion controller, if allocation of additional memory or return of used memory is needed during program execution. The address conversion controller controls, upon receipt of the request for allocation of additional memory, conversion of a base address of additional memory to a physical address and, upon receipt of the request for return of used memory, deletes registered information from the address conversion table. The array processor requests return of additional memory to the address conversion table and transmits a terminal signal to the scheduling controller, upon completion of the program.

Abstract: Method and system for supporting multiple byte order formats, separately or simultaneously, are provided and described. In one embodiment, a page attribute table (PAT), which is programmable, is utilized to indicate byte order format. In another embodiment, a memory type range register (MTRR), which is programmable, is utilized to indicate byte order format.

Abstract: Memory management methods and computing apparatus with memory management capabilities are disclosed. One exemplary method includes mapping an address from an address space of a physically-mapped device to a first address of a common address space so as to create a first common mapping instance, and encapsulating an existing processor mapping that maps an address from an address space of a processor to a second address of the common address space to create a second common mapping instance. In addition, a third common mapping instance between an address from an address space of a memory-management-unit (MMU) device and a third address of the common address space is created, wherein the first, second, and third addresses of the common address space may be the same address or different addresses, and the first, second, and third common mapping instances may be manipulated using the same function calls.

Abstract: An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.

Abstract: An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.

Abstract: An electronic device with improved flash memory compatibility and a method corresponding thereto are disclosed. The electronic device has a NAND flash, a processing unit and a program memory. The program memory stores application software and codes of an operating system, to be retrieved and executed by the processing unit. The application software requests for NAND flash access in accordance with a specific page size. The operating system acts as an intermediary between the application software and the NAND flash and provides a device driver which allocates a number of physical pages of the NAND flash to each virtual page of the specific page size for responding to NAND flash access requests from the application software by referring to the virtual pages.

Abstract: This disclosure provides a method for assigning data in an information handling system including a plurality of physical storage resources comprising a first tier and a second tier which has a lower performance and cost relative to capacity than the first tier. A tier manager may be hosted on the information handling system and in electronic communication with the plurality physical storage resources. The tier manager may, for each page: determine a seek distance value, determine an operation rate, determine an operation size value, determine an elapsed time value, and calculate a relative randomness value using the seek distance value, operation rate, operation size value, and elapsed time value determined for each page. A classification module may assign a physical location for each page such that the relative randomness value for each page in the first tier is greater than in the second tier.

Abstract: Apparatuses and methods for storing a validity mask and operating apparatuses are described. A number of methods for operating an apparatus include storing a validity mask that is associated with a number of pages of memory cells in a group of pages and that provides validity information for the number of pages of memory cells in the group of pages.

Abstract: A memory system maps physical addresses to device addresses in a way that reduces power consumption. The system includes circuitry for deriving efficiency measures for memory usage and selects from among various address-mapping schemes to improve efficiency. The address-mapping schemes can be tailored for a given memory configuration or a specific mixture of active applications or application threads. Schemes tailored for a given mixture of applications or application threads can be applied each time the given mixture is executing, and can be updated for further optimization. Some embodiments mimic the presence of an interfering thread to spread memory addresses across available banks, and thereby reduce the likelihood of interference by later- introduced threads.

Abstract: A method for managing software modules of at least two operating systems sharing physical resources of a computing environment, but running in different partitions separated by a virtualization boundary comprises accumulating module information in a virtualization subsystem that directs the creation and management of the partitions. The accumulated module information is used across the virtualization boundary to manage the use of the software modules. Also, a method for managing software modules comprises making at least two operating systems aware that they are being hosted in a virtualized computing environment.

Abstract: The invention concerns a method of managing computer memory, the method comprising the steps of maintaining (101) a page table entry for mapping a virtual address to a physical address and a cache comprising a plurality of data blocks and, in response to a reference to the virtual address, translating (102) the virtual address into the physical address by means of the page table entry and fetching (103) data from the physical address into the cache, wherein the page table entry comprises a plurality of indicators, each data block corresponding to an indicator, and, upon fetching the-data into the cache, the method comprises the further step of, in response to an indicator being set, zeroing (104) the corresponding data block. The invention further concerns a computer program product and a device therefor.

Abstract: A data storage device is disclosed comprising a non-volatile memory comprising a plurality of memory segments. When a write command comprising a logical block address (LBA) is received, a number of consecutive memory segments to access in response to the write command is determined. When the number of consecutive memory segments to access is greater than a threshold, a new run-length mapping entry in a run-length mapping table (RLMT) is created. When the number of memory segments to access is not greater than a threshold, at least one new single address mapping entry in a single address mapping table (SAMT) is created.

Abstract: The apparatus includes a virtual address space generation unit generating a virtual address space of a guest operating system, the guest operating system being executed in the virtual address space, and a virtual address space of a virtual machine monitor, the virtual machine monitor being executed in the virtual address space; a gateway page generation unit generating a gateway page allocated to a predetermined region of an actual memory region and mapped to the virtual address space of the guest operating system and the virtual address space of the guest machine monitor; and a memory management unit executing the gateway page to map a kernel region of the guest operating system to the predetermined region of the virtual address space of the virtual machine monitor to perform translation between the virtual address space of the guest operating system and the virtual address space of the virtual machine monitor.

Abstract: A volume manager I/O method and system. The method includes determining a storage extent mapping of storage functionality of a plurality of storage devices and generating a logical disk extent based on the storage extent mapping. The logical disk extent is exported to a volume device component that is communicatively coupled to implement I/O for an application. An I/O request from the application is received via the volume device component. The I/O request is executed in accordance with the logical disk extent.

Abstract: A network unit, comprising a processor and a random access memory (RAM) component coupled to the processor, wherein the RAM component comprises a memory management unit (MMU) and a data RAM, wherein the MMU comprises a complete page address table for translating a virtual memory address received from the processor into a physical memory address, and wherein the complete page address table is substantially static.

Abstract: Example methods, apparatus, and articles of manufacture to access memory are disclosed. A disclosed example method involves receiving at least one runtime characteristic associated with accesses to contents of a memory page and dynamically adjusting a memory fetch width for accessing the memory page based on the at least one runtime characteristic.

Abstract: An address translation apparatus includes: a first address translation unit to hold, first address information, validity information and correspondence information, the first address information indicating correspondence between a virtual address and a physical address, the validity information indicating a validity of the first address information, and the correspondence information indicating correspondence between first context information corresponding to the first address information and second context information in an access request; an information holding unit to hold context information in the first address information; a comparison unit to compare the first context information with the second context information and update the correspondence information based on a comparison result; and a control unit to search a new first entry having the first address information including the same virtual address as in the access request based on the validity information and the correspondence information and out

Abstract: A tier identification (TID) is to indicate a characteristic of a memory region associated with a virtual address in a tiered memory system. A thread may be serviced according to a first path based on the TID indicating a first characteristic. The thread may be serviced according to a second path based on the TID indicating a second characteristic.

Abstract: A microprocessor includes a translation lookaside buffer, a request to load a page table entry into the microprocessor generated in response to a miss of a virtual address in the translation lookaside buffer, and a prefetch unit. The prefetch unit receives a physical address of a first cache line that includes the requested page table entry and responsively generates a request to prefetch into the microprocessor a second cache line that is the next physically sequential cache line to the first cache line.

Abstract: Responding to IO requests made by an application to an operating system within a computing device implements IO performance acceleration that interfaces with the logical and physical disk management components of the operating system and within that pathway provides a system memory based disk block cache. The logical disk management component of the operating system identifies logical disk addresses for IO requests sent from the application to the operating system. These addresses are translated to physical disk addresses that correspond to disk blocks available on a physical storage resource. The disk block cache stores cached disk blocks that correspond to the disk blocks available on the physical storage resource, such that IO requests may be fulfilled from the disk block cache.

Abstract: A system and method for efficiently handling translation look-aside buffer (TLB) misses. A memory management unit (MMU) detects when a given virtual address misses in each available translation-lookaside-buffer (TLB). The MMU determines whether a memory access operation associated with the given virtual address is the oldest, uncompleted memory access operation in a scheduler. If this is the case, a demand table walk (TW) request may be stored in an available entry in a TW queue. During this time, the utilization of the memory subsystem resources may be low. While a demand TW request is stored in the TW queue, subsequent speculative TW requests may be stored in the TW queue. When the TW queue does not store a demand TW request, no more entries of the TW queue may be allocated to store TW requests.

Abstract: In one embodiment, a system comprises multiple memory ports distributed into multiple subsets, each subset identified by a subset index and each memory port having an individual wait time. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor, and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address that refers to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.

Abstract: A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.

Abstract: A system and method to manage a translation lookaside buffer (TLB) is disclosed. In a particular embodiment, a method of managing a first TLB includes in response to starting execution of a memory instruction, setting a first field associated with an entry of the first TLB to indicate use of the entry. The method also includes setting a second field to indicate that the entry in the first TLB matches a corresponding entry in a second TLB.

Abstract: Eager send data communications in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI composed of data communications endpoints that specify a client, a context, and a task, including receiving an eager send data communications instruction with transfer data disposed in a send buffer characterized by a read/write send buffer memory address in a read/write virtual address space of the origin endpoint; determining for the send buffer a read-only send buffer memory address in a read-only virtual address space, the read-only virtual address space shared by both the origin endpoint and the target endpoint, with all frames of physical memory mapped to pages of virtual memory in the read-only virtual address space; and communicating by the origin endpoint to the target endpoint an eager send message header that includes the read-only send buffer memory address.

Abstract: A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.

Abstract: Methods and apparatus for supporting diverse memory access schemes are disclosed. In one embodiment, a mobile computing device includes program code that accesses memory according to a first bad block management scheme and program code that accesses memory according to a second bad block management scheme, which is different than the first bad block memory scheme. In addition, a memory component includes data that is partitioned according to both the first bad block management scheme and the second bad block management scheme so as to enable both the code that accesses memory according to a first bad block management scheme and the code that accesses memory according to a second bad block management scheme to utilize the memory component.

Abstract: A method of assigning virtual memory to physical memory in a data processing system allocates a set of contiguous physical memory pages for a new page mapping, instructs the memory controller to move the virtual memory pages according to the new page mapping, and then allows access to the virtual memory pages using the new page mapping while the memory controller is still copying the virtual memory pages to the set of physical memory pages. The memory controller can use a mapping table which temporarily stores entries of the old and new page addresses, and releases the entries as copying for each entry is completed. The translation lookaside buffer (TLB) entries in the processor cores are updated for the new page addresses prior to completion of copying of the memory pages by the memory controller. The invention can be extended to non-uniform memory array (NUMA) systems.

Abstract: What is disclosed is a set key and clear frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which identifies a first and second general register. Obtained from the first general register is a frame size field indicating whether a storage frame is one of a small block or a large block of data. Obtained from the second general register is an operand address of a storage frame upon which the instruction is to be performed. If the storage frame is a small block, the instruction is performed only on the small block. If the indicated storage frame is a large block of data, an operand address of an initial first block of data within the large block of data is obtained from the second general register. The frame management instruction is performed on all blocks starting from the initial first block.

Abstract: A memory card system and related write method are disclosed. The method includes receiving a write request for a predetermined page; performing a write operation on a first log block that corresponds to a first data block including the page; receiving an update request for the page; and performing a write operation on a second log block that corresponds to the first data block. The memory card system includes: at least one non-volatile memory including a data block and a log block for updating the data block; and a memory controller controlling an operation of the non-volatile memory. During a write operation for a predetermined page, the controller controls writing of a first log block corresponding to a first data block including the predetermined page, and controls writing of a second log block during an update operation of the predetermined page.

Abstract: Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the physical address of the first lookup table in non-volatile memory. In some implementations, a cache in volatile memory holds the physical addresses of the most recently written logical sectors. Also disclosed is a block TOC describing block content which can be used for garbage collection and restore operations.

Abstract: A virtually indexed and physically tagged memory is described having a cache way size which can exceed the minimum page table size such that aliased virtual addresses VA within the cache way 12 can be mapped to the same physical address PA. Aliasing management logic 10 permits multiple copies of the data from the same physical address to be stored at different virtual indexes within the cache within given or different cache ways.

Abstract: Disclosed is a computer implemented method, computer program product, and apparatus for maintaining a preselect list. The method comprises software components detecting a page fault of a memory page. In response to detecting a page fault, the software components determine whether the memory page is referenced in the preselect list and unhide the memory page. Upon determining whether the memory page is referenced in the preselect list, the software components remove an entry of the preselect list corresponding to the memory page to form at least one removed candidate page and skip paging-out of the at least one removed candidate page.

Abstract: A system and method for maintaining a mapping table in a data storage subsystem. A data storage subsystem supports multiple mapping tables including a plurality of entries. Each of the entries comprise a tuple including a key. A data storage controller is configured to encode each tuple in the mapping table using a variable length encoding. Additionally, the mapping table may be organized as a plurality of time ordered levels, with each level including one or more mapping table entries. Further, a particular encoding of a plurality of encodings for a given tuple may be selected based at least in part on a size of the given tuple as unencoded, a size of the given tuple as encoded, and a time to encode the given tuple.

Abstract: A system and method for invalidating obsolete virtual/real address to physical address translations may employ translation lookaside buffers to cache translations. TLB entries may be invalidated in response to changes in the virtual memory space, and thus may need to be demapped. A non-cacheable unit (NCU) residing on a processor may be configured to receive and manage a global TLB demap request from a thread executing on a core residing on the processor. The NCU may send the request to local cores and/or to NCUs of external processors in a multiprocessor system using a hardware instruction to broadcast to all cores and/or processors or to multicast to designated cores and/or processors. The NCU may track completion of the demap operation across the cores and/or processors using one or more counters, and may send an acknowledgement to the initiator of the demap request when the global demap request has been satisfied.

Abstract: For a virtual memory of a virtualized computer system in which a virtual page is mapped to a guest physical page which is backed by a machine page and in which a shadow page table entry directly maps the virtual page to the machine page, reverse mappings of guest physical pages are optimized by removing the reverse mappings of certain immutable guest physical pages. An immutable guest physical memory page is identified, and existing reverse mappings corresponding to the immutable guest physical page are removed. New reverse mappings corresponding to the identified immutable guest physical page are no longer added.