Abstract: Systems and methods for tracking changes and performing backups to a storage device are provided. For virtual disks of a virtual machine, changes are tracked from outside the virtual machine in the kernel of a virtualization layer. The changes can be tracked in a lightweight fashion with a bitmap, with a finer granularity stored and tracked at intermittent intervals in persistent storage. Multiple backup applications can be allowed to accurately and efficiently backup a storage device. Each backup application can determine which block of the storage device has been updated since the last backup of a respective application. This change log is efficiently stored as a counter value for each block, where the counter is incremented when a backup is performed. The change log can be maintained with little impact on I/O by using a coarse bitmap to update the finer grained change log.

Abstract: In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.

Abstract: An apparatus for reducing a page fault rate in a virtual memory system includes a page table stored in a main storage unit which stores a reference address so as to read page information from the main storage unit; a buffer unit which stores a portion of the page table; and a processor which reads data from the main storage unit or which stores data in the main storage unit. When changing information for referring to a first page that exists in the page table, the processor performs a task invalidating information related to the first page in the buffer unit. A method of reducing the page fault rate includes resetting reference information stored in the page table; detecting whether the reference information exists in a buffer unit; and invalidating the reference information when the reference information exists in the buffer unit.

Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.

Abstract: A storage system and method is provided including physical storage devices controlled by storage control devices constituting a storage control layer operatively coupled to the physical storage devices and hosts. The storage control layer includes a first virtual layer interfacing with the hosts, operable to represent a logical address space available to said hosts and characterized by an Internal Virtual Address Space (IVAS); a second virtual layer characterized by a Physical Virtual Address Space (PVAS), interfacing with the physical storage devices, and operable to represent an available storage space; and an allocation module operatively coupled to the first and second virtual layers and providing mapping between IVAP and PVAS. Each address in PVAS is configured to have a corresponding address in IVAS. The allocation module facilitates management of IVAS and PVAS, enabling separation of a process of deleting certain logical object into processes performing changes in IVAS and PVAS, respectively.

Abstract: A shared resource management system and method are described. In one embodiment, a shared resource management system facilitates age based miss replay. In one exemplary implementation, a shared resource management system includes a plurality of engines, and a shared resource a shared resource management unit. The plurality of engines perform processing. The shared resource supports the processing. The shared resource management unit handles multiple outstanding miss requests.

Abstract: In one embodiment, a virtual tape storage (VTS) system includes random access storage; sequential access storage; support for at least one virtual volume; a storage manager having logic for determining a physical block ID (PBID) that corresponds to a starting logical block ID (SLBID); and logic for copying a portion of a logical volume from the sequential access storage to the random access storage without copying the entire logical volume. Other embodiments are disclosed also.

Abstract: A command receiver receives, from an external access requesting entity, a command with which to access data, together with an address to be accessed and IOID to identify the access requesting entity. Based on the IOID, the access decision unit determines whether or not an access is one that is to be permitted for an access requesting entity to access a region of access destination. The access decision unit determines whether access of the access requesting entity is permitted or not, for each page that serves as the basic management unit of logical address in the processor space.

Abstract: A memory access control unit is provided with a storage unit for storing a page table that stores a correspondence between a piece of data, a virtual page number, and a physical page number for all pages, and a conversion unit that includes a buffer for storing, for each of a subset of the pages, the virtual page number and the physical page number in correspondence, and a conversion processing unit operable to convert a virtual address into a physical address in accordance with content stored in the buffer.

Abstract: A virtualization platform provides fault tolerance for a primary virtual machine by continuously transmitting checkpoint information of the primary virtual machine to a collector process, such as a backup virtual machine. When implemented on a hardware platform comprising a multi-processor that supports nested page tables, the virtualization platform leverages the nested page table support to quickly identify memory pages that have been modified between checkpoints. The backup virtual machine provides feedback information to assist the virtualization platform in identifying candidate memory pages for transmitting actual modifications to the memory pages rather than the entire memory page as part of the checkpoint information. The virtualization platform further maintains a modification history data structure to identify memory pages that can be transmitted simultaneous with the execution of the primary virtual machine rather than while the primary virtual machine has been stunned.

Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

Abstract: Methods and systems for load balancing read/write requests of a virtualized storage system. In one embodiment, a storage system includes a plurality of physical storage devices and a storage module operable within a communication network to present the plurality of physical storage devices as a virtual storage device to a plurality of network computing elements that are coupled to the communication network. The virtual storage device comprises a plurality of virtual storage volumes, wherein each virtual storage volume is communicatively coupled to the physical storage devices via the storage module. The storage module comprises maps that are used to route read/write requests from the network computing elements to the virtual storage volumes. Each map links read/write requests from at least one network computing element to a respective virtual storage volume within the virtual storage device.

Abstract: A computer system has a translation lookaside buffer (TLB) having a plurality of entries for mapping virtual memory addresses to physical memory addresses and logic configured to perform the following steps for an entry of the TLB: (a) selecting a TLB entry size for the entry; (b) determining whether a mapping for the entry is aligned with a boundary of a contiguous section of memory without overshooting an end of the contiguous section of memory, wherein the mapping is based on the TLB entry size and maps virtual memory addresses to physical memory addresses for a section of the memory consistent with the TLB entry size; (c) if the mapping is determined to be aligned with the boundary of the contiguous section of memory without overshooting the end of the contiguous section of memory, configuring the entry with the mapping written into the entry; and (d) repeating steps (a) through (c) until a mapping is found to be aligned with the boundary of the contiguous section of memory without overshooting the end of

Abstract: Multiple storage area groups into which multiple storage areas provided by multiple storage devices are classified with reference to storage area attributes are managed. The multiple logical volumes to which, in accordance with a write request to at least one address included in multiple addresses in the logical volume, at least one storage area included in the multiple storage areas is allocated are provided. In accordance with the access condition of the at least one address in the logical volume, the data written to the at least one address by the write request is migrated from the at least one storage area included in one of the multiple storage area groups to at least one storage area in another storage area group included in the multiple storage area groups.

Abstract: Administering registered virtual addresses in a hybrid computing environment that includes a host computer and an accelerator, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where administering registered virtual addresses includes maintaining, by an operating system, a watch list of ranges of currently registered virtual addresses; upon a change in physical to virtual address mappings of a particular range of virtual addresses falling within the ranges included in the watch list, notifying the system level message passing module by the operating system of the change; and updating, by the system level message passing module, a cache of ranges of currently registered virtual addresses to reflect the change in physical to virtual address mappings.

Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.

Abstract: A management information generating method wherein logical and physical block addresses (BAs) of continuous addresses are associated with each other in the BA translation table. When a logical block is constructed, an allowable value is set for the number of defective physical blocks. A logical block having fewer defects than the set number is set usable, and a logical block having more defects than the set number is set unusable. System logical block construction is performed to preferentially select physical blocks from a plane list including a large number of usable blocks to equalize the number of usable blocks in each plane list. It is determined whether the number of free blocks is insufficient on the basis of a first management unit and whether the storage area for the indicated capacity can be reserved on the basis of the management unit different from the first unit.

Abstract: In a computer system having virtual machines, one or more unused bits of a guest virtual address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a common memory page. When one bit is allocated for aliasing, sub-pages can be virtually addressed at a granularity that is one-half of a memory page. When M bits are allocated for aliasing, sub-pages can be virtually addressed at a granularity that is 1/(2M)-th of a memory page. The granularity of page sizes can be selected according to particular use cases. In the case of COW optimization, page sizes can be set statically between 4 KB and 2 MB or configured dynamically among multiple page sizes.

Abstract: There is provided a storage subsystem having a virtual volume and a page volume which has a page physical area allocated to the virtual volume. The storage subsystem divides an address space of the virtual volume into a plurality of pages, classifies each of the pages into one of a plurality of states including at least a first state and a second state, and further divide a page which is classified into the second state into a plurality of segments to managed the page classified into the second state. The first state is a state in which a page physical area is allocated to the page from the page volume, and the write data is stored in the page physical area. The second state is a state in which the predetermined pattern data and the segment are managed, in the memory, by correlating with each other.

Abstract: The present invention is directed to systems and methods for optimizing garbage collection in data storage. The data storage may be a shingled disk drive or a non-volatile solid-state memory device. Garbage collection is optimized by selectively saving data read from certain locations of the data storage in response to host read commands and using the saved data for subsequent garbage collection operations. The decision of whether to save data may be based on a number of criteria, including whether the data is located in an area of the data storage that is due to be garbage collected in the near future. In this manner, certain garbage collection operations can be performed without having to re-read the saved data.

Abstract: A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events.

Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

Abstract: A controller includes a storage for a translation table showing logical and physical addresses in a flash memory in correspondence with one another; another storage storing FAT information indicating the state of data stored in each of pages contained in each of blocks and FAT information identifiers each identifying a block to which pages each storing therein the data in the state indicated by the FAT information belong, while keeping them in correspondence with one another; yet another storage for a block management table showing block identifiers, use-state judging information indicating whether the corresponding block is used/unused, and the FAT information identifiers corresponding to all the blocks indicated as being used by the use-state judging information, while keeping them in correspondence with one another; and a controller controlling unit managing data stored in the flash memory by using the translation table, the FAT information, and the block management table.

Abstract: A page table entry dirty bit system may be utilized to record dirty information for a software distributed shared memory system. In some embodiments, this may improve performance without substantially increasing overhead because the dirty bit recording system is already available in certain processors. By providing extra bits, coherence can be obtained with respect to all the other uses of the existing page table entry dirty bits.

Abstract: A method for translation map simplification may include determining a translation map based on a predetermined criterion in response to receiving input data. The method may also include determining if the translation map extends another map or a referenced map and determining if the translation map includes at least one map fragment. The referenced map is loaded in response to a determination that the translation map includes an extension of the referenced map. The map fragment is loaded in response to a determination that the translation map comprises the map fragment. A new map is compiled based on at least the translation map, the referenced map and the at least one map fragment, in response to the translation map not including a new map reference or a modification to the translation map. The input data is processed based on the new map to produce translated data specific to the new map.

Abstract: Method for accessing data in a storage system architecture, the architecture comprises at least one disk array subsystem, comprising the following steps. Provide a SAS for managing a first and a second media extent (ME) the at least one subsystem. Obtain a location index corresponding to a host LBA via a BAT. Obtain a location information of a physical section located in the first ME corresponding to the location index via a physical section to virtual section cross-referencing functionality. Update the cross-reference in the cross-referencing functionality so that the location information obtained from the cross-referencing functionality corresponding to the location index is the location information of the second physical section. A host IO request addressing the host LBA accesses data in the second physical section utilizing the location information of the second physical section.

Abstract: A method for making memory more reliable involves accessing data stored in a removable storage device by translating a logical memory address provided by a host digital device to a physical memory address in the device. A logical memory address is received from the host digital device. The logical memory address corresponds to a location of data stored on the removable storage device. A physical memory address corresponding to the local address is determined by accessing a lookup table corresponding to the logical zone.

Abstract: The prioritization of large memory page mapping is a function of the access bits in the L1 page table. In a first phase of operation, the number of set access bits in each of the L1 page tables is counted periodically and a current count value is calculated therefrom. During the first phase, no pages are mapped large even if identified as such. After the first phase, the current count value is used to prioritize among potential large memory pages to determine which pages to map large. The system continues to calculate the current count value even after the first phase ends. When using hardware assist, the access bits in the nested page tables are used and when using software MMU, the access bits in the shadow page tables are used for large page prioritization.

Abstract: Provided are a method, system, and program for utilizing a virtualized data structure table such as an address translation and protection table (TPT), for example, in an I/O device. The virtualized data structure table has virtually contiguous data structures but not necessarily physically contiguous data structures in system memory. The data structure table may be accessed in a virtually contiguous manner. In the illustrated embodiment, the table is subdivided at a first hierarchal level into a plurality of virtually contiguous units or segments. Each unit or segment is in turn subdivided at a second hierarchal level into a plurality of virtually contiguous subunits, subsegments, pages or blocks. Each page or block is in turn subdivided at a third hierarchal level into a plurality of physically contiguous table entries.

Abstract: A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict. A changeable mapping table that maps the virtualized memory addresses to physical memory addresses is stored in the same memory system.

Abstract: A semiconductor device according to the present invention includes a first address generation unit that includes a first register group and generates a table address by a cyclically repeating first pattern using a value stored to the first register group, a second address generation unit that includes a second register group and generates an access address by a cyclically repeating second pattern using a value stored to the second register group and parameter information determined by the table address, and a control unit that outputs setting information to be supplied to the first register group and the second register group. Further, the semiconductor device performs at least one of a read process and a write process of data from and to a data memory using the access address.

Abstract: Various embodiments disclosed herein including systems and methods for improving allocation of computing resources in a virtual machine (VM) environment. Embodiments maintain data relating to how VM image data is stored in storage devices and loaded into volatile memory such as random access memory (RAM). The data is then used to identify common content in the volatile memory that can be shared across VM instances. In some embodiments, multiple VM instances can share at least a portion of a single common VM image loaded into a shared volatile memory.

Abstract: A method for writing and reading data in memory cells, comprises the steps of: defining a virtual memory, defining write commands and read commands of data (DT) in the virtual memory, providing a first nonvolatile physical memory zone (A1), providing a second nonvolatile physical memory zone (A2), and, in response to a write command of an initial data, searching for a first erased location in the first memory zone, writing the initial data (DT1a) in the first location (PB1(DPP0)), and writing, in the metadata (DSC0) an information (DS(PB1)) allowing the first location to be found and an information (LPA, DS(PB1)) forming a link between the first location and the location of the data in the virtual memory.

Abstract: Embodiments of techniques and systems for increasing efficiencies in computing systems using virtual memory are described. In embodiments, instructions which are located in two memory pages in a virtual memory system, such that one of the pages does not permit execution of the instructions located therein, are identified and then executed under temporary permissions that permit execution of the identified instructions. In various embodiments, the temporary permissions may come from modified virtual memory page tables, temporary virtual memory page tables which allow for execution, and/or emulators which have root access. In embodiments, per-core virtual memory page tables may be provided to allow two cores of a computer processor to operate in accordance with different memory access permissions. in embodiments, a physical page permission table may be utilized to provide for maintenance and tracking of per-physical-page memory access permissions. Other embodiments may be described and claimed.

Abstract: An illustrative embodiment of a computer-implemented process for managing a staging area creates the staging area for identified candidate cold objects, moves the identified candidate objects into the staging area, tracks application access to memory comprising the staging area and determines whether frequency of use information for a specific object exceeds a predetermined threshold. Responsive to a determination that the frequency of use information for the specific object exceeds a predetermined threshold, move the specific object into a regular area and determine whether a current time exceeds a predetermined threshold. Responsive to a determination that the current time exceeds a predetermined threshold, the computer-implemented process moves remaining objects from the staging area to a cold area.

Abstract: Embodiments of techniques and systems for using substitute virtualized-memory page tables are described. In embodiments, a virtual machine monitor (VMM) may determine that a virtualized memory access to be performed by an instruction executing on a guest software virtual machine is not allowed in accordance with a current virtualized-memory page table (VMPT). The VMM may select a substitute VMPT that permits the virtualized memory access, In scenarios where a data access length for the instruction is known, the substitute VMPT may include full execute, read, and write permissions for the entire guest software address space. In scenarios where a data access length for the instruction is not known, the substitute VMPT may include less than full execute, read, and write permissions for the entire guest software address space, and may be modified to allow the requested virtualized memory access. Other embodiments may be described and claimed.

Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Abstract: The present disclosure includes methods for transaction log recovery in memory. One such method includes examining a number of entries saved in a transaction log to determine a write pattern, reading the memory based on the write pattern, updating the transaction log with information associated with data read from the memory based on the write pattern, and updating a logical address (LA) table using the transaction log.

Abstract: A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.

Abstract: In response to detecting a PCI host bridge (PHB), a first address translation table may be allocated in a first portion of a memory. The first address translation table may be associated with the PHB. If an input/output adapter accessible to the PHB is configured as a virtualized adapter, a first table manager may be assigned to manage the first address translation table. The first address translation table may be configured for an initial number of virtual functions. If a requested number of virtual functions is greater than the initial number of virtual functions, additional virtual functions may be configured. A second address translation table may be allocated in a second portion of the memory. The second portion of the memory may be non-contiguous with reference to the first portion of the memory. Entries may be created in the second address translation table for the additional virtual functions.

Abstract: The present disclosure relates to a method for executing, by a processor, a program read in a program memory, comprising steps of: detecting a program memory read address jump; providing prior to a jump address instruction for jumping a program memory read address, an instruction for storing the presence of the jump address instruction; and activating an error signal if an address jump has been detected and if the presence of a jump address instruction has not been stored. The present disclosure also relates to securing integrated circuits.

Abstract: A controller, techniques, systems, and devices for optimizing throughput of read operations in flash memory are disclosed. Various optimizations of throughput for read operations can be performed using a controller. In some implementations, read operations for a multi-die flash memory device or system can be optimized to perform a read request with a highest priority (e.g., an earliest received read request) as soon as the read request is ready. In some implementations, the controller can enable optimized reading from multiple flash memory dies by monitoring a read/busy state for each die and switching between dies when a higher priority read operation is ready to begin.

Abstract: Methods for providing shadow page tables that virtualize processor memory protection. In one embodiment, virtualization software maintains the following: (a) a mapping ? from guest domain identifier to a set of shadow L2 page tables that back guest L1 sections marked with a domain identifier; and (b) with each such shadow L2 page table, a set ? of back-pointers to “potentially referencing” shadow L1 descriptors.

Abstract: What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field.

Abstract: A system memory is partitioned into a first paged partition for a first operating system and a second paged partition for a second operating system. The first paged partition is mapped into a first virtual memory partition, and the second paged partition is mapped into a second virtual memory partition. A subset of pages within the second virtual memory partition is marked as reclaimable by the first operating system to produce a set of marked pages. Responsive to a request by the first operating system for further memory, at least one reclaimable page selected from the set of marked pages is swapped out to a storage file, and the first operating system writes to the at least one reclaimable page.

Abstract: A non-volatile semiconductor memory comprising (1) a non-volatile memory array including a plurality of blocks with at least some of the plurality of blocks comprising a plurality of memory segments and with at least some of the plurality of memory segments each assigned a physical address and (2) a volatile memory. Upon a power-up of the non-volatile semiconductor memory, a translation table is generated in the volatile memory for mapping logical addresses to physical addresses in the non-volatile memory array. The generating includes reading at least one entry comprising a logical address from an inverse map stored in the non-volatile memory array. The logical address corresponds to a physical address of one of the memory segments. In response to determining that the memory segment corresponding to the logical address is valid, the translation table is updated using the logical address.

Abstract: Embodiments of the invention provide techniques for managing cache metadata providing a mapping between addresses on a storage medium (e.g., disk storage) and corresponding addresses on a cache device at which data items are stored. In some embodiments, cache metadata may be stored in a hierarchical data structure comprising a plurality of hierarchy levels. When a reboot of the computer is initiated, only a subset of the plurality of hierarchy levels may be loaded to memory, thereby expediting the process of restoring the cache metadata and thus startup operations. Startup may be further expedited by using cache metadata to perform operations associated with reboot.

Abstract: An approach for automatic storage planning and provisioning within a clustered computing environment is provided. Planning input for a set of storage area network volume controllers (SVCs) will be received within the clustered computing environment, the planning input indicating a potential load on the SVCs and its associated components. Analytical models (e.g., from vendors) can be also used that allow for a load to be accurately estimated on the storage components. Configuration data for a set of storage components (i.e., the set of SVCs, a set of managed disk (Mdisk) groups associated with the set of SVCs, and a set of backend storage systems) will also be collected. Based on this configuration data, the set of storage components will be filtered to identify candidate storage components capable of addressing the potential load. Then, performance data for the candidate storage components will be analyzed to identify an SVC and an Mdisk group to address the potential load.

Abstract: Systems and methods for performing non-allocating memory access instructions with physical address. A system includes a processor, one or more levels of caches, a memory, a translation look-aside buffer (TLB), and a memory access instruction specifying a memory access by the processor and an associated physical address. Execution logic is configured to bypass the TLB for the memory access instruction and perform the memory access with the physical address, while avoiding allocation of one or more intermediate levels of caches where a miss may be encountered.

Abstract: A method for updating, in the background, data stored in physical memories without affecting the current operations performed by the microprocessor. When the update is completely terminated, the application switches from an old version to a new version. This switching occurs by a reconfiguration of the page table during which a first sub-tree structure of pointers accessing the old version of data stored in memories is replaced by a second sub-tree structure of pointers thus allowing access to the new version of data. This update method prevents incoherent transitory states of the system as the latter works with the previous data version until the installation of the new version becomes usable. In the case of an interruption to the update process, the application can always reinitialize the update since the old version of data can be reactivated by returning to the previous configuration of the page table.