Abstract: According to one embodiment, upon request from an information processor, a semiconductor storage controller writes pieces of data in predetermined units into storage locations in which no data has been written in erased areas within a semiconductor chip's storage area. A third table and a second table which is a subset thereof include physical addresses each indicating a storage location of each of pieces of the data within the semiconductor chip. The first table includes either information specifying a second table entry or information specifying a third table entry. The semiconductor storage controller records the first and the second tables into a volatile memory or records the first table into a volatile memory and the third table into a nonvolatile memory.

Abstract: Virtual tape libraries (VTLs) and methods for concurrently accessing a VTL are provided. One VTL includes memory partitioned into multiple volumes, multiple virtual drives, and a processor. The processor is configured to enable multiple applications to concurrently access a virtual storage volume in a first or second access mode. One method includes receiving a first request for a first application to access a virtual storage volume to write data to or read data from the virtual storage volume and granting the first request. The method further includes receiving a second request for a second application to concurrently access the virtual storage volume to write data to or read data from the virtual storage volume, determining if the first and second requests are compatible, and accepting or denying the second request based on the determination. Also provided are physical computer storage mediums including computer code for performing the above method.

Abstract: A data object is stored in a hosted storage system and includes an access control list specifying access permissions for data object stored in the hosted storage system. The hosted storage system provides hosted storage to a plurality of clients that are coupled to the hosted storage system. A request to store a second data object is received. The request includes an indicator that the first data object stored in the hosted storage system should be used as an access control list for the second data object. The second data object is stored in the hosted storage system. The first data object is assigned as an access control list for the second data object stored in the hosted storage system.

Abstract: A method and system to facilitate paging of one or more segments of a logical-to-physical (LTP) address mapping structure, such as a table, to a non-volatile memory, such as a NAND flash memory. The LTP address mapping structure is part of an indirection system map associated with the non-volatile memory. By allowing one or more segments of the LTP address mapping structure to be paged to the non-volatile memory, the amount of volatile memory required to store the LTP address mapping structure is reduced while maintaining the benefits of the LTP address mapping structure. One or more segments of the logical to physical address mapping structure may be cached in volatile memory, and a size of each segment may be the same as or a multiple of a page size of the NAND flash memory. A lookup or segment table may be provided to indicate a location of each segment and may be optimized for sequential physical addresses.

Abstract: Techniques for optimizing data movement in electronic storage devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for optimizing data movement in electronic storage devices comprising maintaining, on the electronic storage device, a data structure associating virtual memory addresses with physical memory addresses. Information can be provided regarding the data structure to a host which is in communication with the electronic storage device. Commands can be received from the host to modify the data structure on the electronic storage device, and the data structure can be modified in response to the received command.

Abstract: Embodiments of a data cache are disclosed that substantially decrease a number of accesses to a physically-tagged tag array of the data cache are provided. In general, the data cache includes a data array that stores data elements, a physically-tagged tag array, and a virtually-tagged tag array. In one embodiment, the virtually-tagged tag array receives a virtual address. If there is a match for the virtual address in the virtually-tagged tag array, the virtually-tagged tag array outputs, to the data array, a way stored in the virtually-tagged tag array for the virtual address. In addition, in one embodiment, the virtually-tagged tag array disables the physically-tagged tag array. Using the way output by the virtually-tagged tag array, a desired data element in the data array is addressed.

Abstract: A system and method for implementation of MMU assisted data breakpoints for any number of data structures within a program application are provided. For each data structure for which a data breakpoint is desired, two distinct MMU entries are created. One MMU entry has access attributes. The other entry has an interrupt triggering sub-entry. According to the preferred embodiment, access to the second MMU entry causes a page fault.

Abstract: A method for generating a virtual volume (VV) in a storage system architecture. The architecture comprises a host and one or more disk array subsystems. Each subsystem comprises a storage controller. One or more of the subsystems comprises a physical storage device (PSD) array. The method comprises the following steps: mapping the PSD array into a plurality of media extents (MEs), each of the MEs comprises a plurality of sections; providing a virtual pool (VP) to implement a section cross-referencing function, wherein a section index (SI) of each of the sections contained in the VP is defined by the VP to cross-reference VP sections to physical ME locations; providing a conversion method or procedure or function for mapping VP capacity into to a VV; and presenting the VV to the host. A storage subsystem and a storage system architecture performing the method are also provided.

Abstract: A translation lookaside buffer (TLB) is disclosed formed using RAM and synthesisable logic circuits. The TLB provides logic within the synthesisable logic for pairing down a number of memory locations that must be searched to find a translation to a physical address from a received virtual address. The logic provides a hashing circuit for hashing the received virtual address and uses the hashed virtual address to index the RAM to locate a line within the RAM that provides the translation.

Abstract: A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.

Abstract: A virtual-machine-based system provides a mechanism for a virtual machine monitor (VMM) to process a hypercall received from an application running in the virtual machine (VM). A hypercall interface causes the virtual memory pages, needed by the VMM to process the hypercall, to be available to the VMM. In one embodiment, when virtual memory pages needed by the VMM to process the hypercall are not available to the VMM, the application is caused to access the needed pages, in response to which the required virtual memory becomes available to the VMM.

Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.

Abstract: In an embodiment, a stacked package-on-package system has a memory die and a logic die. The memory die comprises a first memory and a second memory, each operated independently of the other, and each having an inter-chip interface electrically connected to the logic die. The logic die has two independent clock sources, one to provide a first clock signal to the first memory, and the other clock source to provide a second clock signal to the second memory.

Abstract: A volume migration method for causing to carry out a migration from a first volume manager to a second volume, includes: by causing the first volume manager to carry out actual accesses, obtaining information of correspondence, by the first volume manager, between logical volume offsets and physical blocks on a physical medium; judging, based on the obtained information of the correspondence, whether or not an exceptional data layout is carried out; and when it is judged that the exceptional data layout is not carried out, updating only a header area on the physical medium for the second volume manager. Incidentally, the aforementioned obtaining is carried out by using a program module for blocking access by the first volume manager to the physical medium. Thus, when only the header area is updated after it is confirmed the exceptional data layout is not made, the high-speed volume migration becomes possible.

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Abstract: Systems and methods are disclosed for selectively combining commands for a system having non-volatile memory (“NVM”). In some embodiments, a command dispatcher of a system can receive multiple commands to access a NVM for a period of time. After receiving the multiple commands, the command dispatcher can determine a set of commands that are naturally combinable. In some embodiments, the command dispatcher can select commands that are fairly distributed across different chip enables (“CEs”) and/or buses. After selecting the set of commands, the command dispatcher can combine the set of commands into a multi-access command. Finally, the command dispatcher can dispatch the multi-access command to the NVM.

Abstract: A method for data storage includes representing logical volumes by respective sets of pointers to physical partitions in which data used by the logical volumes is stored. One or more of the logical volumes are defined as provisionally deleted. A subset of the provisionally-deleted logical volumes is selected such that each logical volume in the subset has one or more private physical partitions whose data is used exclusively by that logical volume. One or more of the private physical partitions of the logical volumes in the subset are released for reallocation to another logical volume.

Abstract: Some of the embodiments of the present disclosure provide a method for predicting, for a first virtual address, a first descriptor based at least in part on the one or more past descriptors associated with one or more past virtual addresses; and determining, for the first virtual address, a first physical address based at least in part on the predicted first descriptor. Other embodiments are also described and claimed.

Abstract: Embodiments of a transmit-side scaler and method for processing outgoing information packets using thread-based queues are generally described herein. Other embodiments may be described and claimed. In some embodiments, a process ID stored in a token area may be compared with a process ID of an application that generated an outgoing information packet to obtain a transmit queue. The token area may be updated with a process ID stored in an active threads table when the process ID stored in the token area does not match the process ID of the application.

Abstract: A data storage device includes a flash memory including a plurality of data blocks and a flash translation layer that divides the plurality of data blocks into a data block of a first group and a data block of a second group, and that records the data signal to a data block of the first group or a data block of the second group which is extended from a data block of the first group.

Abstract: A method for assigning data in a plurality of physical storage resources for an information handling system is disclosed. The plurality of physical storage resources includes a first tier and a second tier with a lower performance and cost relative to capacity than the first tier. A tier manager hosted on the information handling system and in electronic communication with the plurality of physical storage resources is configured to: determine a seek distance value, operation rate, operation size value, and elapsed time value for each page; and calculate a relative randomness value for each page using the seek distance value, operation rate, operation size value, and elapsed time value determined for each page. A classification module may assign a physical location for each page such that the relative randomness value for each page in the first tier is greater than the relative randomness value for each page in the second tier.

Abstract: A method for address translation in a memory comprising a plurality of memory streaming units (MSUs), wherein n represents the number of MSUs and n is not a power of two, and wherein the memory further comprises a striped region, the method comprising determining an MSU from among the plurality of MSUs having a physical address (PA) in the striped region corresponding to a logical address (LA) comprising performing a modulo n operation on less than all the bits representing the LA; and transmitting the LA to the MSU.

Abstract: A method includes defining a first mapping, which translates between logical addresses and physical storage locations in a memory with a first mapping unit size, for accessing the memory by a first processing unit. A second mapping is defined, which translates between the logical addresses and the physical storage locations with a second mapping unit size that is different from the first mapping unit size, for accessing the memory by a second processing unit. Data is exchanged between the first and second processing units via the memory, while accessing the memory by the first processing unit using the first mapping and by the second processing unit using the second mapping.

Abstract: The present disclosure includes methods for transaction log recovery in memory. One such method includes examining a number of entries saved in a transaction log to determine a write pattern, reading the memory based on the write pattern, updating the transaction log with information associated with data read from the memory based on the write pattern, and updating a logical address (LA) table using the transaction log.

Abstract: A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict. To improve memory performance destructive read operations are used when reading data but the data is written back into the physical memory in a later cycle.

Abstract: For each original data segment, a distributed storage processing unit generates encoded slices designed to prevent the original data segment from being reconstructed using fewer than a threshold number of encoded slices. Multiple encoded slices are generated for each of two different data segments, and the slices associated with the first and second data segment are stored substantially concurrently in different storage sets employing different distributed storage units. Encoded slices for even and odd data segments can be stored in different storage sets, or longer sequences of data segments can be stored in alternating storage sets. Storage sets can also be determined by the vault generation of a particular data segment.

Abstract: An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the page table request requires the hypervisor to process. If the determination reveals that the page table request requires the hypervisor, then the hypervisor is used to handle the request. However, if the determination reveals that the page table request does not require the hypervisor, then an indicator included in a page table entry corresponding to the request is read to determine if the page table entry is controlled by the operating system or the hypervisor. The operating system is able to update the page table entry if the indicator identifies the page table entry as being operating system controlled.

Abstract: A data storage device including a storing medium to shingle write and a controller to access the storing medium so that data is sequentially written on the storing medium using a mapping table based on Logical Block Address (LBA) included in a write command.

Abstract: An alignment data structure is used to map a logical data block start address to a physical data block start address dynamically, to service a client data access request. A separate alignment data structure can be provided for each data object managed by the storage system. Each such alignment data structure can be stored in, or referenced by a pointer in, the inode of the corresponding data object. A consequence of the mapping is that certain physical storage medium regions are not mapped to any logical data blocks. These unmapped regions may be visible only to the file system layer and layers that reside between the file system layer and the mass storage subsystem. They can be used, if desired, to store system information, i.e., information that is not visible to any storage client.

Abstract: A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased.

Abstract: In a CPU, the CPU having multiple CPU cores, each core having a first machine specific register, a second machine specific register, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations.

Abstract: A system including memory and a resource controller. The memory includes a first memgroup and a second memgroup, wherein the first memgroup comprises a first physical page mapped to a virtual page, and wherein the second memgroup comprises a second physical page. The resource controller is configured to receive a request to stop the first memgroup, instruct a memory power management subsystem to mark the first memgroup as stopped in response to receiving the request to stop the first memgroup, wherein no free pages are allocated from the first memgroup after the first memgroup is marked as stopped, remap the virtual page to the second physical page in response to the marking the first memgroup as stopped, and reduce power to the first memgroup in response to a determination that the first physical page is not mapped to the virtual page.

Abstract: A system that includes a memory, a tilelet data structure entry, a first tile freelist, and an allocation subsystem. The memory includes a first tilelet on a first tile. The tilelet data structure entry includes a first tilelet preferred pagesize assigned to a first value. The first tile freelist for the first tile includes a first tile in-bounds page freelist, and a first tile out-of-bounds page freelist. The allocation subsystem is configured to detect that a first physical page is freed, store, in the first tile in-bounds page freelist, a first page data structure, detect that a second physical page is freed, store, in the first tile out-of-bounds page freelist, a second page data structure, and coalesce the memory using the second page and at least one of the physical pages associated with the plurality of out-of-bounds page data structures into a third physical page.

Abstract: What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field.

Abstract: In general, in one aspect, the invention relates to a system that includes memory and a prediction subsystem. The memory includes a first memgroup and a second memgroup, wherein the first memgroup comprises a first physical page and a second physical page, wherein the first physical page is a first subtype, and wherein the second physical page is a second subtype. The prediction subsystem is configured to obtain a status value indicating an amount of freed physical pages on the memory, store the status value in a sample buffer comprising a plurality of previous status values, determine, using the status value and the plurality of previous status values, a deficiency subtype state for the first subtype based on an anticipated need for the first subtype on the memory, and instruct, based on the determination, an allocation subsystem to coalesce the second physical page to the first subtype.

Abstract: A system includes first memory configured to store first metadata to associate logical addresses with physical addresses. Second memory is configured to include the physical addresses, to store first data based on the physical addresses, and to store portions of the first metadata when a status of a predetermined group of the physical addresses is changed. A recovery module is configured to update the first metadata based on the portions of the first metadata stored in the second memory.

Abstract: System for controlling data transfer between a host system and storage devices. A virtualization controller implements the data transfer and includes first ports for connection with the storage devices, a second port for connection with the host system, a processor, and a memory configured to store volume mapping information which correlates first identification information used by the host system to access a first storage area in one of the storage devices, with second identification information for identifying the first storage area, the correlation being used by the processor to access the first storage area. When data stored in the first storage area is transferred to a second storage area, the processor correlates the first identification information with a third identification information for identifying the second storage area and registers the first identification information and the third identification information in the volume mapping information.

Abstract: A computing system includes virtualization software including a guest operating system (OS). A method maintains, by the virtualization software layer, a first shadow page table for use in a kernel mode and a second shadow page table for use in a user mode. The virtualization software switches between using the first shadow page table and the second shadow page table when the guest OS switches between operating in the kernel mode and the user mode.

Abstract: A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical address, and wherein the attribute entry provided describes characteristics of the physical address.

Abstract: A system and method for merging sectors of a flash memory module, the method includes: receiving multiple sectors, each received sector is associated with a current erase block out of multiple (L) erase blocks; accumulating the received sectors in a sector buffer, the sector buffer is stored in a non-volatile memory module; maintaining a merged sector map indicative of a sectors of the sector buffer that have been merged and sectors of the sector buffer waiting to be merged; finding a first sector waiting to be merged according to the merged sector map; merging the first sector and other sectors that belong to a same erase block as the first sector; and updating the merged sector map to indicate that that the first second and the other sectors that belonged to the same erase block were merged.

Abstract: A solid-state storage device with multi-level addressing is provided. The solid-state storage device includes a plurality of flash memory devices, a volatile memory, and a controller. The controller is configured to store data received from a host in the plurality of flash memory devices in response to a write command and to read the data stored in the plurality of flash memory devices in response to a read command. The controller is further configured to maintain a multi-level address table that maps logical addresses received from the host identifying the data stored in the plurality of flash memory devices to physical addresses in the plurality of flash memory devices containing the data. A first level of the multi-level address table is maintained by the controller in the volatile memory and second and third levels of the multi-level address table are maintained by the controller in the plurality of flash memory devices.

Abstract: Memory address translation circuitry 14 performs a top down page table walk operation to translate a virtual memory address VA to a physical memory address PA using translation data stored in a hierarchy of translation tables 28, 32, 36, 38, 40, 42. A page size variable S is used to control the memory address translation circuitry 14 to operate with different sizes S of pages of physical memory addresses, pages of virtual memory address and translation tables. These different sizes may be all 4 kBs or all 64 kBs. The system may support multiple virtual machine execution environments. These virtual machine execution environments can independently set their own page size variable as can the page size of an associated hypervisor 62.

Abstract: Embodiments of an invention for using a memory address translation structure to manage protected micro-contexts are disclosed. In one embodiment, an apparatus includes an interface and memory management logic. The interface is to perform a transaction to fetch information from a memory. The memory management logic is to translate an untranslated address to a memory address. The memory management logic includes a storage location, a series of translation stages, and determination logic. The storage location is to store an address of a data structure for the first translation stage. Each of the translation stages includes translation logic to find an entry in a data structure based on a portion of the untranslated address. Each entry is to store an address of a different data structure for the first translation stage, an address of a data structure for a successive translation stage, or the physical address.

Abstract: In one embodiment, a system includes memory ports distributed into subsets identified by a subset index, where each memory port has an individual wait time based on a respective workload. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address referring to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.

Abstract: A hybrid drive is disclosed comprising a head actuated over a disk comprising a plurality of data sectors, and a non-volatile semiconductor memory (NVSM). A read frequency of a first logical block address (LBA) is maintained, and when the read frequency of the first LBA exceeds a threshold and a corresponding PBA is assigned to a data sector of the disk, first data stored in the data sector is copied to a memory segment of the NVSM. When the read frequency of the first LBA exceeds a threshold and the PBA is assigned to a memory segment of the NVSM, first data stored in the memory segment is copied to a data sector of the disk. When a read command is received to read the first LBA, a decision is made to read the first data from one of the NVSM and the disk.

Abstract: According to one embodiment, a semiconductor memory controlling device includes a write control unit that writes a predetermined number of pieces of first data and redundant information calculated by using the predetermined number of pieces of the first data and used for correcting an error in the first data into different semiconductor storage drives, respectively; a constructing unit that constructs a storage area for storing therein a table by using driver information, the table showing an association between a logical address and a physical address of the first data and identification information for associating the predetermined number of pieces of first data with the redundant information; and a table controlling unit that stores, into the storage area, the table associated with the identification information, the physical address and the logical address of the predetermined number of pieces of the first data, and a physical address of the redundant information.

Abstract: A storage system and method are provided including physical storage devices controlled by storage control devices constituting a storage control layer operatively coupled to the physical storage devices and hosts. The storage control layer includes: a first virtual layer interfacing with the hosts, operable to represent a logical address space characterized by logical block addresses, characterized by an Internal Virtual Address Space (IVAS) and operable, responsive to I/O requests addressed to logical block addresses, to provide protocol-dependent translation of said logical block addresses into IVAS addresses; and a second virtual layer interfacing with the physical storage space, and operable to represent available physical space to said hosts and characterized by a Physical Virtual Address Space (PVAS). Each address in PVAS having a corresponding address in IVAS.

Abstract: A storage controller manages address conversion information denoting the correspondence relationship between a logical address and a physical address of storage area (for example, a physical block) inside a flash memory. The storage controller uses the above-mentioned address conversion information to specify a physical address corresponding to a logical address specified by an I/O request from a higher-level device, and sends an I/O command including I/O-destination information based on the specified physical address to a memory controller inside a flash memory module. The memory controller carries out the I/O with respect to a storage area inside a flash memory specified from the I/O-destination information of the I/O command from the storage controller.

Abstract: Embodiments of the present invention provide a method of a first processor using a memory resource associated with a second processor. The method includes receiving a memory instruction from a first processor process, wherein the memory instruction refers to a shared memory address (SMA) that maps to a second processor memory. The method also includes mapping the SMA to the second processor memory, wherein the mapping produces a mapping result and providing the mapping result to the first processor.

Abstract: A method of impeding leakage of cache access behavioral information of a section of a sensitive process to an untrusted process, said sensitive and untrusted processes being performed by a processor within a data processing apparatus, said data processing apparatus further comprising at least one cache operable to store information required by said processor while performing said sensitive and untrusted processes, the method comprising the steps of prior to commencing processing of a section of said sensitive process by said processor, evicting information stored in locations of said at least one cache which may otherwise be evicted by said sensitive process loading information that may be required by said section of said sensitive process in said at least one cache; commencing processing of said section of said sensitive process by said processor; switching said processor during processing of said section of said sensitive process to said untrusted process in response to a switching request; on switching bac