Abstract: A processor includes a memory unit in which instructions having their constituent bytes stored in ascending address order alternate with instructions having their constituent bytes stored in descending address order. A single address pointer is used to read one instruction by reading up, and another instruction by reading down. The amount of address information needed for program execution is thereby reduced, as one address pointer suffices for two instructions. The address pointer may be provided by a branch instruction that also indicates whether to read up or down. An up-counter and a down-counter may be provided as address counters, enabling the two instructions to be read and executed concurrently. Four address counters may be provided, enabling a branch instruction to designate the execution of from one to four consecutive instructions.

Abstract: A pattern generator for semiconductor test system for testing a semiconductor memory device by generating and applying test patterns. The pattern generator is capable of freely generating inversion request signals for inverting the read/write data for specified memory cells for a memory device under test having different total numbers of memory cells between X (row) and Y (column) directions. The locations of specified memory cells are on a diagonal line on an array of memory cells in the memory device under test or on a reverse diagonal line which is perpendicular to the diagonal line.

Abstract: A computer system includes a read ahead engine that receives a sequence of read requests and performs read ahead operations in accordance with various patterns detected within the sequence of read requests. The prefetch engine may implement the method of storing a first run value indicative of the run size of a first plurality of sequential read requests, and storing a first skip value indicative of a non-sequential skip associated with a subsequent read request. The method may further include determining whether a second run value indicative of the sequential run size of a second plurality of read requests equals the first run value, and whether a second skip value indicative of another non-sequential skip associated with an additional read request equals the first skip value. If the first run value equals the second run value, and the first skip value equals the second skip value, a stride pattern is indicated, and one or more read ahead operations according to the detected stride pattern may be initiated.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: An architecture and method for dynamically allocating and deallocating memory for variable length packets with a variable number of virtual lanes in an Infiniband subnetwork. This architecture uses linked lists and tags to handle the variable number of Virtual Lanes and the variable packet sizes. The memory allocation scheme is independent of Virtual Lane allocation and the maximum Virtual Lane depth. The disclosed architecture is also able to process Infiniband packet data comprising variable packet lengths, a fixed memory allocation size, and deallocation of memory when packets are either multicast or unicast. The memory allocation scheme uses linked lists to perform memory allocation and deallocation, while tags are used to track Infiniband subnetwork and switch-specific issues. Memory allocation and deallocation is performed using several data and pointer tables. These tables store packet data information, packet buffer address information, and pointer data and point addresses.

Abstract: A method for generating a modulo Gray-code representation of a non-power-of-two set of binary values begins by determining a desired Gray-code sequence length. The method then continues by determining a bus width, M, in bits, based on the desired Gray-code sequence length, to represent the generated Gray-code. The method then continues by determining a set of skipped binary values based on the desired Gray-code sequence length and the bus width to obtain the non-power-of-two set of binary values. The method then continues by representing the non-power-of-two set of binary values as a set of equivalent Gray-code values.

Abstract: The present system and method allows for a memory location, typically a system event register, present in a processor to be accessed as either big or little endian mode, depending on an operating system (OS) accessible bit for endian selection. The OS type is determined at boot time.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A technique enables a server, such as a filer, configured with a plurality of virtual servers, such as virtual filers (vfilers), to participate in a plurality of private network address spaces having potentially overlapping network addresses. The technique also enables selection of an appropriate vfiler to service requests within a private address space in a manner that is secure and distinct from other private address spaces supported by the filer. An IPspace refers to each distinct address space in which the filer and its storage operating system participate. An IPspace identifier is applied to translation procedures that enable the selection of a correct vfiler for processing an incoming request and an appropriate routing table for processing an outgoing request.

Abstract: Disclosed is a device and method such that data of size S is stored in a memory of size K, a two-dimensional matrix with R rows and C columns, and interleaving indexes I are generated according to a predetermined interleaving rule to randomly output the data from the memory. If a first index I is greater than data size S, a second index is generated and output prior to outputting invalid data stored in the memory at the location of the first index.

Abstract: Methods and apparatus are disclosed for matching a string with multiple lookups using a single associative memory, such as, but not limited to binary and ternary content-addressable memories (CAMs). In one implementation, an information string is partitioned into multiple segments. A first lookup operation is performed on the associative memory using the first segment to produce a first associative memory result, which is used as input to a memory lookup operation to produce a first result. The first result can be programmed to have any desired value or length. This first result along with a second segment of the information string is then used as input to the same associative memory to produce a second associative memory result, which is typically used as input to a memory lookup operation to produce a second result. This process can be repeated for an arbitrary or predetermined number of times.

Abstract: A system and method for rapidly generating a series of non-repeating, deterministic, pseudo-random addresses is disclosed. A deterministic, pseudo-random number generator is implemented in hardware. Once a number in a pseudo-random sequence is generated, a pattern eliminator alters the number to remove any pattern existing in the low order bits. The number may then be combined with an offset and a base to form a memory address for testing a memory device. The generated memory address is output directly to the memory device being tested.

Abstract: A content addressable memory (CAM) is provided that can perform wide word searches. At least one CAM memory core having a plurality of bit pattern entry rows is included in the CAM. In addition, search logic is included that, is capable searching particular rows during each cycle. The search logic is also capable of allowing match line results of unsearched rows to remain unchanged during a cycle. The CAM further includes a serial AND array in communication with the bit pattern entry rows, wherein the serial AND array is capable of computing a match result for wide word entries that span multiple bit pattern entry rows. In one aspect, a match line enable signal is provided to the serial AND array, which facilitates computation of the match result.

Abstract: Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits of the latched address bits and their compliments are applied to respective first multiplexers along with respective bits from a burst counter. The first multiplexers apply the latched address bits and their compliments to respective second multiplexers during a first bit of a burst access, and bits from a burst counter during the remaining bits of the burst. The second multiplexers are operable responsive to a control signal to couple either the latched address bits or their compliments to respective outputs for use as an internal address. The control signal is generated by an adder logic circuit that receives the two low-order bits of the column address.

Abstract: An integrated circuit memory includes a FLASH memory including a circuit for recording a word presented on its input without the possibility of recording simultaneously several words in parallel. The integrated circuit memory may include a buffer memory with a sufficient capacity to store a plurality of words, the output of which is coupled to the input of the FLASH memory. A circuit is also included for recording into the buffer memory a series of words to be recorded into the FLASH memory and recording into the FLASH memory the words first recorded into the buffer memory.

Abstract: An internal nonvolatile memory contains a program to be executed during a rewrite operation mode. During the rewrite operation mode a CPU core writes received rewrite data to an external nonvolatile memory according to a program in the internal nonvolatile memory. A first selector circuit transmits a first chip select signal to the external nonvolatile memory when a mode signal indicates a normal operation mode, and transmits the first chip select signal to the internal nonvolatile memory when the mode signal indicates the rewrite operation mode. Since the activation of the internal nonvolatile memory is inhibited during the normal operation mode, it is possible to prevent erroneous execution of the program in the internal nonvolatile memory during the normal operation mode, and to prevent data rewrite to the external nonvolatile memory.

Abstract: Each prefetch buffer has a tag register for storing a branch address and a data register for storing instruction data. Each of the prefetch buffers is assigned to either a first prefetch buffer rewritable during a normal operation period and a second prefetch buffer to be disabled for rewrite during the normal operation period. The second prefetch buffer can thus be prevented from being rewritten even if a central processor outputs branch addresses frequently. This realizes an improvement in the instruction fetch efficiency of the central processor and an improvement in the entire system performance. The fetch efficiency can be improved particularly in such systems that branch addresses occur frequently and some of them occur repeatedly.

Abstract: There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first register address, and using said second register address to access said register file. A computer system for carrying out such a technique is also enclosed.

Abstract: A reconfigurable parallel look-up table system includes a memory; a plurality of look-up tables stored in the memory; a row index register for holding the values to be looked up in the look-up tables; a column index register for storing a value representing the starting address of the look-up tables stored in the memory; and an address translation circuit responsive to the column index register and the row index register to simultaneously generate an address for each value in the row index register to locate in parallel the function of those values in each look-up table.

Abstract: A memory system includes a memory array for storing a plurality of data elements, the memory array comprising a plurality of memory blocks. In one embodiment, the data element are tag string data. The memory system may also include a comparator unit coupled to receive a memory block output and an input signal, wherein when the memory block output matches the input signal, the memory system transmits a match signal and a code word on a result bus. In one embodiment, data elements are stored as fragments in different portions of the memory array. The input signal may be received as fragments and compared to the data elements over different time periods. In one embodiment, the present invention provides a memory lookup system and method that supports multiple protocols.

Abstract: A signal processing device has a program memory for storing program code transferred from an external source under the control of an access control unit having an address counter. The transferred program code is executed by a computational unit having a program counter. The access control unit controls the transfer of the program code according to the values of both the address counter and the program counter, thereby enabling the computational unit to start executing the program code before the entire program has been transferred. Program initialization can therefore be completed quickly, and the program can promptly begin producing audible or visible results.

Abstract: An apparatus and method for memory allocation with digital processing systems comprises a first memory bank, a hardware register, and a processing circuit configured to write the contents of the hardware register to a memory address in the first memory bank, and to write the memory address to the hardware register. In an embodiment, a pointer list containing memory pointer values may be maintained in the first memory bank. The first memory bank may contain associated data buffers, and a second memory bank may contain corresponding data buffers such that an associated data buffer and a corresponding data buffer may be located from a single memory pointer value.

Abstract: A method for generating sequences of memory addresses for a memory buffer having N*M locations includes making a first address and a last address of every sequence respectively equal to 0 and to N*M−1, assigning a first sequence of addresses, and each address but a last address of another sequence of addresses is generated by multiplying a corresponding address of a previous sequence by N, and performing a modular reduction of this product with respect to N*M−1. The method further includes calculating a greatest bit length of every address, and calculating an auxiliary constant as the modular reduction with respect to N*M−1 of the power of two raised to twice the greatest bit length.

Abstract: Methods and apparatus enable: the partitioning of a main memory into a plurality of blocks, each block being adjacent to at least one of the other blocks, and each block including a plurality of data units containing one or more bits of data; the partitioning of each block of the main memory into a plurality of zones, each zone containing one or more of the data units; the association of at least some of the respective zones of each given block with respective others of the adjacent blocks to the given block; and the pre-fetching of a given one of the other blocks into a cache memory when any one of the data units within any of the associated zones of that block is addressed.

Abstract: An InfiniBand™ computing node includes a dual port memory configured for storing data for a CPU and a host channel adapter in a manner that eliminates contention for access to the dual port memory. The dual port memory includes first and second memory ports, memory banks for storing data, and addressing logic configured for assigning first and second groups of the memory banks to the respective memory ports based on prescribed assignment information. The host channel adapter is configured for accessing the dual port memory via the first memory port, and the CPU is configured for accessing the dual port memory via the second memory port. The CPU also is configured for providing the prescribed assignment information to the addressing logic, enabling the host channel adapter to access the first group of memory banks via the first memory port as the CPU concurrently accesses the second group of memory banks via the second memory port.

Abstract: A method and system for storing and accessing associations between network addresses and ports within a network multiplexer. The method and system implement an address table containing indexed address/port pairs. Multiple hash functions are applied to an input address in order to identify indexes of address table entries in which the input address may be stored. If the entries indexed by application of the multiple hash functions to an input source address are neither empty nor contain the input source address, then contents of one of the entries is discarded, and the input source address is placed into the now empty entry. Over time, discarded addresses are re-entered into the address table in a fashion equivalent to hash table reshuffling, but the computational inefficiencies inherent in hash table reshuffling are deferred and largely avoided.

Abstract: A predictive memory performance optimizing unit for use with an interleaved memory, for example a DDR SDRAM memory, and suitable for use in a computer graphics system, among others, is described. The unit maintains a queue of pending requests for data from the memory, and prioritizes precharging and activating interleaves with pending requests. Interleaves which are in a ready state may be accessed independently of the precharging and activation of non-ready interleaves. The unit utilizes idle cycles occurring between consecutive requests to activate interleaves with pending requests.

Abstract: A memory interface device (100) providing a fractional address interface between a data processor (104) and a memory system (102) and a method for retrieving intermediate data values from a memory system using fractional addressing. The device includes an address generator (108) for generating first and second memory addresses, the first memory address being less than or equal to a specified fractional address, the second memory address being greater than or equal to the fractional address. The device also includes a memory access unit (110) coupled to the address generator (108) for retrieving first and second data values from the memory system (102) at the first and second memory addresses, respectively. The device also includes a data access unit (112) for interpolating between the first and second data values and passing the interpolated value to the data processor (104).

Abstract: A memory interface for connecting a bus to memory comprises an input, a buffer, an address input, a generator, and a writer. The input receives a plurality of data words from the bus. The buffer buffers the data words received from the bus. The address input receives from the bus addresses associated with the plurality of data words. The generator generates a series of addresses in the memory into which the buffered data words may be written. The series of addresses are derived from the received addresses. The writer writes the buffered data words into the memory at the generated addresses.

Abstract: A method and apparatus for compressing a reference pattern (RP) with repeated substrings by encoding produce compressed reference patterns (CRPs) with reduce storage requirements. Operation codes and a flag are stored with the CRPs. During comparison of reference elements of the CRP to input elements (IEs) of an input pattern (IP), the operation codes are read and the reference pattern is decoded allowing all reference elements including those of the repeated substrings to be compared to IEs in the IP to determine if the RP appears within the IP.

Abstract: An apparatus comprising a memory device and one or more control circuits. The memory device may be configured to store and retrieve data. The one or more control circuits may be configured to control access to the memory device. Each of the control circuits may be configured to provide a readback of an internal address value when in a first state and a readback of a mask value when in a second state.

Abstract: A computer system includes a read ahead engine that receives a sequence of read requests and performs read ahead operations in accordance with various patterns detected within the sequence of read requests. The prefetch engine may implement the method of storing a first run value indicative of the run size of a first plurality of sequential read requests, and storing a first skip value indicative of a non-sequential skip associated with a subsequent read request. The method may further include determining whether a second run value indicative of the sequential run size of a second plurality of read requests equals the first run value, and whether a second skip value indicative of another non-sequential skip associated with an additional read request equals the first skip value. If the first run value equals the second run value, and the first skip value equals the second skip value, a stride pattern is indicated, and one or more read ahead operations according to the detected stride pattern may be initiated.

Abstract: A request message for transfer across an interface is formed by a method comprising the steps of representing each of a plurality of data chunks to be stored in the message by a respective chunk object, declaring each of the chunk objects as a variable on a program stack, storing a first data chunk in a first area of the message; storing a second data chunk in a second area of the message; and employing the chunk object representing the first data chunk to locate the first data chunk in the course of loading into the first chunk an offset value representing the location of the second chunk, wherein the offset value represents an offset from a base address of the message. The method enables an overloaded deference operator to employ an offset stored in a chunk object on the program stack to locate a particular chunk.

Abstract: An apparatus generates addresses for circular address buffers in a memory, in which a higher boundary of a circular buffer is implied from the current address. This approach is applied alone, and in combination with circular buffers which rely on an implied lower boundary to improve memory usage and flexibility in the design of circular buffers for integrated circuits. The dual mode address generator comprises inputs that receive a current address A, an address offset M, a buffer length L and a control signal; and logic configured to compute a first memory address for a buffer with an implied lower boundary and a second memory address for a buffer with an implied higher boundary in response to A, M, and L. One of the first and second memory addresses is provided in response to the control signal.

Abstract: An apparatus comprising a control circuit and a generation circuit. The control circuit may be configured to generate a mask signal, a unique counter control signal, and an incremented state signal in response to an address signal and a counter control signal. The generation circuit may (i) comprise an internal counter register and (ii) be configured to generate an output address in response to the mask signal, the unique counter control signal, and the incremented state signal. The mask signal may be configured to selectively mask the internal counter register.

Abstract: An addressing scheme and associated hardware allows for two different types of access, one for reading and one for writing, to take place. A memory device constructed according to the invention comprises a plurality of arrays of memory cells. Peripheral devices are provided for reading information out of and for writing information into the plurality of memory cells. The peripheral devices include a reorder circuit responsive to certain address bits for ordering bits received from the plurality of arrays and an address sequencer for routing certain of the address bits to the reorder circuit during a read operation. The method of the present invention comprises reordering a block of n-bit words output from a memory array according to information in certain address bits before outputting at least one n-bit word from a memory device.

Abstract: A computer system for storing corresponding instruction blocks in a compressed form in a main memory and in an uncompressed form in an instruction cache. The instruction cache line addresses for the uncompressed instruction blocks in the instruction cache have an algebraic correlation to the main memory line addresses for the compressed instruction blocks in the main memory. Preferably, the instruction cache line addresses are proportional to the corresponding main memory line addresses.

Abstract: A data processing device includes a memory system capable of a plurality of simultaneous accesses, a plurality of address generators each generating an address for accessing the memory system, an addressing register having a plurality of address registers, a data processing unit providing an operation process to the data read from the memory system, and a control unit controlling operations of the plurality of address generators and the data processing unit. The plurality of address generators can generate addresses from a common value in one address register to simultaneously read data designated by the generated addresses from the memory system.

Abstract: A memory device is comprised of a plurality of arrays of memory cells and peripheral devices for reading and writing information to the memory cells. The peripheral devices include a decode circuit responsive to a first portion of address information for identifying an address and is further responsive to a second portion of the address information for identifying an order. The address may be a read address or a write address, and the order may be the order for reading data or writing data, respectively. The peripheral devices may also include a read sequencer circuit or both a write sequencer circuit and a read sequencer circuit for reordering bits to be read or written in response to another portion of the address information. Methods of operating such a memory device including outputting or reading a word from a memory array in two prefetch steps or operations are also disclosed.

Abstract: The present invention relates to an instruction control device, and more particularly to an instruction control device which has achieved a high speed operational processing, such as a reduction in the amount of components, so as to enable an out-of-order instruction execution to thereby execute an instruction processing at high speed in an information processor.

Abstract: A storage of DSP receives and stores a plurality of signal processing modules according to which a digital tone signal is processed. Each signal processing module includes a plurality of data groups (e.g., program, fixed data, work data). The storage has a plurality of storage areas, each assigned to a different one of the data groups. Each storage area is divided into a plurality of division areas for the plurality of signal processing modules. DSP receives address qualifying information on the difference between the size of a specified data groups (e.g., work data) for a signal processing module and the size of a specified division area which stores the specified data group. DSP sequentially executes the plurality of signal processing modules. When it has completed executing of the current signal processing module, DSP uses the address qualifying information to determine the start address of the specified division area for the next signal processing module.

Abstract: A data processing apparatus has a main memory and a plurality of memory banks. A bank switching instruction designating a particular bank address of the first memory bank is stored in an arbitrary memory space in the main memory. A main return instruction designating a particular main address of the main memory is stored in the memory address represented by a particular bank address of the nth memory bank. When the bank switching instruction is read, the readout destination is branched to the first memory bank. Data stored in the first memory bank, the second memory bank, . . . , and the nth memory bank are successively read. When the main return instruction is read from the nth memory bank, the readout destination returns to the main memory.

Abstract: A system may include a memory file and an execution core. The memory file may include an entry configured to store an addressing pattern and a tag. If an addressing pattern of a memory operation matches the addressing pattern stored in the entry, the memory file may be configured to link a data value identified by the tag to a speculative result of the memory operation. The addressing pattern of the memory operation includes an identifier of a logical register, and the memory file may be configured to predict whether the logical register is being specified as a general purpose register or a stack frame pointer register in order to determine whether the addressing pattern of the memory operation matches the addressing pattern stored in the entry. The execution core may be configured to access the speculative result when executing another operation that is dependent on the memory operation.

Abstract: A non-power-of-two modulo N Gray-code counter (the “Gray-code counter”) and a binary incrementer-decrementer algorithm are disclosed.

Abstract: Methods and structure for loading a CRC value cache memory in a storage controller on the fly to reduce overhead processing associated with access to system memory to load the CRC value cache memory. The invention provides for circuits and methods for monitoring normal system accesses to system memory to manipulate CRC values in system memory in conjunction with associated access to disk drive of a storage subsystem. When accesses are detected loading or retrieving CRC values from system memory, the CRC values are loaded substantially in parallel into the CRC value cache memory.

Abstract: A non-power-of-two modulo N Gray-code counter (the “Gray-code counter”) and a binary incrementer-decrementer algorithm are disclosed.

Abstract: A system and method for calculating memory addresses in a partitioned memory in a processing system having a processing unit, input and output units, a program sequencer and an external interface. An address calculator includes a set of storage elements, such as registers, and an arithmetic unit for calculating a memory address of a vector element dependent upon values stored in the storage elements and the address of a previous vector element. The storage elements hold STRIDE, SKIP and SPAN values and optionally a TYPE value, relating to the spacing between elements in the same partition, the spacing between elements in the consecutive partitions, the number of elements in a partition and the size of a vector element, respectively.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory component, on a single integrated circuit, operated as a slave to an external master, includes a RAM, one or more configuration registers, data formatting logic, and associated control logic. The behavior of the memory component, and in particular the selection of a burst transfer format, is controllable via configuration register bits in the one or more configuration registers. Specifically, based on a format selection specified by the configuration bits, the control logic determines the sequence-length of the data transfers between the RAM and the external master. Other than the sequence-length, the data is not otherwise altered during the data transfers.

Abstract: A memory addressing system for a multi-bank memory device that generally provides no bank conflicts for stride 1 data access patterns and infrequent bank conflicts for power of 2 stride patterns or other access patterns of interest. In a preferred embodiment, the device comprises an address translation or remapping unit that remaps sequences of logical addresses into sequences of slightly aperiodic physical addresses such that the physical addresses do not form a repetitive pattern of period less than N+1, where N is the number of memory banks, and do not on average repeat a physical bank number within approximately N physical addresses. In large memory modules and embedded logic devices wherein multiple memory units communicate with multiple microprocessors in a single chip, the disclosed remapping combined with disclosed scrambling methods also achieves high tolerance of chip defects which would otherwise render chips unusable, thereby yielding manufacturing economies.