Abstract: A virtual machine storage service can be use a unique network identifier and a SR-IOV compliant device can be used to transport I/O between a virtual machine and the virtual machine storage service. The virtual machine storage service can be offloaded to a child partition or migrated to another physical machine along with the unique network identifier.

Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.

Abstract: The invention concerns a method for read-addressing a site among a plurality of storage units using a coded address derived from an instruction. The method comprises the following steps: a) predicting (104) the storage unit corresponding to the site to be addressed; b) decoding (108) the address of the site to be addressed and determining (109) the storage unit to be addressed; c) managing (105) a potential read and rewrite conflict assuming that the predicted storage unit is the storage unit to be addressed; d) controlling (111) the addressing of the predicted storage unit at the end of the managing step (105); e) at the end of step b), determining (110) whether the storage unit to be addressed corresponds to the predicted storage unit; and f) if the storage unit to be addressed does not correspond to the predicted storage unit, managing (115) a possible read and rewrite conflict in the storage unit to be addressed and addressing the site of the storage unit to be addressed.

Abstract: A FLASH translation layer (FTL) includes a translation table that is maintained in non-FLASH memory. The translation table maps logical addresses to physical addresses and may be maintained in phase change memory (PCM). A bad block table (BBT) may also be maintained in non-FLASH memory.

Abstract: A data storage system and method are disclosed. The data storage system includes a first and a second memory and a memory control unit. The first memory is non-volatile, and the second memory is designed to store dynamic information of the first memory. The memory control unit includes a snapshot module, a recording module and a power-off recovery module, and is operative to handle the data loss of the second memory when an unexpected power-off occurs. When the power of the system is recovered, an initial address stored in the first memory by the snapshot module and link information and updating information recorded in the first memory by the recording module are obtained by the power-off recovery module to recovery the second memory.

Abstract: A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application.

Abstract: Systems and/or methods that facilitate PBA and LBA translations associated with a memory component(s) are presented. A memory controller component facilitates determining which memory component, erase block, page, and data block contains a PBA in which a desired LBA and/or associated data is stored. The memory controller component facilitates control of performance of calculation functions, table look-up functions, and/or search functions to locate the desired LBA. The memory controller component generates a configuration sequence based in part on predefined optimization criteria to facilitate optimized performance of translations. The memory controller component and/or associated memory component(s) can be configured so that the translation attributes are determined in a desired order using the desired translation function(s) to determine a respective translation attribute based in part on the predefined optimization criteria. The LBA to PBA translations can be performed in parallel by memory components.

Abstract: A method for performing a transaction including a transaction head and a transaction tail, includes executing the transaction head, including executing at least one memory reserve instruction to reserve a transactional memory location that are accessed in the transaction and executing the transaction tail, wherein the transaction cannot be aborted due to a data race on that transactional memory location while executing the transaction tail, wherein data of memory write operations to the transactional memory location is committed without being buffered.

Abstract: A method for managing memory in a nested virtualization environment is provided. The method comprises implementing a first virtual machine (VM) for a first software such that a first guest memory is allocated to the first software; maintaining a first data structure to translate one or more memory addresses in the first guest memory to corresponding memory addresses in a physical memory; maintaining a second data structure to translate one or more memory addresses in the second guest memory to corresponding memory addresses in the physical memory. The first software implements a second VM for a second software such that a second guest memory is allocated to the second software and maintains a third data structure to translate one or more memory addresses in the second guest memory to corresponding memory addresses in the first guest memory.

Abstract: A data recording method including, when moving data stored in a cache to a data storage medium, selecting one cache area from an extended cache area group of the data storage medium by using managing information of a translation layer, moving the data stored in the cache to the selected cache area by using a physical address of the data storage medium on the selected cache area, and updating the managing information of the translation layer, wherein the managing information of the translation layer includes a physical block address-based address of the extended cache area group in the data storage medium.

Abstract: The memory device comprises a physical memory plane (PMP) comprising m first physical lines (RGP1i) extending along a first direction and n second physical lines (RGP2j) extending along a second direction, reception means for receiving a logical address (ADR) designating a first logical line (RG1i) and a second logical line (RG2j) of a matrix logical memory plane (PML), possessing 2p first logical lines extending along the first direction and 2q second logical lines extending along the second direction, in that m and n are each different from a power of two, m being a multiple of 2k, k being less than or equal to p, and the product of m and n being equal to the nearest integer above 2p+q, and in that it comprises means for addressing the physical memory plane (PMP) that are configured to address a first physical line and a part only of a second physical line on the basis of the content of the said logical address received and of the remainder of a Euclidean division of a part of the content of this logical ad

Abstract: A method of controlling access to a multi-bank memory, and an apparatus to perform the method, is provided. For the access control, a stride register is provided to store stride values determined by a processor during a run time. A memory controller controls access to a logical block in row and column directions, in an interleaved manner, the logical block having a width determined according to the stride values stored in the stride register. Accordingly, simultaneous access to a plurality of pieces of data at successive addresses adjacent in the row and column directions may be made.

Abstract: There are provided a storage system and a method of operating thereof. The method comprises: a) representing to a plurality of hosts an available logical address space divided into one or more logical groups (e.g. logical volumes, virtual partitions, snapshots, combinations of a given logical volume and its respective snapshot(s), etc.), and b) mapping between one or more contiguous ranges of addresses related to the logical address space and one or more contiguous ranges of addresses related to the physical address space, wherein said mapping is provided with the help of one or more mapping trees, each tree assigned to a separate logical group in the logical address space.

Abstract: A method begins when a dispersed storage (DS) processing unit of a DS unit has at least one of DS unit operational data and DS unit operating system algorithm to store. The method continues with the DS processing unit encoding at least a portion of the at least one of DS unit operational data and DS unit operating system algorithm in accordance with an error coding dispersal storage function to produce a plurality of data slices. The method continues with the DS processing unit storing at least some of the plurality of data slices in memory devices of the DS unit in accordance with the error coding dispersal storage function.

Abstract: One embodiment of the present invention sets forth a technique for computing dynamic random access memory (DRAM) addresses from linear physical addresses for memory subsystems implementing integral power of two virtual page sizes, and an arbitrary number of available partitions. Each DRAM address comprises a row address, column address, bank address, and partition address. The linear physical address is used to generate to the DRAM address in units of a DRAM bank size. Address scrambling may be implemented to overcome transient access contention to specific DRAM pages by multiple client modules.

Abstract: The invention provides a data access method of a memory device. In one embodiment, the memory device comprises a plurality of memories. First, a plurality of commands sequentially received from a host is stored in a command queue. A target command is then retrieved from the command queue. A target memory accessed by the target command is then determined. Whether the target memory is in a busy state is then determined. When the target memory is not in a busy state, access operations requested by the target command are then performed. When the target memory is in a busy state, a substitute command is selected from a plurality of subsequent commands stored in the command queue and access operations requested by the substitute command are performed, wherein the sequence of the subsequent commands in the command queue is subsequent to the target command.

Abstract: One embodiment of the present invention sets forth a technique for unifying the addressing of multiple distinct parallel memory spaces into a single address space for a thread. A unified memory space address is converted into an address that accesses one of the parallel memory spaces for that thread. A single type of load or store instruction may be used that specifies the unified memory space address for a thread instead of using a different type of load or store instruction to access each of the distinct parallel memory spaces.

Abstract: A block management method for managing a plurality of physical blocks of a flash memory chip is provided. The block management method includes configuring a plurality of logical addresses; mapping the logical addresses to a plurality of logical blocks; and mapping the logical blocks to the physical blocks. Additionally, the block management method also includes obtaining deleting records related to a plurality of deleted logical addresses from a host system, wherein data stored in the deleted logical addresses is recognized as invalid by the host system. And, the block management method further includes obtaining a deleted logical block, marking each of the logical addresses mapped to the deleted logical block as a bad logical address, and linking the physical block mapped to the deleted logical block to a spare area. Accordingly, the block management method can effectively prolong the lifespan of a flash memory chip.

Abstract: In a management computer which manages a storage system including a main logical volume and subsidiary logical volumes, when the access volume to the main logical volume exceeds a threshold value, a subsidiary logical volume associated with a physical volume having higher input/output performance than the physical volume associated with the main logical volume is selected. When the migration time of the data stored in the physical volume corresponding to the selected subsidiary logical volume is within a prescribed time period, then data stored in the physical volume corresponding to the main logical volume is migrated to the physical volume corresponding to the selected subsidiary logical volume, and the physical volume corresponding to the selected subsidiary logical volume is associated with the main logical volume.

Abstract: A system, method and computer-readable medium for updating an address translation table. In the method, a message indicating a physical memory location that corresponds to a virtual address is received from a processor. An I/O Memory Management Unit (IOMMU) is used to update an entry within the address translation table corresponding to the virtual address according to the indicated physical memory location.

Abstract: A method for writing and reading data in memory cells, comprises the steps of: defining a virtual memory, defining write commands and read commands of data (DT) in the virtual memory, providing a first nonvolatile physical memory zone (A1), providing a second nonvolatile physical memory zone (A2), and, in response to a write command of an initial data, searching for a first erased location in the first memory zone, writing the initial data (DT1a) in the first location (PB1(DPP0)), and writing, in the metadata (DSC0) an information (DS(PB1)) allowing the first location to be found and an information (LPA, DS(PB1)) forming a link between the first location and the location of the data in the virtual memory.

Abstract: A processor cache is indexed by a group of distinct page colors. The use of this cache by different working sets is controlled using page coloring. Translations of virtual addresses of the instructions and/or data of a working set are constrained to physical addresses the page colors of which are in a subgroup of the group of distinct page colors.

Abstract: A memory system according to the present invention includes a bus connected to process units, a first DRAM which has a first storage area and a second storage area and which is controlled in operation by a DRAM control signal, a second DRAM which has the same bit width as that of the first DRAM, which has a third storage area having the same address space as that of the first storage area and having a capacity equal to that of the first storage area, and which is controlled in operation by the DRAM control signal, and a controller which is provided with a read command and a logical address from the process units via the bus, which controls operation of the first DRAM and the second DRAM according to the read command and the logical address, and thereby outputs data read from the first DRAM or the second DRAM to the process units via the bus.

Abstract: According to one embodiment, a memory system includes a first memory chip includes a first temporary memory and a first block, a second memory chip includes a second temporary memory and a second block, and a memory controller that controls writing of logical pages to the first and second memory chips. The memory controller forms a second unit having the same page number as the first unit by the first temporary memory and the lowermost physical page in the first block, forms a third unit having the same page number as the first unit by the second temporary memory and the lowermost physical page in the second block, and writes the logical pages by an interleave operation in order of the second unit, the third unit, the first unit in the first block, and the first unit in the second block.

Abstract: A storage control device for controlling the storage device including a medium for storing data, logical address information, and address translation information and a memory for storing the address translation information read from the medium includes a first receiver for receiving a write request including logical address information, a first sending module for sending a read request including the logical address information of the write request to the storage device, a second receiver for receiving data and logical address information stored in the medium in accordance with the read request from the storage device, and a second sending module for sending an instruction to cause the storage device to write the address translation information stored in the medium into the memory when the logical address information received by the second receiver is different from logical address information included in the write request.

Abstract: Some embodiments of the present invention provide a system that maps an address to an entity, wherein the mapping interleaves addresses between a number of entities. During operation, the system receives an address A from a set of X consecutive addresses, wherein the address A is to be mapped to an entity E in a set of Y entities, and wherein Y need not be a power of two. Next, the system obtains F=floor(log2(Y)) and C=ceiling(log2(Y)). The system then calculates L, which equals the value of the F least-significant bits of A. The system also calculates M, which equals the value of the C most-significant bits of A. Next, the system calculates S=L+M. Finally, if S<Y, the system sets E=S. Otherwise, if S?Y, the system sets E=S?Y.

Abstract: A translation look-aside buffer (TLB) is described. The TLB may include a memory populated with pointers to collections (e.g., tables) of virtual-to-physical address translations. The memory may be populated by, for example, a page fault logic in response to resolving a page fault. The TLB may also include a signal logic to receive a virtual address and to selectively provide either a miss signal or a pointer to a collection of virtual-to-physical translations. The signal may provide the miss signal upon determining that the virtual address is not associated with a stored pointer and may provide a pointer upon determining that the virtual address is associated with the pointer.

Abstract: A coherency control system includes a logical-physical address translation unit which translates a logical address including a first tag and an index address into a physical address including a second tag and the index address, a request output unit which transmits a load request, a corresponding state storage unit which stores a relation state between an area of the second storage apparatus and an area of the first storage apparatus based on the way number included in the load request and the second tag and the index address of the physical address also included in the load request which has been received, and an invalidation instructing unit which transmits an invalidation instruction including the index address and the way number based on the second tag of the physical address included in the store request and the relation state stored in the corresponding state storage unit.

Abstract: A memory controller (101) according to this invention includes: a command generation unit (102) which generates access commands each including a physical address, based on an access request including a logical address indicating a rectangular area in image data; and a command issuance unit (105) which issues, to a memory (0), the access commands generated by the command generation unit (102). The command generation unit (102) includes a group determination unit (104) which determines a group to which a bank including data to be accessed belongs, based on the physical address corresponding to the access request. The command generation unit (102) generates a pair of a first and a second access commands which share a prefetch buffer between two banks belonging to different groups, when data to be accessed is continuous across two banks belonging to different groups.

Abstract: Roughly described, a data processing system comprises a central processing unit and a split network interface functionality, the split network interface functionality comprising: a first sub-unit collocated with the central processing unit and configured to at least partially form a series of network data packets for transmission to a network endpoint by generating data link layer information for each of those packets; and a second sub-unit external to the central processing unit and coupled to the central processing unit via an interconnect, the second sub-unit being configured to physically signal the series of network data packets over a network.

Abstract: A computing system comprises at least a processing module, a main memory, a memory controller, and a plurality of memory components. A method begins by the memory controller receiving a memory access request regarding a data segment. The method continues with the memory controller interpreting the memory access request to determine whether an error encoding dispersal function of the data segment is applicable. The method continues with the memory controller identifying at least a threshold number of memories based on the memory access request, wherein the threshold number of memories includes at least one of the main memory and/or one or more of the plurality of memory components, when the error encoding dispersal function is applicable. The method continues with the memory controller addressing the at least a threshold number of memories to facilitate the memory access request.

Abstract: Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the location of the first lookup table in non-volatile memory. An index cache tree in volatile memory holds the physical addresses of the most recently written or accessed logical sectors in a compressed format.

Abstract: Embodiments of the present invention are directed to systems and methods of controlling data transfer between a host system and a plurality of storage devices. One embodiment is directed to a virtualization controller for controlling data transfer between a host system and a plurality of storage devices. The virtualization controller comprises a plurality of first ports for connection with the plurality of storage devices each having a storage area to store data; a second port for connection with the host system; a processor; and a memory configured to store volume mapping information which correlates first identification information used by the host system to access a first storage area in one of the storage devices, with second identification information for identifying the first storage area, the correlation being used by the processor to access the first storage area.

Abstract: A system includes a processor with a memory map specifying a user mode region with virtual address translation by a memory management unit and a kernel mode region with direct virtual address translation. The processor executes an application in the user mode region where virtual addresses are not unique. A probe receives trace information from the processor. A host system receives the trace information from the probe. The host system includes a data structure associating a process name, a process identification and a set of instruction counters. Each instruction counter is incremented upon the processing of a designated virtual address within the trace information. A profiling module processes information associated with the process name and set of instruction counters to identify a performance problem in the application.

Abstract: A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application.

Abstract: A method of address translation in a computing system providing direct memory access (DMA) by way of one or more remote memory management units (MMUs) is provided. The method comprises intercepting a request for a first DMA operation forwarded by a first device to a second device; and translating a guest address included in the request to a first address according to a mapping referencing a memory frame in a memory of the second device. A local MMU increments a first reference count indicating number of active DMA operations directed to the memory frame and a second reference count indicating number of remote MMUs that have mapped the memory frame.

Abstract: Methods, devices, and systems for employing binary objects representing SIP messages. More specifically, a binary SIP stack is provided which allows a mechanism to enhance the efficiency of communications and more particularly to enhance the efficiency of SIP communications between SIP network elements.

Abstract: A memory system to manage a memory using a virtual memory is provided. The memory system may use an asymmetric memory as a swap storage of a dynamic random access memory (DRAM). The asymmetric memory may access on a byte basis, allowing a process to directly access a page swapped out to the asymmetric memory through direct mapping.

Abstract: A data storage device capable of improving reading and writing performance includes at least one memory chip comprising a control unit and a plurality of blocks for storing data, and communicating with a host through a channel; and memory storing data output from the at least one memory chip. The control unit may sequentially read data having continuous logic addresses and discontinuous physical addresses from the plurality of blocks and store the data in the memory to have continuous physical addresses.

Abstract: A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address.

Abstract: A semiconductor recording apparatus includes a logical-to-physical conversion table 115 showing correspondence between a physical address of said semiconductor memory and a logical address and writes the table to a flash memory 120. On receiving a write command issued from a host device 200, a block management section 114 selects a physical block with reference to said logical-to-physical conversion table, and updates said logical-to-physical conversion table. A logical-to-physical conversion table initializing section 117 updates a physical address corresponding to each logical address of the logical-to-physical conversion table into an invalid address. Accordingly the apparatus can render the number of rewrites of physical blocks uniform irrespective of writing conditions.

Abstract: In one embodiment, a processor comprises execution circuitry and a translation lookaside buffer (TLB) coupled to the execution circuitry. The execution circuitry is configured to execute a store instruction having a data operand; and the execution circuitry is configured to generate a virtual address as part of executing the store instruction. The TLB is coupled to receive the virtual address and configured to translate the virtual address to a first physical address. Additionally, the TLB is coupled to receive the data operand and to translate the data operand to a second physical address. A hardware accelerator is also contemplated in various embodiments, as is a processor coupled to the hardware accelerator, a method, and a computer readable medium storing instruction which, when executed, implement a portion of the method.

Abstract: The present invention discloses a data accessing method and an apparatus for performing the method. Through a newly-defined host logical unit (HLUN), a unique HLUN number is given to each LUN-to-LD/Partition mapping relationship, and the HLUN is present to external hosts. Therefore, all of the hosts in the same storage system may recognize different logical units (i.e., HLUN). Hence, when processing an Input/Output (IO) request issued from any one host, a storage virtualization controller (SVC) can correctly find the corresponding LD/Partition for accessing data without identifying the identity of the host.

Abstract: Techniques and systems are described herein to maintain a mapping of logical to physical registers—for example, in the context of a multithreaded processor that supports renaming. A mapping unit may have a plurality of entries, each of which stores rename information for a dedicated one of a set of physical registers available to the processor for renaming. This physically-indexed mapping unit may support multiple threads, and may comprise a content-addressable memory (CAM) in certain embodiments. The mapping unit may support various combinations of read operations (to determine if a logical register is mapped to a physical register), write operations (to create or modify one or more entries containing mapping information), thread flush operations, and commit operations. More than one of such operations may be performed substantially simultaneously in certain embodiments.

Abstract: The method of operating the data storage device includes performing channel distribution non-sequentially based on a logical address included in a data signal and outputting a channel address, and at least one of writing data to and reading stored data from a memory connected to one of a plurality of channels based on the channel address.

Abstract: A cartridge preferably for use with a game console. The cartridge comprises a ROM, a non-volatile memory, a processor and a dispatcher. An application running on the console may communicate with the dispatcher using predefined addresses, which enables the dispatcher to access the ROM, the non-volatile memory, or the processor, as the case may be. The invention improves on the prior art copy protection as no generic copy method may be found if the addresses are changed from one cartridge to another. In addition, to copy the software, the processor must be emulated.

Abstract: A controller, a data storage device and a data storage system including the controller, and a data processing method are provided. The controller may process a plurality of instructions in parallel by including a plurality of address translation central processing units (CPUs) in a multi-channel parallel array structure, thereby improving the performance of a semiconductor memory system.

Abstract: Intelligent resource state memory recall techniques, and associated apparatus and methods, are disclosed. States of one or more video switcher resources in a resource state memory may be recalled to the same or different resources, depending on resource availability at the time of memory recall. A memory recall need not affect an on air signal. The memory may be recalled to recreate a desired program output, as defined in the memory, on a preview output of the video switcher, which leaves a current program output of the video switcher undisturbed when the memory is recalled.

Abstract: A memory system comprises a nonvolatile memory device and a controller. The controller comprises a working memory and is configured to control the nonvolatile memory device. The nonvolatile memory device is configured to store drive data required to access the nonvolatile memory device. When an initialization operation of the memory system is performed, the controller activates an operation standby signal after loading a portion of the drive data stored in the nonvolatile memory device into the working memory.

Abstract: A distributed data processing system executes multiple tasks within a parallel job, including a first local task on a local node and at least one task executing on a remote node, with a remote memory having real address (RA) locations mapped to one or more of the source effective addresses (EA) and destination EA of a data move operation initiated by a task executing on the local node. On initiation of the data move operation, remote asynchronous data move (RADM) logic identifies that the operation moves data to/from a first EA that is memory mapped to an RA of the remote memory. The local processor/RADM logic initiates a RADM operation that moves a copy of the data directly from/to the first remote memory by completing the RADM operation using the network interface cards (NICs) of the source and destination processing nodes, determined by accessing a data center for the node IDs of remote memory.