Abstract: The invention relates to a microprocessor having a plurality of components which are selected from registers (14,16), arithmetic logic units (30,32), memory (36,38), input/output circuits and other similar components where the plurality of components are interconnected in a manner which allows connection between some of the components to be varied under program control.

Abstract: A processor is provided. The processor includes at least two cores. The at least two cores have a first level cache memory and are multi-threaded. A crossbar is included. A plurality of cache bank memories in communication with the at least two cores through the crossbar is provided. Each of the plurality of cache bank memories communicates with a main memory interface. A plurality of input/output interface modules in communication with the main memory interface and providing a link to the at least two cores are included. The link bypasses the plurality of cache bank memories and the crossbar. Threading hardware configured to enable the at least two cores to switch from a first thread to a second thread in a manner hiding delays caused by cache accesses is included. A server and a method for determining when to switch threads in a multi-core multi-thread environment are included.

Abstract: A spilling method in register files for a processor is proposed. The processor is of Parallel Architecture Core (PAC) structure, and accordingly includes a first cluster, a second cluster and a memory. Each of the first and second clusters includes a first function unit (e.g., M-Unit), a second function unit (e.g., I-Unit), a first local register file, a second local register file and a global register file. The first and second local register files are used by the first and second function units, respectively.

Abstract: A computing system that includes a number of processing elements, a memory and a multi-task controller is disclosed. The memory has an interface that includes a task page mechanism with an index register. A portion of the multi-task controller also has a task page register for accessing the memory via another interface. The task page mechanism provides access to the memory by the host processor. The index register can be loaded by either the address or data bus of the host processor. In one embodiment, the task page mechanism includes a comparator and a counter to facilitate a polling scan of the status of the various tasks in the memory.

Abstract: A method and a device are provided for performing switching and data comparison in a computer system having at least two processing units which each process data at a specified clock pulse, in which a switchover arrangement is provided and switching takes place between at least two operating modes, and a comparison unit is provided. A first operating mode corresponding to a compare mode is provided, and a second operating mode corresponding to a performance mode is provided. A synchronization arrangement is provided which assigns to the specifiable data a clock pulse information as a function of a processing unit, and at least the comparison unit takes into consideration this clock pulse information in the corresponding data.

Abstract: A unit and method for clock changeover in a system having at least two processing units, in which switchover device(s) are provided by which a switchover between at least two operating modes of the system is able to be implemented in which a clock pulse changeover is carried out in at least one processing unit in a switching of the operating mode.

Abstract: A set of helper thread binaries is created to retrieve data used by a set of main thread binaries. The set of helper thread binaries and the set of main thread binaries are partitioned according to common instruction boundaries. As a first partition in the set of main thread binaries executes within a first core, a second partition in the set of helper thread binaries executes within a second core, thus “warming up” the cache in the second core. When the first partition of the main completes execution, a second partition of the main core moves to the second core, and executes using the warmed up cache in the second core.

Abstract: The specification discloses a computer program and computer-based system and method for interrogating a user and generating a result, for example a report, custom video presentation, web-site presentation, etc., based upon the user's interrogatory answers.

Abstract: Various approaches for profiling a target system are described. In one approach, a uni-directional, point-to-point bus has a single input port and a single output port. A target processor has a trace port coupled to the input port of the bus and is configured to execute a plurality of instructions one or more times. The target processor provides state data at the trace port and to the input port of the bus. A profile circuit arrangement is coupled to the output port of the first bus, and a memory is coupled to the profile circuit arrangement. The profile circuit arrangement is configured to read data from the output port of the first bus and write the data to the memory.

Abstract: Embodiments of the present invention provide a system for transferring data between a receiver chip and a transmitter chip. The system includes a set of data path circuits in the transmitter chip and a set of data path circuits in the receiver chip coupled to a shared data channel. In addition, the system includes a set of asynchronous control circuits for controlling corresponding data path circuits in the transmitter chip and receiver chip. Upon detecting the transition of a control signal for an asynchronous control circuit in the transmitter chip, the asynchronous control circuit is configured to enable a transfer of data from the corresponding data path circuit in the transmitter chip across the data channel to a corresponding data path circuit in the receiver chip, and generate a control signal to cause a next asynchronous control circuit to commence the transfer of a data signal.

Abstract: Disclosed are methods, apparatus, and systems for the interconnection of electronic system apparatus having one or more different communication protocols. A preferred embodiment is disclosed in which a single physical interface and a single protocol are used for providing an efficient and scalable interconnection between a host and operably coupled subsystem apparatus connected to the MMC. In a disclosed method, a bus is provided for coupling a system host to a plurality of system components and a Multi-Management Protocol (MMP) is employed. The Multi-Management Protocol includes a plurality of subclasses, each further including component identity information and function data. The subclasses are grouped by functionality into at least two groups comprising a standard group and an extension group.

Abstract: One embodiment of a video processor includes a first media processing device coupled to a first memory and a second media processing device coupled to a second memory. The second media processing device is coupled to the first media processing device via a scalable bus. A software driver configures the media processing devices to provide video processing functionality. The scalable bus carries video data processed by the second media processing device to the first media processing device where the data is combined with video data processed by the first media processing device to produce a processed video frame. The first media processing device transmits the combined video data to a display device. Each media processing device is configured to process separate portions of the video data, thereby enabling the video processor to process video data more quickly than a single-GPU video processor.

Abstract: Embodiments of circuits for processors with multiple redundancy techniques for mitigating radiation errors are described herein. Other embodiments and related methods and examples are also described herein.

Abstract: This invention discloses a method for executing vertex shader in a computer system, the method comprising running software vertex shader for a predetermined vertex shader command in a CPU thread when a GPU is overloaded by vertex shader execution, buffering the output of the software vertex shader, running hardware vertex shader for z-values of the vertex shader command, and replacing z-values from the software vertex shader with the z-values from the hardware vertex shader, wherein the vertex shader overloading can be lessoned yet the vertex shader z-values are consistently transformed by the hardware vertex shader.

Abstract: Executing MIMD programs on a SIMD machine, including establishing SIMD partitions on the SIMD machine; booting SIMD partitions in MIMD mode; executing MIMD programs on the compute nodes of a first SIMD partition booted in MIMD mode; re-executing a launcher program by an operating system on a compute node in the first SIMD partition booted in MIMD mode upon termination of the MIMD program executed by the launcher program; determining by a scheduler that the first SIMD partition booted in MIMD mode is required to establish a new SIMD partition large enough to run a SIMD program that is scheduled for execution; moving by the scheduler data processing operations from the first SIMD partition booted in MIMD mode to the second SIMD partition booted in MIMD mode; and establishing by the scheduler the new SIMD partition.

Abstract: A computer configured for a connection to a network of computers including the Internet, comprising: a microchip including a microprocessor including a master control unit configured using hardware and firmware, and two processing units; an internal hardware firewall that is located between a protected portion and an unprotected portion of the microchip; said protected portion including said master control unit and one of the processing units, said unprotected portion including one or more of the processing units that are separate from and located outside of the internal hardware firewall; said hardware firewall denying access to said protected portion by the network; and said hardware firewall permitting access by another computer in the network to one or more of the processing units included in the unprotected portion for an operation with said another computer in the network; and an active configuration of a circuit integrated into the microchip.

Abstract: A universal register rename mechanism for instructions with multiple targets using a common destination tag. For each instruction that updates multiple destinations, a single rename entry is allocated to handle all destinations associated with it. A rename entry now consists of a DTAG and a vector to indicate the type of destination(s) that is/are being updated by such a particular instruction. For example, a common DTAG can be assigned to a fixed point unit instruction (FXU) that updates general purpose register (GPR), fixed point exception register (XER), and condition code register (CR) destinations. During flush time, the DTAGs in the recovery link may be used to restore the information indicating that the youngest instruction updates a particular architected register. By using a single, universal rename structure for all types of destinations, a large saving in silicon and power can be realized without the need to sacrifice performance.

Abstract: This invention describes a baseband dual-core signal processing in mobile communication systems operating according to GSM, GPRS, or EDGE comprising a first digital signal processor adapted to perform tasks on a first time basis and a second digital signal processor adapted to perform tasks on a second time basis. The second time basis is an integer multiple of the first time basis.

Abstract: A data processing apparatus and method are provided for managing polling loops. The data processing apparatus comprises a main processing unit and a subsidiary processing unit operable to perform a task on behalf of the main processing unit. The subsidiary processing unit is operable to set a completion field when the task has been completed and the main processing unit is operable to poll the completion field in order to determine whether the task has been completed. If on polling the completion field a threshold number of times the main processing unit determines that the task has not been completed, the main processing unit is operable to enter a power saving mode. The subsidiary processing unit is operable, when the task has been completed, to cause a notification to be issued on a path interconnecting the main processing unit and the subsidiary processing unit. The main processing unit is arranged, upon receipt of the notification to exit the power saving mode.

Abstract: A processing apparatus that is capable of dynamically updating a database when a processing device set for use is newly added, thus providing a process performed by the newly added processing device. In the processing apparatus, among a plurality of processing devices, a processing device that is not in use is set for use, and a registration request is issued for registering process designating information corresponding to the processing device set for use. Based upon the issued registration request, the process designating information corresponding to the processing device set for use is registered in the database.

Abstract: A system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints.

Abstract: Provided is a system comprising a first node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the first node connect via their processor fabrics; a second node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the second node connect via their processor fabrics; and a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes.

Abstract: Producers and consumer processes may synchronize and transfer data using a shared data structure. After locating a potential transfer location that indicates an EMPTY status, a producer may store data to be transferred in the transfer location. A producer may use a compare-and-swap (CAS) operation to store the transfer data to the transfer location. A consumer may subsequently read the transfer data from the transfer location and store, such as by using a CAS operation, a DONE status indicator in the transfer location. The producer may notice the DONE indication and may then set the status location back to EMPTY to indicate that the location is available for future transfers, by the same or a different producer. The producer may also monitor the transfer location and time out if no consumer has picked up the transfer data.

Abstract: A multi-mode parallel graphics rendering and display system supporting real-time graphics rendering and display operations using a graphics hub device. The system includes a CPU memory space, one or more CPUs for executing graphics-based applications, and a multi-mode parallel graphics rendering system (MPGRS) supporting multiple modes of parallel operation including object division, image division, and time division. The MMPGRS includes a plurality of graphic processing pipelines (GPPLs) that support a parallel graphics rendering process employing one or more modes of parallel operation.

Abstract: Resources may be dynamically allocated in a distributed processing portable electronic communication device. The dynamic allocation may include receiving an instruction to process an audio processing task related to audio data; determining whether resources for processing the processing task are available at a first processing unit; performing the audio processing task by the first processing unit when the resources are determined to be available, the audio processing task obtaining processed audio data; and providing the processed audio data synchronously with a global synchronization pulse so that the phase of the audio data is controlled.

Abstract: A unified register rename mechanism for targets of different instruction types is provided in a microprocessor. The universal rename mechanism renames destinations of different instruction types using a single rename structure. Thus, an instruction that is updating a floating point register (FPR) can be renamed along with an instruction that is updating a general purpose register (GPR) or vector multimedia extensions (VMX) instructions register (VR) using the same rename structure because the number of architected states for GPR is the same as the number of architected states for FPR and VR. Each destination tag (DTAG) is assigned to one destination. A floating point instruction may be assigned to a DTAG, and then a fixed point instruction may be assigned to the next DTAG and so forth. With a universal rename mechanism, significant silicon and power can be saved by having only one rename structure for all instruction types.

Abstract: A microprocessor includes a direct access memory (DMA) engine which is responsive to pairs of block indices associated with one or more blocks in a first logical plane and transfers the one or more blocks between the first logical plane, a second logical plane, and a physical memory space according to the pairs of block indices. The logical planes represent two dimensional fields of data such as those found in images and videos. The microprocessor further comprises cache memory which updates its content with one or more cache-blocks which are in the neighborhood of the one or more blocks improving the operation of the cache memory by increasing cache hits. The DMA engine may further operate on n-dimensional blocks in a n-dimensional logical space. The microprocessor further includes special-purpose instructions, operative on a single-instruction-multiple-data (SIMD) computation unit, especially tailored to perform matrix operations.

Abstract: A network device includes one or more processing units and an external memory. Each of the one or more processing units includes a centralized counter configured to perform accounting for the respective processing unit. The external memory is associated with at least one of the one or more processing units and is configured to store a group of count values for the at least one processing unit.

Abstract: A method is for designing an accelerator for digital signal processing including defining a software programmable fully pre-laid out macro by pre-laying out with a fixed topology a control logic of the DSP accelerator to obtain a fully pre-laid out control logic. The method further includes defining a hardware programmable partially pre-laid out macro by customizing a configurable layout area, thereby mapping a computational logic based on computation kernels related to an application of the DSP accelerator. A partially pre-laid out computational logic is therefore obtained.

Abstract: A method of providing physics data within a game program or simulation using a hardware-based physics processing unit having unique architecture designed to efficiently calculate physics related data.

Abstract: Secure operation of cell processors is disclosed. A cell processor receives a secure file image from a client device at a cell processor of a host device (host cell processor), wherein the secure file image includes an encrypted SPU image.

Abstract: A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

Abstract: In general, in one aspect, the disclosure describes a system including multiple programmable processing units, a dedicated hardware multiplier, and at least one bus connecting the multiple processing units and multiplier.

Abstract: A device may include a data processing logic cell field and one or more sequential CPUs. The logic cell field and the CPUs may be configured to be coupled to each other for data exchange. The data exchange may be in block form using lines leading to a cache memory. In a method for operating a reconfigurable unit having runtime-limited configurations, the configurations may be able to increase their maximum allowed runtime, e.g., by triggering a parallel counter. An increase in configuration runtime by the configurations may be suppressed in response to an interrupt.

Abstract: The present invention relates generally to computer programming, and more particularly to systems and methods for parallel distributed programming. Generally, a parallel distributed program is configured to operate across multiple processors and multiple memories. In one aspect of the invention, a parallel distributed program includes a distributed shared variable located across the multiple memories and distributed programs capable of operating across multiple processors.

Abstract: A method for reducing electromagnetic emissions in an electronic device having a multiple micro-controllers includes identifying the number of micro-controllers installed in the electronic device. An operating frequency range of the electronic device is determined based on the operating frequency range of each micro-controller. A frequency spacing for each micro-controller within the operating frequency range of the electronic device is then calculated, and an operating frequency is assigned to each micro-controller. The operating frequency of each micro-controller is separated from the operating frequency of each other micro-controller by at least the frequency spacing. Then, the operating frequency of each micro-controller is set at the assigned operating frequency.

Abstract: A cell element field for data processing having function cells for execution of algebraic and/or logic functions and memory cells for receiving, storing and/or outputting information is described. A control connection may lead from the function cells to the memory cells.

Abstract: A data processing apparatus processes a stream of instructions from an instruction set. The instruction set includes exception instructions and non-exception instructions. Exception instructions may cause a break in an instruction flow, and non-exception instructions execute in a statically determinable way. At least two processing blocks process instructions from the stream of instructions. A first processing block has a set of physical registers associated with it for storing data values being processed by the first processing block. Renaming circuitry associated with the first processing block maps architectural registers specified in instructions to be processed by the first processing block to physical registers within the set of physical registers. A second processing block has a set of physical registers associated with it for storing data values being processed by the second processing block. The second processing block and registers do not support renaming.

Abstract: A processor, system, and method are disclosed. In an embodiment, the processor includes a first site and a second site. There is a link to transmit a voltage stabilization signal from the second site to the first site. In the first site voltage correction logic can dynamically modify a voltage supplied to the first site and second site. In the second site there is logic to assert the voltage stabilization signal. After asserting the voltage stabilization signal, the second site is granted at least a window of time in which the supplied voltage to the second site does not change.

Abstract: Systems, methods, and apparatuses including computer program products for speculative throughput computing are disclosed. Speculative throughput computing is used to execute program segments in parallel.

Abstract: One embodiment of the invention is a method for resetting a partition of a multiple partition system, wherein the partition comprises a plurality of processors, the method comprising executing, by one processor of the plurality of processors, reset code from firmware, building a list of reset register addresses associated with the plurality of processors, sending an interrupt to the other processors of the plurality of processors, resetting the other processors by writing a reset code to their associated reset registers, and resetting the one processor by writing to its associated reset register.

Abstract: A method of multi-user detection in a given uplink and downlink time slot in a software-defined receiver which includes filtering and sampling a received signal; forming a block-banded matrix A of the sampled signals; and solving {circumflex over (d)}=T?1y, where T=(AHA), y=AHx. The methods of solving for the matrix T includes a) computing Cholesky factors of the matrix T by approximating using the block-banded property of the matrix T and A; b) Schur decomposition for Cholesky factors of the matrix T and approximating the lower triangular Cholesky factor matrix R using block Toeplitz property of matrix T; or c) Fourier Transformation.

Abstract: A reconfigurable context-based operation instruction set processor for use in a processing system capable of executing a first instruction set. The reconfigurable context-based operation instruction set processor comprises: 1) a reconfigurable data path comprising a plurality of reconfigurable functional blocks; and 2) a programmable finite state machine capable of controlling the reconfigurable data path. The programmable finite state machine is capable of executing a first plurality of context-related instructions that are a first subset of the first instruction set.

Abstract: A scalable and fully configurable computing architecture for a mobile multimedia architecture used in a vehicle includes a head unit having a processor, a field programmable gate array and a memory. The processor and the memory are configured to communicate over a first bus that is a dedicated memory bus, and the processor and the field programmable gate array are configured to communicate over a separate second bus. The field programmable gate array is configured to be loaded from memory with part of a multimedia vehicle-related application-specific functionality that is executable by the field programmable gate array, and the processor is cooperatively operable with the field programmable gate array to execute another portion of the multimedia vehicle-related application-specific functionality. The multimedia vehicle-related application-specific functionality in the field programmable gate array may be changed with software and downloaded to the field programmable gate array in the field.

Abstract: An image processing device including a storage section, a parallel processing controller, a sequential processing controller, and a selection section which selectively operates the two control sections. The parallel processing controller connects one or more of the image processing modules such that first buffer modules are connected at least one of preceding and following each image processing module, to formulate a first image processing section, and controls such that individual image processing modules perform image processing in parallel with one another. The first buffer modules perform exclusive access control. The sequential processing controller connects one or more of the image processing modules such that second buffer modules are connected at least one of preceding and following each image processing module, to formulate a second image processing section, and controls such that the individual image processing modules perform image processing sequentially.

Abstract: A method and system for using processor compatibility information to select a compatible processor for addition to a multiprocessor computer. A software program is executed on the multiprocessor computer to determine the number of current processors in the multiprocessor computer and the revision number of each processor. A software program that compares the revision numbers of the current processors with processor compatibility information is then executed to determine the revision numbers of processors that are compatible with all current processors.

Abstract: In the operation of a mobile device (such as a cellular telephone or a PDA, i.e. Personal Digital Assistant), which mobile device includes a mobile terminal and a memory module, certain operational signals of the mobile device are multiplexed and demultiplexed, resulting in efficient device bus utilization and reduced device pin count.

Abstract: A computer implemented method, data processing system, and computer program product for dynamically scheduling algorithms in a pipeline which operate on a stream of data. The illustrative embodiments determine a computational cost of each algorithm in a plurality of algorithms in a pipeline. The plurality of algorithms in the pipeline processes an incoming data stream in a first sequential algorithm order. The illustrative embodiments reorder the plurality of algorithms in the pipeline to form a second sequential algorithm order based on the computational cost of each algorithm. The plurality of algorithms may then be executed in the second sequential algorithm order. When the illustrative embodiments assign a spare processing unit to an algorithm at an end of the pipeline, the computational cost of each algorithm in the plurality of algorithms in the pipeline is redetermined.

Abstract: An embodiment involves throttling a bus frequency based upon incoming arbitration requests from units or devices coupled to a bus. Arbitration circuitry monitors request rates from each requestor and increases or decreases the bus frequency in order to meet the bandwidth levels requested. When the bandwidth requirements increase, the bus frequency increases. When the bandwidth requirements are reduced, the bus frequency is reduced to reduce power consumption. No software intervention is required to adjust the bus bandwidth.

Abstract: An AC generator has a first terminal coupled through an Isolation Loss Detect (ILD) capacitor to the positive bus of a Power-Over-Ethernet (POE) system, and has a second terminal coupled through the primary of a transformer to earth ground. AC current flowing between ground and the positive bus causes a corresponding AC voltage across the secondary of this transformer. The secondary of the transformer is coupled to an AC detector, whose output is coupled to a comparator. The threshold of the comparator is set such that when AC current through the ILD capacitor exceeds a threshold value, an ISOLATION FAULT output is generated by the comparator.