Power Conservation Patents (Class 713/320)
  • Patent number: 11256316
    Abstract: Methods, apparatus, and processor-readable storage media for automated device power conservation using machine learning techniques are provided herein. An example computer-implemented method includes obtaining usage-related data from one or more processing devices; determining at least one usage pattern for the one or more processing devices by processing the obtained usage-related data using one or more machine learning techniques; automatically generating, based at least in part on the at least one determined usage pattern, instructions pertaining to controlling one or more power states of the one or more processing devices; and performing at least one automated action based at least in part on the generated instructions.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: February 22, 2022
    Assignee: Dell Products, L.P.
    Inventors: Tamilarasan Janakiraman, Sreeram Muthuraman, Balamurugan Gnanasambandam, Charu Lata Ojha, Santosh Kumar Sahu, Vaishnavi Suchindran
  • Patent number: 11256441
    Abstract: Provided is a semiconductor system. The semiconductor system includes a universal flash storage (UFS) host, including a host controller interface, a UniPro and a M-PHY; a UFS device configured to exchange data with the UFS host through a UFS interface; and an application processor configured to control the UFS host. The UFS device is configured to maintain a power-on status when the application processor operates in a suspend mode.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: February 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyun-Seung Seo
  • Patent number: 11249649
    Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: February 15, 2022
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely Tsern
  • Patent number: 11249766
    Abstract: An instruction set architecture including instructions for a processor and instructions for a coprocessor may include synchronizing instructions that may be used to begin and end instruction sequences that include coprocessor instructions (coprocessor sequences). If a terminating synchronizing instruction is followed by an initial synchronizing instruction and the pair are detected in the coprocessor concurrently, the coprocessor may suppress execution of the pair of instructions.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: February 15, 2022
    Assignee: Apple Inc.
    Inventors: Aditya Kesiraju, Rajdeep L. Bhuyar, Ran A. Chachick, Andrew J. Beaumont-Smith
  • Patent number: 11249538
    Abstract: The present application teaches methods and apparatuses related to providing dynamic auxiliary port power management including providing a first current to a first auxiliary port and a second current to a second auxiliary port, determining a system power level in response to the first current and the second current, comparing the system power level to a system power level threshold, and providing a third current to the second auxiliary port in response to the system power level exceeding the system power level threshold, the third current having a lower amperage than the second current.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: February 15, 2022
    Assignee: Gulfstream Aerospace Corporation
    Inventors: Matthew Wallace, Dean Knight, Kristin Medin
  • Patent number: 11249540
    Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes: may determine a first amount of power consumed by a processor of an information handling system; may configure power consumed by the processor to a second amount of power, lower than the first amount of power; may determine a first performance value based at least on a first change of frames per second and a first change of temperature; may determine a second performance value based at least on a second change of frames per second and a second change of temperature; may determine that the second performance value is greater than the first performance value; may configure power consumed by the processor to the second amount of power; and may configure power consumed by the a graphics processing unit of the information handling system to a third amount of power.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: February 15, 2022
    Assignee: Dell Products L.P.
    Inventors: Qinghong He, Travis Christian North
  • Patent number: 11251989
    Abstract: A vehicle network system is disclosed. The vehicle network system includes a first controller area network (CAN) bus including a first node and a first secure transceiver and a second CAN bus including a second node and a second secure transceiver, a gateway to enable transmission of a CAN message from the first node to the second node. The vehicle network system also includes an auxiliary communication link to transmit an auxiliary data derived from the CAN message from the first secure transceiver to the second secure transceiver.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: February 15, 2022
    Assignee: NXP B.V.
    Inventor: Thierry G. C. Walrant
  • Patent number: 11243768
    Abstract: Disclosed embodiments relate to processing logic for performing function operations. In one example, and apparatus includes an execution unit within a processor to execute a code block, power management hardware coupled to the execution unit, wherein the power management hardware is to monitor a first execution of the code block, store a micro-architectural context of the processor in a metadata block associated with the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters, read the associated metadata block upon a second execution of the code block, and tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: February 8, 2022
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Eliezer Weissmann, Boris Ginzburg, Alon Naveh, Nadav Shulman, Ronny Ronen
  • Patent number: 11239885
    Abstract: A near field communication (NFC) transceiver includes a receiver, a transmitter, and a clock recovery circuit. The receiver is configured to recover a reception (RX) frame encoded with power supply information and information transmitted from a reader to a tag. The transmitter is configured to recover a transmission (TX) frame by a subcarrier load modulation scheme for information transmitted from the tag to the reader. The clock recovery circuit is configured to recover a carrier signal of the TX frame as a baseband clock signal of the NFC transceiver through a rail-to-rail boosting.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: February 1, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong Joong Kim, Joonseong Kang
  • Patent number: 11237617
    Abstract: Devices and techniques for arbitrating operation of memory devices in a managed NAND memory system to conform the operation to a power budget. In an example, a method can include receiving an operation change indication for a NAND memory operation at power management circuitry of a NAND memory system, and summing a power credit to a value of a first register associated with the operation change indication to provide an indication of instantaneous power consumption of the NAND memory system as the value of the first register.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventor: David Aaron Palmer
  • Patent number: 11237615
    Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: February 1, 2022
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Efraim Rotem, Nir Rosenzweig, Krishnakanth V. Sistla, Ashish V. Choubal, Ankush Varma
  • Patent number: 11231769
    Abstract: Methods, Apparatus, and Systems are discussed for a sequencer-based protocol adapter that executes a limited instruction set. The sequencer-based protocol adapter is implemented in electronic hardware and programmable registers in an integrated circuit and configured to transition a set of 1) one or more voltage sources, 2) one or more frequency sources, or 3) a combination of voltage sources and frequency sources, coupled with that sequencer-based protocol adapter. The sequencer-based protocol adapter manages power on the integrated circuit, via receiving a desired performance index at an input and then executing one or more of the limited instructions stored in the programmable registers in a proper sequence of steps in order to transition the coupled voltage sources and/or frequency sources from a current operational state to a desired operational state. Note, the desired operational state the coupled voltage sources and/or frequency sources corresponds to the received desired performance index.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: January 25, 2022
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventors: Gregory Ehmann, Drew E. Wingard
  • Patent number: 11233893
    Abstract: A communication device may have multiple units for communicating through multiple channels. The communication device may also include a display for displaying various screens. The communication device may display a function settings screen for selecting a communication unit to be used for communication with an external device. The communication device may determine whether an external device is already specified. The communication device may also display a device search screen identifying one or more external devices that can communicate with a particular communication unit of the communication device. Further, the communication device may display an updated function settings screen that indicates which communication unit is set to be used for communication with an external device and that identifies which external device is to receive communications from such communication unit.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: January 25, 2022
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Norihiko Asai
  • Patent number: 11221857
    Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem, Krishnakanth V. Sistla, Eliezer Weissmann
  • Patent number: 11221658
    Abstract: A multi-port power delivery system includes a first universal serial bus (USB) port, a second USB port, a first power conversion unit, a second power conversion unit, a power delivery control circuit and a switch circuit. The first USB port is configured to output power delivered to a first power path. The second USB port is configured to output power delivered to a second power path. The first power conversion unit has a first output terminal coupled to the first power path. The second power conversion unit has a second output terminal coupled to the second power path. The power delivery control circuit generates a switch control signal according to first connection information on the first USB port and second connection information on the second USB port. The switch circuit selectively couples the first output terminal to the second output terminal according to the switch control signal.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: January 11, 2022
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN), LTD.
    Inventors: Pao-Yao Yeh, Yu-Ming Chen, Jung-Pei Cheng, Hsiang-Chung Chang
  • Patent number: 11209890
    Abstract: A method includes sensing, with a sensor, a distance of a user from a display of a computing device. The method further includes comparing, with the computing device, the sensed distance to a threshold distance, and determining, with the computing device, whether the user is present at the display based at least in part on the comparison.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: December 28, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Syed S Azam, Wen Shih Chen, Christopher C Mohrman
  • Patent number: 11206199
    Abstract: A highly scalable distributed connection interface for data capture from multiple network service sources, comprising a connector module wherein, the connector module retrieves a plurality of operational data from a plurality of network data sources; employs a plurality of application programming interface routines to communicate with the plurality of operational data sources; accepts a plurality of analysis parameters and control commands directly from human interface devices or from one or more command and control storage devices; and specifies the action or actions to be taken on the retrieved operational data.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: December 21, 2021
    Assignee: QOMPLX, INC.
    Inventors: Jason Crabtree, Andrew Sellers
  • Patent number: 11197136
    Abstract: Apparatuses, systems, and methods related to accessing a memory resource at one or more physically remote entities are described. A system accessing a memory resource at one or more physically remote entities may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: December 7, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Aaron P. Boehm
  • Patent number: 11196291
    Abstract: The present invention is related to a hardware developed for allowing the virtualization of power and therefore bringing change to the data center market. This new concept, unique in the industry, offers the missing link to respond to the multiple and contradictory challenges the industry will be facing in managing power. The concept of a rack mounted power pack sized for average loads, is allowing peak shaving, and microgrid utilization. The combination of renewable power sources and grid connections enables cost savings while increasing the resilience of the overall infrastructure. The so-called “Power Fusion” operates like a decentralized double conversion UPS with all the advantages of centralized architecture.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: December 7, 2021
    Assignee: CE+T Power Luxembourg SA
    Inventors: Daniel Rixhon, François Milstein, Thierry Joannes, Paul Bleus
  • Patent number: 11196287
    Abstract: A real-time clock module includes a switch circuit that is electrically coupled to a first node to which a first power supply voltage is applied and a second node to which a second power supply voltage is applied and switches between outputting the first power supply voltage and outputting the second power supply voltage, a power supply detection circuit that detects a voltage value of the first power supply voltage, a switch control circuit that controls the switching of the switch circuit based on an output of the power supply detection circuit, a constant voltage circuit that outputs a constant voltage signal based on the output of the switch circuit, and a current control circuit that controls a current supplied to the constant voltage circuit, in which, when where the switch control circuit switches the switch circuit, the current control circuit increases the current supplied to the constant voltage circuit.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: December 7, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Sho Matsuzaki
  • Patent number: 11181967
    Abstract: A system includes a plurality of cores. Each core includes a processing unit, an on-chip memory (OCM), and an idle detector unit. Data is received and stored in the OCM. Instructions are received to process data in the OCM. The core enters an idle mode if the idle detector unit detects that the core has been idle for a first number of clocking signals. The core receives a command to process when in idle mode and transitions from the idle mode to an operational mode. A number of no operation (No-Op) commands is inserted for each time segment. A No-Op command prevents the core from processing instructions for a certain number of clocking signals. A number of No-Op commands inserted for a first time segment is greater than a number of No-Op commands inserted for a last time segment. After the last time segment no No-Op command is inserted.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: November 23, 2021
    Assignee: Marvell Asia Pte Ltd
    Inventors: Chia-Hsin Chen, Avinash Sodani, Atul Bhattarai, Srinivas Sripada
  • Patent number: 11177674
    Abstract: A communication apparatus (1), such as a mobile phone, a tablet computer or a laptop computer, provides charging reminders to the user of a connected peripheral device (14), such as a headset. The charging reminders are provided in dependence on an auxiliary status signal (AS) received from the peripheral device (14) and on detected charging events (ME), wherein a main charging event (ME) comprises a charging or replacement of a main battery (2) that energizes the communication apparatus (1). The auxiliary status signal (AS) indicates an auxiliary energy level (AL) of an auxiliary battery (15) of the peripheral device (14). The communication apparatus (1) detects low-battery conditions (LC), based on the indicated auxiliary energy level (AL), and provides notification signals (NS) for a user interface (11) to notify the user of the detected low-battery conditions (LC) in response to the detected main charging events (ME).
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: November 16, 2021
    Assignee: GN AUDIO A/S
    Inventor: Lars Ivar Hauschultz
  • Patent number: 11176034
    Abstract: A method, computer program product, and computer system for receiving, by a computing device, new data to write to a leaf. At least two timestamps of the leaf may be examined. It may be determined whether a time interval between the at least two timestamps of the leaf is greater than an age threshold. The new data may be written to a first tier storage device when the time interval between the at least two timestamps of the leaf is less than the age threshold; The new data may be written to a second tier storage device when the time interval between the at least two timestamps of the leaf is greater than the age threshold.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: November 16, 2021
    Assignee: EMC IP HOLDING COMPANY, LLC
    Inventors: Vamsi K. Vankamamidi, Philippe Armangau, Anton Kucherov
  • Patent number: 11175940
    Abstract: Managing execution of a job in a computing environment. A method establishes, for a job to be executed in the computing environment, an execution plan for processing the job. The execution plan identifies computationally intensive tasks of the job and data intensive tasks of the job. The method selects a virtual machine of the computing environment to process the identified computationally intensive tasks of the job and identified data intensive tasks of the job. The method assigns the identified computationally intensive tasks of the job for foreground processing of the virtual machine and assigns the identified data intensive tasks of the job for background processing of the virtual machine. Execution of the job executes the identified computationally intensive tasks of the job in foreground processing of the virtual machine and executes the identified data intensive tasks of the job in background processing of the virtual machine.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gopal K. Bhageria, Rajesh K. Saxena, Vikram Yadav
  • Patent number: 11172450
    Abstract: Various embodiments of the present disclosure relate to an electronic device including an environment sensor and a method for controlling an operation thereof. The electronic device may comprise: at least one environment sensor; and at least one processor functionally coupled to the at least one environment sensor and configured to control the at least one environment sensor to collect environment information at designated intervals, to recognize presence or absence of a user based on the collected environment information, and to control an operation of the electronic device according to the presence or absence of the user. Other various embodiments are possible.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: November 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taehan Lee, Sunggun Bae, Sangil Park, Hyun-Cheol Park, Ikjoo Byun
  • Patent number: 11171847
    Abstract: A highly scalable distributed connection interface for data capture from multiple network service sources, comprising a connector module wherein, the connector module retrieves a plurality of data from a plurality of network data sources; employs a plurality of application programming interface routines to communicate with the plurality of data sources; accepts a plurality of analysis parameters and control commands directly from human interface devices or from one or more command and control storage devices; and specifies the action or actions to be taken on the retrieved data.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: November 9, 2021
    Assignee: QOMPLX, Inc.
    Inventors: Jason Crabtree, Andrew Sellers
  • Patent number: 11169850
    Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: November 9, 2021
    Assignee: INTEL CORPORATION
    Inventors: Abhishek R Appu, Altug Koker, Balaji Vembu, Joydeep Ray, Kamal Sinha, Prasoonkumar Surti, Kiran C. Veernapu, Subramaniam Maiyuran, Sanjeev S. Jahagirdar, Eric J. Asperheim, Guei-Yuan Lueh, David Puffer, Wenyin Fu, Nikos Kaburlasos, Bhushan M. Borole, Josh B. Mastronarde, Linda L. Hurd, Travis T. Schluessler, Tomasz Janczak, Abhishek Venkatesh, Kai Xiao, Slawomir Grajewski
  • Patent number: 11163351
    Abstract: A device for power estimation is disclosed. The device includes a transformer circuit coupled with a processing circuit and a transaction interface. The transformer circuit is configured to count performance activities executed in the processing circuit and to compare count values of the performance activities with a predetermined value to determine a power state of the processing circuit. The transaction interface is configured to receive a request from the processing circuit and record a first timestamp, and further configured to receive a response from a memory model and record a second timestamp, the transaction interface being further configured to record a time difference between the first timestamp and the second timestamp as a time difference. The transformer circuit is further configured to determine the power state of the processing circuit based on both of the count values and the time difference.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: November 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Yuan Ting, Shereef Shehata, Tze-Chiang Huang, Sandeep Kumar Goel, Mei Wong, Yun-Han Lee
  • Patent number: 11157056
    Abstract: A system includes a power distribution unit and power manager circuitry. The power manager circuitry to receive a first load profile of a first information handling system, a second load profile of a second information handling system, and a third load profile of a third information handling system. The load profiles are based on power telemetry of the associated server. The power manager circuitry creates an aggregate load profile based on the first, second, and third load profiles, and determines whether the aggregate load profile exceeds a maximum load of the power distribution unit. If the aggregate load profile exceeds the maximum load of the power distribution unit, the power manager circuitry provides an optimal set of power recovery delays for a first, second, and third information handling system and also provides a power supply load limit exceeded warning message.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: October 26, 2021
    Assignee: Dell Products L.P.
    Inventors: John Erven Jenne, Kyle E. Cross
  • Patent number: 11160018
    Abstract: An electronic device (such as an access point) may provide a management frame, intended for at least a recipient electronic device, that includes slotted-operation information corresponding to a power-save mode of the electronic device for communication with at least the recipient electronic device. The slotted-operation information may include a sequence of temporal slots and associated channel information for the temporal slots. When a channel for a temporal slot comprises a null value, the power-save mode may include transitioning the electronic device into a lower-power-consumption mode during the temporal slot. Alternatively, when a channel for a temporal slot is different than a null value, the power-save mode may include performing another activity than communicating with the recipient electronic device during the temporal slot.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: October 26, 2021
    Assignee: Apple Inc.
    Inventors: Guoqing Li, Yong Liu, Lawrie Kurian, Tashbeeb Haque
  • Patent number: 11151140
    Abstract: Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of programmed state machines to enable selective activation and deactivation of the block during a pattern search. The block may be deactivated if the pattern search is no longer active in that block and activated when needed by the pattern search. Additionally, the block may be deactivated based on an identifier of the data stream being searched. Excess blocks not used for any programmed state machines may be disabled such that they are not refreshed during a memory cycle.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, David R. Brown
  • Patent number: 11151952
    Abstract: Provided is a liquid crystal display or the like that is able to achieve prevention of or recovery from an image sticking phenomenon in the liquid crystal display, while ensuring convenience for an operator of the liquid crystal display. The liquid crystal display includes a liquid crystal panel that displays an image, and a display control unit that controls display of a predetermined image to respond to image sticking on the liquid crystal panel. The liquid crystal display includes a selection receiving unit that receives a selection of a display mode from among a plurality of display modes in which the predetermined image is displayed, and the display control unit controls the display of the predetermined image in accordance with the display mode selected at the selection receiving unit.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: October 19, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Osamu Koshimizu, Yoshitaka Matsui
  • Patent number: 11153455
    Abstract: A CPU of an information processing apparatus (MFP) obtains device information regarding a secondary storage device provided in the MFP, and discriminates, based on the obtained device information, whether the secondary storage device is a type of storage device in which the number of shifts to a power saving state affects the lifetime of the storage device. The CPU determines, as a shift condition for the secondary storage device to shift to the power saving state, a shift time for the secondary storage device to shift to the power saving state, by determining the shift time for the type of storage device in which the number of shifts does not affect the lifetime to be shorter than the shift time for the type of storage device in which the number of shifts affects the lifetime.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: October 19, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Takaaki Miyata
  • Patent number: 11150718
    Abstract: Methods, systems, and computer programs for identifying, by an operating system, a power consumption level associated with a platform configuration of the information handling system; identifying, by the operating system, a bandwidth associated with a flash memory medium of the information handling system; identifying a first battery charge level associated with a battery of the information handling system, the battery in a charging state; determining a first cache size based on the power consumption level associated with the platform configuration, the bandwidth associated with the flash memory medium, and the first battery charge level associated with the battery; and enabling a first portion of the cache memory based on the determined first cache size.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: October 19, 2021
    Assignee: Dell Products L.P.
    Inventors: Xu Chen, Michael Sean Gregoire, Qiu Lin Cheng, Qi Liu
  • Patent number: 11144366
    Abstract: A computing node processor resource optimization method, a computing node, and a server cluster are provided. A standard processor computing power is used as a reference to acquire a relative computing power of a processor in the computing node. Based on the relative computing power, a relative computing resource of the computing node is determined. The relative computing resource of the processor in each computing node is acquired based on a uniform reference. The computing power in the computing nodes having the same number of the processor cores multiplied by the number of the threads per processor core may be distinguished, such that the task load distributed to each computing node can match the computing power of the computing node. Thus, the computing resource of the processor in each computing node may be fully utilized, thereby improving the computing efficiency of the big data computing platform.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: October 12, 2021
    Assignee: LENOVO (BEIJING) LIMITED
    Inventor: Dong Li
  • Patent number: 11140243
    Abstract: The systems and methods monitor thermal states associated with a device. The systems and methods set thermal thresholds associated with the device. The systems and methods infer the thermal thresholds from information gathered by a client application running on the device. The systems and methods implement a stored policy associated with a violation of one of the thermal thresholds by one of the monitored thermal states.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: October 5, 2021
    Assignee: Snap Inc.
    Inventors: Michael Cieslak, Michael David Marr
  • Patent number: 11125790
    Abstract: In an embodiment a method for operating a power consumption metering system includes measuring, by a sensor deployed at a monitored site, power consumption values over time to obtain a high speed value pattern of a power consumption with a resolution of more than 1000 values per second, measuring, by the sensor, low speed power consumption values over time to obtain a low speed value pattern of the power consumption with a resolution of less than 100 values per second, identifying a status of a power consumer of the monitored site dependent on the high speed value pattern and counting an operation time of the power consumer dependent on the low speed value pattern and on the identified status.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: September 21, 2021
    Assignee: ENERGYBOX LTD.
    Inventor: Dirk Beiner
  • Patent number: 11127328
    Abstract: The embodiments of the present disclosure provides a bar screen control circuitry, a bar screen display system and the method for controlling the bar screen. The bar screen control circuitry comprises a power supply control circuitry and a processor electrically connected with each other; the power control circuitry is configured to: determine whether a current time reaches a preset starting time, and control a bar screen external to the bar screen control circuitry to enter a first working state when the current time reaches the preset starting time; obtain a closing control signal sent by the processor in response to a preset closing time, and control the bar screen to enter a closed state according to the closing control signal; and the processor is configured to: determine whether the current time reaches the closing time, and send the closing control signal to the power supply control circuitry when the current time reaches the closing time.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 21, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Hui Rao, Kejun Hu, Zhiguo Zhang, Xiaohong Wang, Xin Li, Shu Wang, Xinxin Yang
  • Patent number: 11121389
    Abstract: A method of cleaning power cells in an array of power cells, comprising coupling at least one first power cell to second power cells in an array of power cells and causing the second power cells to drive the at least one first power cell with a voltage to clean catalyst on the at least one first power cell.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: September 14, 2021
    Assignee: ENCITE LLC
    Inventors: Stephen A. Marsh, Lawrence W. Hill
  • Patent number: 11119562
    Abstract: A method comprises receiving, by a computing device, a desired usage plan for a plurality of user devices associated with a group of users; determining, by the computing device, whether an amount of power available across the plurality of user devices is sufficient to implement the desired usage plan; generating, by the computing device and based on the amount of power available across the plurality of user devices for the desired usage rules, usage rules that allocate the usage of the plurality of the user devices by each user in the group of users; and outputting to the plurality of user devices, the usage rules to cause the plurality of user devices to limit the usage of the plurality of user devices by each user in the group of users based on the allocation.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: September 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James E. Bostick, John M. Ganci, Jr., Martin G. Keen, Sarbajit K. Rakshit
  • Patent number: 11119555
    Abstract: In one embodiment, a processor includes a plurality of cores and a power controller. This power controller in turn may include a voltage ramp logic to pre-empt a voltage ramp of a voltage regulator from a first voltage to a second voltage, responsive to a request for a second core to exit a low power state. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: September 14, 2021
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Jeremy J. Shrall, Anupama Suryanarayanan, Ameya Ambardekar, Craig Topper, Eric R. Heit, Joseph M. Alberts
  • Patent number: 11112853
    Abstract: Methods and apparatus relating to Priority Based Application Event Control (PAEC) to reduce application events are described. In one embodiment, PAEC may determine which applications (and their corresponding sub-system(s)) may cause a processor or platform to exit a low power consumption state. In an embodiment, PAEC may determine which applications (and their corresponding sub-system(s)) may resume operations after a processor or platform exit a low power consumption state. Other embodiments are also claimed and disclosed.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: September 7, 2021
    Assignee: Intel Corporation
    Inventors: Rajesh Poornachandran, Rajeev Muralidhar
  • Patent number: 11112855
    Abstract: An electronic device comprises a clock request pad, a multiplexer and a control circuit. The clock request pad is arranged to refer to a first control signal to operate under a low voltage level or a high voltage level, to indicate whether the electronic device needs a clock signal generated from a clock generation circuit external to the electronic device. Said multiplexer is arranged to refer to a second control signal to output one of a voltage level of the clock request pad and a predetermined voltage level to function as a multiplexer output signal. The control circuit is coupled to said multiplexer, and refers to said multiplexer output signal to determine whether to control the electronic device to operate in a power-saving mode.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: September 7, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Kuo-Cyuan Kuo, Chih-Chiang Chen, I-Ta Chen
  • Patent number: 11115076
    Abstract: A transceiver assembly includes a radio frequency (RF) transceiver configured to transmit and receive signals, and a transceiver controller operatively coupled with the transceiver via a transmit path and a receive path. A power amplifier disposed along the transmit path is configured to amplify RF signals for transmission by the transceiver. A power detection line is configured to provide power control feedback to the transceiver controller indicating an amplitude of current flowing from the power amplifier to the transceiver. A directionally-specific protection element disposed along the power detection line is configured to allow the power control feedback to flow to the transceiver controller over the power detection line in a first direction, while preventing at least some electrical noise originating from the transceiver controller from flowing through the power detection line in a second direction, thereby preventing the electrical noise from entering the receive path.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: September 7, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Siamak Varnamkhasti
  • Patent number: 11106474
    Abstract: Aspects of the embodiments include systems, methods, devices, and computer program products to receive, from the downstream component, an indication of an extended capability; determining, from the indication, one or more configuration parameters for the downstream component; applying the one or more configuration parameters; and performing data signal or control signal transmissions across the PCIe-compliant link with the downstream component based, at least in part, on the applied one or more configuration parameters. The extended capabilities can be indicated by a DVSEC extended capability definition received from a downstream device. The extended capabilities of the downstream component can indicate the number of buses, the port type, the expandability capability, the D3Cold support status, the host router indicator, and/or the safe eject requirements of the downstream component.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Vinay Raghav, Reuven Rozic, David J. Harriman
  • Patent number: 11099803
    Abstract: Provided is a method of providing information through a mobile device, in which an information providing screen is outputted only during the first activation performed within a predetermined time range designated by a user. Therefore, inconvenience resulting from repetitive outputs of the information providing screen can be resolved.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: August 24, 2021
    Inventors: Jaekyu Lee, Jaelark Jung, Jaeyong Jang
  • Patent number: 11099620
    Abstract: A fail-safe power limit (FSPL) can be applied to components that lose communication with a management module (MM) to determine a safe power level at which to operate. The FSPL may be computed by the management module (MM) for the information handling system and distributed to components in the information handling system. By computing a FSPL and transmitting the FSPL to the components, a larger amount of the available power can be used by the components. This allows the components to continue operating at performance levels closer to or equivalent to levels available when the management module (MM) is operating normally. The FSPL may be updated at set times and/or on a periodic schedule such that the FSPL used by the components when communication is lost with the management module (MM) reflects a recent operating state of the components.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: August 24, 2021
    Assignee: Dell Products L.P.
    Inventors: Douglas E. Messick, Kyle Eric Cross, Dan Rao, Shawn Joel Dube
  • Patent number: 11093013
    Abstract: Methods and systems for managing power for a Power over Ethernet (PoE) device are disclosed herein. The method may include obtaining, by a supervisor, power information from a plurality of power supply units (PSUs) to obtain total power consumption information; obtaining, by the supervisor, a total system power capacity value for the plurality of PSUs; and making a determination, by the supervisor, using the total power consumption information, and the total system power capacity value, whether a powered device should stop receiving power.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: August 17, 2021
    Assignee: ARISTA NETWORKS, INC.
    Inventors: Eric Jahfei Won Yam, Robert Calvin Cyphers, Charles Melvin Aden, Eudean Michael Sun, Dipankar Bhatt Acharya
  • Patent number: 11093015
    Abstract: An imaging apparatus to which an accessory apparatus is detachably and communicatively attachable. The imaging apparatus comprises a power supply unit configured to supply a power to the accessory apparatus; a camera control unit configured to control the power supply unit; and a camera communication unit configured to communicate with the accessory apparatus, wherein the camera communication unit receives, from the accessory apparatus, one or more settable power modes settable to the accessory apparatus and transmits, to the accessory apparatus, a request power mode corresponding to a power that the power supply unit can supply to the accessory apparatus, and wherein when one of the settable power modes corresponds to the request power mode, the power supply unit supplies the power corresponding to the request power mode.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: August 17, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Tomoaki Yamanaka
  • Patent number: 11089331
    Abstract: Methods and devices for encoding a point cloud. A bit sequence signaling an occupancy pattern for sub-volumes of a volume is coded. Predictive coding is used to find a set of predicted points, from which a corresponding predicted occupancy pattern may be determined. The predicted occupancy pattern may be used to determine the contexts for entropy coding the occupancy pattern. The determination may include determining for each sub-volume, whether it contains a predicted point or not and, in some cases, the count of predicted points within the sub-volume. Various threshold numbers of predicted points may cause the selection of different context sets for coding the occupancy pattern. The predictive coding may be enabled by determining that the prediction of occupancy of a parent volume to the volume met a threshold level of accuracy.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: August 10, 2021
    Assignee: BlackBerry Limited
    Inventors: Sébastien Lasserre, David Flynn