Abstract: A power source is configured to supply power to one or more components of an electronic device. A processing device that is in communication with the power source can be configured to determine an estimated power requirement of the mobile electronic device during a time period, to determine a charge state of the power source, and to produce an indication of the remaining use time of the electronic device based on the estimated power requirement and the charge state of the power source.

Abstract: Aspects described herein relate to instructing, from a layer of a modem processor, a host processor to utilize an increased power consumption state for processing data from a network node. The instructing can be performed based on transmitting a signal to the network node and/or receiving signals from the network node, and at a time that allows the host processor to wake up before receiving data from the modem processor for processing.

Abstract: A method includes obtaining a first network wakeup parameter, where the first network wakeup parameter is used to wake up an application program. The method further includes performing reconfiguration processing on the first network wakeup parameter based on a preset first configuration condition to obtain a second network wakeup parameter. The method further includes configuring a driver of the terminal based on the second network wakeup parameter. The second network wakeup parameter is written into Wi-Fi firmware such that the Wi-Fi firmware directly performs processing without waking up the application program when the first network wakeup parameter is received next time.

Abstract: A non-volatile storage device comprises non-volatile memory cells, clocked circuity, and one or more control circuits. The one or more control circuits are configured to process commands to access the non-volatile memory cells using the clocked circuity, implement a power control loop to regulate power consumption of the non-volatile storage device based on a first feedback signal, implement a temperature control loop to regulate temperature of the non-volatile storage device based on a second feedback signal, and implement a clock frequency control loop to regulate one or more clock frequencies of the clocked circuitry based on a third feedback signal.

Abstract: In an example, a display device with power inputs includes a first power input to receive a first amount of input power, a second power input to receive a second amount of input power, a power allocator to combine at least a portion of the first amount of power with at least a portion of the second amount of power to form a combined output power, and a universal serial bus (USB) port to output at least a portion of the combined output power to a peripheral device.

Abstract: A method for performing programming management, associated memory device and a controller thereof are provided. The memory device may include a non-volatile (NV) memory, and the NV memory may include a plurality of NV memory elements. The method may include: before programming a target NV memory element of the plurality of NV memory elements, checking whether another NV memory element of the plurality of NV memory elements is in a busy state or in a non-busy state; and when the other NV memory element enters the non-busy state, programming the target NV memory element.

Abstract: An image forming apparatus capable of reducing execution time of a process for shifting the image forming apparatus from a normal operation mode to a low-power consumption operation mode. A sub interrupt controller 113 is connected to units and performs notification to a sub CPU in accordance with occurrence of a return trigger in any of the units. When shifting from the normal operation mode to the low-power consumption operation mode, a main CPU transmits mode instruction information indicative of the low-power consumption operation mode to the sub CPU. The sub CPU stores one or a plurality of units associated with the low-power consumption operation mode in advance, and sets one or a plurality of units in the sub interrupt controller, based on the mode instruction information and the plurality of units stored in association with the low-power consumption operation mode.

Abstract: One embodiment facilitates a storage system, which comprises a backplane and a plurality of storage medium cards coupled to the backplane. The backplane is coupled to a host via a first interface, and the backplane comprises global management circuitry coupled to a plurality of groups of components and configured to process an input/output (I/O) request and manage a mapping table. A respective group of components includes: first circuitry configured to perform first computing operations; and second circuitry configured to perform second computing operations. A respective storage medium card is allowed to operate without a controller residing on the storage medium card. Data associated with the I/O request is processed by the global management circuitry and further processed by first circuitry and second circuitry associated with a storage medium card selected for executing the I/O request.

Abstract: Devices, systems, and methods for storing and managing sensitive information in a connected environment are provided. The system comprises a master controller and a sensitive information storage device (“SIS device”). The SIS device has an island that can be activated by user interaction with the SIS device. In general, the island is deactivated by default and when the island is deactivated, sensitive information that is stored on the SIS device cannot be accessed. Only when the island is activated by user interaction can the stored sensitive information be accessed.

Abstract: Disclosed herein are methods, systems, and processes to perform granular and selective agent-based throttling of command executions. A polling interval of an agent process executing on a protected host is monitored. If the agent process is active and a current throttle is greater than a desired throttle, the agent process and its children processes are suspended and a run count flag is incremented. However, if the agent process is inactive and the current throttle is less than or equal to the desired throttle, the agent process and its children processes are resumed and a skip count flag is incremented.

Abstract: In an embodiment, a local throttling mechanism for the one or more processor cores may support one or more externally-triggered throttling mechanisms. An external source, such as a system-level power manager, may detect an energy-consumption state in the system as a whole and may trigger additional throttling in the processor core throttling mechanism. The externally-triggered throttling may temporarily increase throttling in the processor cores, in an embodiment, decreasing processor core energy consumption to account for the excess energy consumption in other parts of the system.

Abstract: The present disclosure includes apparatuses and methods updating a register in memory. An example includes an array of memory cells; and a controller coupled to the array of memory cells configured to perform logical operations on data stored in the array of memory cells using a register that is updated to access the data stored in the array of memory cells.

Abstract: The present invention achieves high speed safe response performance. A safety controller (100) includes a first voltage monitoring circuit (12) and a second voltage monitoring circuit (22). The first voltage monitoring circuit (12) is an AD converter which operates upon receiving electric power from a second electric power source (21) and which transmits, to a second MPU (20), a signal that gives notification of occurrence of an anomaly in a first voltage value. The second voltage monitoring circuit (22) is an AD converter which operates upon receiving electric power from a first electric power source (11) and which transmits, to a first MPU (10), a signal that gives notification of occurrence of an anomaly in a second voltage value.

Abstract: Methods, computer readable mediums, and systems for power management. The method of power management may include receiving first power supply unit (PSU) capacity data and first PSU consumption data from a first PSU to a supervisor; storing, via the supervisor, the first PSU capacity data and the first PSU consumption data in storage; receiving first controlled device power consumption data from a first controlled device to the supervisor; updating a priority table, stored in the storage, with the first controlled device power consumption data; making a first determination that the first PSU consumption data exceeds a first threshold, where, the first threshold is calculated based on at least the first PSU capacity data; and based on the first determination, initiating a power response procedure.

Abstract: An apparatus includes a plurality of processor cores, a cache memory that includes a plurality of banks, and a power management circuit. The power management circuit is configured to maintain a power credit approach for the apparatus that includes tracking a total number of currently available power credits, and to store a plurality of threshold values. Each threshold value is associated with one or more of a plurality of throttling actions. In response to the total number of currently available power credits reaching a particular threshold value of the plurality of threshold values, the power management circuit performs the one or more throttling actions associated with the particular threshold value. The plurality of throttling actions includes selectively throttling one or more of the plurality of processor cores, and selectively throttling one or more of the plurality of banks in the cache memory.

Abstract: A system loading detecting device and method are provided. The system loading detecting device includes a processing device, a detection circuit and a controller. The detection circuit detects whether an adapter is unplugged from the system loading detecting device to generate a detection signal. When the adapter is unplugged from the system loading detecting device, the detection signal is changed from a first level to a second level. The controller is coupled to the detection circuit and the processing device. In addition, the controller receives the detection signal and determines whether to trigger the generation of a throttling signal according to the detection signal to enable a throttling mechanism to reduce system loading.

Abstract: The disclosure relates to a method for providing hardware reset in an electronic device having at least one non-physical key and the electronic device thereof, and an operating method of the electronic device may include detecting a current amount supplied to a processor, detecting whether wireless power is input, generating a hardware reset signal based on the detected current amount and the wireless power input, and transmitting the generated hardware reset signal to the processor.

Abstract: Systems, apparatuses, and methods related to thermal leveling are described. Thermal leveling can be performed on a host computing system as opposed to on a memory system. Thermal leveling can include operations performed by a host to control temperature characteristics and/or power consumption of a memory system. For instance, a host computing system can control temperature characteristics of multiple memory devices that are deployed in a memory system. In an example, a set of processing resources (e.g., a thermal leveling component) can be provided on a host. The set of processing resources can receive information corresponding to thermal characteristics of a memory device coupled to the host and control a thermal setting for the memory device based on the received thermal characteristics.

Abstract: A method, electronic device, and computer-readable medium for displaying a user input. The method includes determining whether a writing utensil is within a predetermined proximity of the display panel while a display panel of the electronic device is powered off. The method also includes, in response to determining that a writing utensil is within the predetermined proximity, activating a black screen display mode for the display panel. Additionally, the method includes, in response to detecting the writing utensil contacting a surface of the electronic device, activating individual pixels corresponding to locations where the writing utensil contacted the electronic device to display a contrasting color.

Abstract: A control method of a storage device wherein a host cannot transfer a command to the storage device when the storage device transfers data to the host, after which there is a data transfer delay time period and no data is transferred to the host until a read command is received from the host, the control method comprising the steps of: detecting, by a memory controller of the storage device, a host delay time of the host each time a read command is received from the host during the data transfer delay time period; and adjusting, by the memory controller, the data transfer delay time period based on one or more of the detected host delay times.

Abstract: Techniques facilitating integrated circuit identification and reverse engineering are provided. A computer-implemented method can comprise identifying, by a system operatively coupled to a processor, an element within a first elementary cell of one or more elementary cells of an integrated circuit. The method can also comprise matching, by the system, the element with respective elements across the one or more elementary cells including the first elementary cell. The respective elements can be replicas of the element. Further, matching the element with respective elements can be based on a layout analysis of the integrated circuit.

Abstract: Systems, methods, and apparatus for adaptively modifying latency times governing entry of a PCIe interface into low power states are described. A method performed by a controller of a PCIe interface includes determining that a burst of data is being transmitted on a PCIe link, configuring a timer to signal when an entry latency period has elapsed after determining that a PCIe link has entered an idle state, causing one or more circuits of the PCIe interface to enter a low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active, and increasing the entry latency period when a number of entries of the PCIe interface to the low-power state that occurs during transmission of the burst of data exceeds a threshold maximum number.

Abstract: Technology for computing number of active servers needed over time in a cloud/compute cluster includes the following operations (not necessarily in the following order): (i) determining the capacity of each VCE provisioned on the cloud against the resource guaranteed to that VCE; (ii) forecasting the resource needs over time using historical requests for each VCE flavor; and (iii) using the forecasted resource needs to determine the required number of future servers at some future time. Some embodiments of the present invention use a formula that accounts for the interplay among various parameter values of the VCE flavors and also the mapping of the needs of VCEs of various flavors to the capabilities of physical resources.

Abstract: Technology for computing number of active servers needed over time in a cloud/compute cluster includes the following operations (not necessarily in the following order): (i) determining the capacity of each VCE provisioned on the cloud against the resource guaranteed to that VCE; (ii) forecasting the resource needs over time using historical requests for each VCE flavor; and (iii) using the forecasted resource needs to determine the required number of future servers at some future time. Some embodiments of the present invention use a formula that accounts for the interplay among various parameter values of the VCE flavors and also the mapping of the needs of VCEs of various flavors to the capabilities of physical resources.

Abstract: The described technology is generally directed towards maintaining a consistent logical data size with variable protection stripe size in an array of independent disks system. According to an embodiment, a system can comprise a processor that can execute computer executable components stored in a memory, and storage devices. The components can receive a configuration from another node of the redundant array of independent disks system based on a selected number of logical data blocks to configure disks, and configure, based on the selected number, the storage devices to store data in a number of stripes, with the logical data blocks mapping to the storage devices. The data can be stored in the storage devices, wherein parity information for a stripe of the number of stripes is stored for the stored data, and wherein a logical data block of the number of logical data blocks corresponds to the stored data.

Abstract: Techniques for analyzing code are described. In some instances, a code analysis service is to perform a series of comparisons, one or more per path segment of an index structure of non-defective code samples, using a token derived from a defective code segment of the stored code, to determine one or more paths in the index, wherein each path is to point to code that is similar to the defective code segment; and provide, in response to the series of comparisons, at least one of: a location of the code determined to be similar to the defective code segment and the code determined to be similar.

Abstract: Systems and methods for runtime update of battery coefficients are described. In an illustrative, non-limiting embodiments, an Information Handling System (IHS), may include: a processor; and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: receive a battery configuration policy from a remote server; and transmit at least a portion of the policy to a battery management unit (BMU) at runtime, where the policy comprises one or more battery coefficients.

Abstract: According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.

Abstract: A storage control system acquires, for each of a plurality of power control groups in which a plurality of storage devices which form the basis of a plurality of redundancy configuration groups are classified, an I/O (Input/Output) amount of the power control group. For each of the plurality of power control groups, the storage control system controls power consumption of each of the storage devices belonging to the power control group in power control group units, based on the acquired I/O amount relating to the power control group. None of the plurality of redundancy configuration groups spans two or more power control groups among the plurality of power control groups, all being contained in any of the plurality of power control groups.

Abstract: An electronic device includes a processor, a volatile memory, and a non-volatile memory. The non-volatile memory stores a first operating system, and the electronic device works in a first working mode and a second working mode. When the electronic device is in the first working mode, a second operating system is run in the volatile memory. When the processor detects that the electronic device reaches a preset condition for entering the second working mode, the non-volatile memory is enabled, and non-system data in the volatile memory is moved to the non-volatile memory. The non-system data does not include the second operating system. After the movement of the non-system data is completed, the volatile memory is disabled, and the first operating system is run in the non-volatile memory, so that the electronic device enters the second working mode.

Abstract: Thermal management in three dimensional integrated circuits can be difficult. Although three dimensional integrated circuits offer multiple benefits in alleviating back-end-of-the-line (BEOL) interconnect issues by reducing the wire length and reaping resistance-capacitance (RC) quadratic benefits, the thermal issues associated with stacking high performance (and subsequently high-power consumption) dice have so far proven to be prohibitive. Disclosed are methods and devices for efficient thermal management in multilayered ICs by determining thermally dangerous regions and selectively activating them to avoid undesirable temperature effects.

Abstract: A method tests the configuration of an aggregated DERs system using distributed asset managers in a decentralized hardware-in-the-loop (“HIL”) scheme. The managers contain the model of the asset they are meant to control. The method programs an asset manager with a model of a DERs asset. A plurality of asset managers are connected to a central controller. The plurality of asset managers are also connected to a simplified hardware-in-the-loop platform. The simplified HIL platform is configured to solve a network model, a load model, a non-controllable asset model, and a grid model. The method tests the DERs system control structure by using: (a) the simplified HIL platform to solve the network model, the load model, the non-controllable asset model, and the grid model, and (b) the asset manager to solve the model of the DERs asset, without any simulation between the central controller and the distributed asset managers.

Abstract: Described herein are methods and systems for connecting via a cable a USB host and USB device over distances equal to greater than 50 meters. The methods and systems include having the host and device each send a pilot signal over the cable and the host and device, each detecting that the received pilot signal is valid. After confirming the validity of the pilot signals, the host begins standard USB protocols with the device. The system and methods also allow for the insertion of a power over Ethernet device into the cable to provide power to a remote USB device. In some embodiments, only the D+ and D? lines are used allowing multiple independent USB connections over the cable.

Abstract: In one example, a printing device is disclosed, in which a network detection unit may discover available network interfaces associated with a client device upon detecting a printer network interface on which a print job is being received is down, a communication unit may send a link status notification to the client device via the available network interfaces associated with the client device, and a network switching unit may resume the print job using an alternate printer network interface that is accessible by the client device based on the link status notification.

Abstract: A system for setting a power cap state is disclosed. The system includes a plurality of power monitor sensors generating power monitor sensor data and a plurality of thermal monitor sensors generating thermal monitor sensor data. A controller has a plurality of inputs configured to receive the power monitor sensor data and the thermal monitor sensor data, to assign a priority to one of two or more power cap states and to generate a control signal. A power limiting circuit coupled to the controller is configured to receive the control signal and to modify one or more power settings.

Abstract: A processing system can include a plurality of processing clusters. Each processing cluster can include a plurality of processor cores and a last level cache. Each processor core can include one or more dedicated caches and a plurality of counters. The plurality of counters may be configured to count different types of cache fills. The plurality of counters may be configured to count different types of cache fills, including at least one counter configured to count total cache fills and at least one counter configured to count off-cluster cache fills. Off-cluster cache fills can include at least one of cross-cluster cache fills and cache fills from system memory. The processing system can further include one or more controllers configured to control performance of one or more of the clusters, the processor cores, the fabric, and the memory responsive to cache fill metrics derived from the plurality of counters.

Abstract: An operation management apparatus includes a processor. The processor generates a VM load model for each virtual machine running on an information processing system, generates resource utilization rate estimation data based on VM load models of a virtual machine group running on the physical machine and a VM load model of a first virtual machine, for each of physical machines except for a first physical machine on which the first virtual machine is running, generates a resource competition occurrence model based on the resource utilization rate of the physical machine, calculates a statistical value of competition occurrence probabilities of the resource, for each of the physical machines except for the first physical machine, based on the resource utilization rate estimation data and the resource competition occurrence model, specifies the migration destination physical machine based on the statistical value, and outputs information of a specified migration destination physical machine.

Abstract: A highly scalable distributed connection interface for data capture from multiple network service sources, comprising a connector module wherein, the connector module retrieves a plurality of business related data from a plurality of network data sources; employs a plurality of application programming interface routines to communicate with the plurality of business related data sources; accepts a plurality of analysis parameters and control commands directly from human interface devices or from one or more command and control storage devices; and specifies the action or actions to be taken on the retrieved business data.

Abstract: An electronic device monitors a volume of data processed by the electronic device within a first monitoring time segment, where a processor of the electronic device is configured to be in a first working mode, and the processor processes data in a poll mode driver (PMD) manner in the first working mode. The electronic device switches the processor from the first working mode to a second working mode when it is determined, according to the volume of data processed by the electronic device within the first monitoring time segment, that the processor is idle within the first monitoring time segment, where the processor processes data in the PMD manner and a sleep manner in the second working mode.

Abstract: A disclosed example includes: a temperature predictor to determine a combined ambient air temperature of a data center during a future duration based on 1) a first ambient air temperature corresponding to heat generated by hardware resources in physical server racks when executing workloads and 2) a second ambient air temperature corresponding to a building structure of the data center; a power utilization analyzer to determine a predicted total data center power utilization for the future duration based on a computing power utilization and a climate control power utilization, the climate control power utilization based on a power utilization corresponding to adjusting the combined ambient air temperature to satisfy an ambient air temperature threshold; and a power manager to configure a power supply station to deliver an amount of electrical power during the future duration to satisfy the predicted total data center power utilization.

Abstract: A method of supplying power in a power grid, a system supplying power in a power grid, a method of consolidating power injection and consumption in a power grid, a system for consolidating power injection and consumption in a power grid, a metering system for a power grid, and a metering method for a power grid. The method of supplying power in a power grid, the method comprises determining an initial forward probabilistic power supply time profile of an aggregate intermittent power source connected to the power grid; determining a target power demand time profile of at least one load connected to the power grid; and associating at least respective portions of the initial forward probabilistic power supply time profile and the target demand time profile such that a probability of supply of power from the intermittent power source to the load meets a specified criterion.

Abstract: A zero cross detection circuit has a first comparator circuit receiving a first input signal and a second input signal and outputting a first comparison result, a second comparator circuit having a hysteresis function, receiving the first input signal and the second input signal, and outputting a second comparison result, a power supply voltage detection circuit outputting a detection signal when a power supply voltage to be supplied becomes equal to or larger than a predetermined voltage, and a logic circuit outputting a zero cross detection signal based on the first comparison result, the second comparison result, and the detection signal.

Abstract: According to one embodiment, an image forming apparatus includes an image forming unit, a fixing unit, a reading unit, and a control unit. The image forming unit forms a visible image on a sheet. The fixing unit executes a fixing process of fixing the visible image on the sheet. The reading unit executes a reading process of reading an image. The control unit starts measurement of time until shift to a power saving mode, and shifts the operation mode to the power saving mode in which power consumption is suppressed when the measured time passes a predetermined set time. The control unit stops the measurement of the time during execution of printing, which is a process involving execution of the fixing process, and continues the measurement of the time during execution of the reading process without execution of the printing.

Abstract: An electronic device measures noise variability of background noise present in a sampled audio signal, and determines whether the measured noise variability is higher than a high threshold value or lower than a low threshold value. If the noise variability is determined to be higher than the high threshold value, the device categorizes the background noise as having a high degree of variability. If the noise variability is determined to be lower than the low threshold value, the device categorizes the background noise as having a low degree of variability. The high and low threshold values are between a high boundary point and a low boundary point. The high boundary point is based on an analysis of files including noises that exhibit a high degree of variability, and the low boundary point is based on an analysis of files including noises that exhibit a low degree of variability.

Abstract: A solid-state drive (SSD) includes a connector communicatively coupling the SSD to a host device, a controller coupled to the connector, and a memory device. The SSD also include a regulator configured to receive an instruction to enter a low power mode of the SSD, enter the low power mode upon receipt of the instruction, receive an indication to exit the low power mode, and exit the low power mode upon receipt of the indication.

Abstract: An asynchronous state machine (ASM) for managing deep sleep state of a device and related methods are described. One method includes the ASM automatically detecting a request to wake up the device based on either a change in a status of a power user-interface element associated with the device or upon a detection of an attachment of an external power source to the device. The method further includes the ASM automatically initiating a wake-up sequence including turning on a battery pack associated with the device. The method further includes the ASM automatically detecting whether a power management function associated with the device is enabled and automatically transferring control of a remaining portion of the wake-up sequence to the power management function and the ASM passing the status of the power user-interface element to the power management function as needed.

Abstract: In some examples, in a battery-powered computing device, a software monitor may access a calendar, determine that an event is occurring, determine that the event has an associated profile, and configure the computing device based on the profile to reduce a power consumption of the computing device. For example, one or more hardware components and one or more software components identified in the profile may be placed in a low power consumption state. For example, a hardware component may be transitioned from a power-on state to a low-power state power or may not be provided power. As another example, execution of a software component may be stopped or an execution priority of the software component may be modified from a first priority to a second priority that is lower than the first priority.

Abstract: According to one embodiment, an image forming apparatus having a plurality of operation modes including a normal mode and a power saving mode in which power consumption is less than that in the normal mode and includes a processor. The processor is configured to acquire information about unexecuted print jobs via a communication interface or the like. The processor transitions the apparatus to the power saving mode after a preset standby time elapses after a completion of a print job by the apparatus if an unexecuted print job satisfies predetermined conditions that indicate that the unexecuted print job can be executed on the apparatus. The processor transitions the apparatus to the power saving mode sooner than the elapse of the preset standby time after the completion of the print job if none of the unexecuted print jobs satisfies the predetermined conditions.

Abstract: A secure mobile device charger for charging batteries of mobile devices. The secure mobile charger can include one or more body housing battery charging elements; a power connector; a mobile device connector; a code receiver; and a switch that prevents unauthorized battery charging from the mobile device connector. The code receiver may receive a code transmitted from the power source in the form of a variation in the electrical power supplied by the power source, which may be used to provide authorization to enable battery charging from the mobile device connector.

Abstract: In one disclosed embodiment, a processor includes a first execution unit and a second execution unit, a register file, and a data path including a plurality of lanes. The data path and the register file are arranged so that writing to the register file by the first execution unit and by the second execution unit is allowed over the data path, reading from the register file by the first execution unit is allowed over the data path, and reading from the register file by the second execution unit is not allowed over the data path. The processor also includes a power control circuit configured to, when a transfer of data between the register file and either of the first and second execution units uses less than all of the lanes, power down the lanes of the data path not used for the transfer of the data.