Programmable Calculator With Power Saving Feature Patents (Class 713/321)
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Patent number: 8359482Abstract: A power supply circuit is provided. The power supply circuit includes an audio codec chip and a voltage absorbing circuit. The audio codec chip has a power input terminal. The power input terminal is connected to a power source terminal. The voltage absorbing circuit is connected between the power source terminal and the power input terminal of the audio codec chip so as to decrease a divided voltage accomplished with a voltage from the power source terminal to low level. A method configured for starting up an audio codec chip on a computer motherboard in a normal manner is also provided.Type: GrantFiled: December 11, 2009Date of Patent: January 22, 2013Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventor: Ke-You Hu
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Patent number: 8359486Abstract: A high speed input/output (HSIO) system and a power saving control method for the HSIO system are provided. The HSIO system has a plurality of transmission speed modes. When an external device is connected to the HSIO system and an auto-configuration link is completed, the power saving control method forcibly sets an interface controller to any desired transmission speed specification in accordance with an actual transmission speed of to-be-transmitted data. Therefore, transmission speed mode of a single physical layer can be changed to achieve a low power transmission.Type: GrantFiled: May 20, 2010Date of Patent: January 22, 2013Assignee: Faraday Technology Corp.Inventors: Po-Yao Huang, Chien-Ting Wang
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Patent number: 8352767Abstract: The invention relates to systems and or methodologies for intelligent and adaptive power management in mobile devices. A peripheral power management component can set peripheral devices to active or inactive based on one or more schemas. The schemas can be predetermined or generated by the peripheral power management component. In addition, an adaptive component can modify the schemas to reflect actual usage or changing trends for each peripheral device.Type: GrantFiled: November 26, 2008Date of Patent: January 8, 2013Assignee: Symbol Technologies, Inc.Inventors: Chi Zhang, Charles Bolen
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Patent number: 8352794Abstract: Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock signal from a clock signal generator and for outputting said clock signal to synchronous circuitry that is to be clocked by said clock signal.Type: GrantFiled: November 19, 2009Date of Patent: January 8, 2013Assignee: ARM LimitedInventors: Remi Teyssier, Florent Begon, Jocelyn Francois Orion Jaubert, Cédric Denis Robert Airaud
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Patent number: 8351361Abstract: A WCDMA enabled user equipment device configured to have functions collectively or selectively idle to conserve power. A discontinuous receiver is used to detect and read network messages and report the messages to the computer within the WCDMA enabled user equipment device. The computer then activates functions previously powered down to receive incoming messages for the user of the device. The discontinuous receiver is also used when the device is active to read network messages, freeing a modem of the device to operate on user messaging; and therefore, enhancing user related performance.Type: GrantFiled: May 19, 2008Date of Patent: January 8, 2013Assignee: QUALCOMM IncorporatedInventors: Michael Kohlmann, Tae Hea Nahm, Beomsup Kim, Cormac Conroy
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Publication number: 20130007491Abstract: Methods and apparatus relating to enhanced interconnect link width modulation for power savings are described. In one embodiment, the width of a link is modified from a first width to a second width in response to a power management flit, while non-idle flits continue to be transmitted over the link after transmission of the power management flit. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: July 1, 2011Publication date: January 3, 2013Inventors: VENKATRAMAN IYER, ROBERT G. BLANKENSHIP, DENNIS R. HALICKI
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Patent number: 8347119Abstract: In some embodiments, the invention involves modification of the processor utilization calculations that are used by operating system power management services to improve processor efficiency. An embodiment of the present invention is a system and method relating to power management policies under operating system control. In at least one embodiment, the present invention is intended to modify the processor utilization evaluation process so that C-state transition time and/or unhalted reference cycles are included in the calculation. Other embodiments are described and claimed.Type: GrantFiled: June 26, 2009Date of Patent: January 1, 2013Assignee: Intel CorporationInventor: Justin J. Song
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Patent number: 8344880Abstract: A field device of automation technology, is fed via a two-wire line or via an energy source of limited energy reserve associated with the field device. The field device includes: a hardwired communication interface having at least one communication channel; and, associated with the communication interface, a functional unit, which is embodied in such a manner, that it performs sending and/or receiving of digital communication signals via the communication interface. The functional unit, for the purpose of energy saving, is turned on only in active, operating phases, while it is switched off in inactive, resting phases; and a detection circuit is provided, which detects a communication signal applied to the communication interface and automatically activates the functional unit.Type: GrantFiled: December 16, 2009Date of Patent: January 1, 2013Assignee: Endress + Hauser Process Solutions AGInventors: Christian Seiler, Marc Fiedler
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Patent number: 8347121Abstract: A system and method for adjusting an energy efficient Ethernet (EEE) control policy using measured power savings. An EEE-enabled device can be designed to report EEE event data. This reported EEE event data can be used to quantify the actual EEE benefits of the EEE-enabled device, debug the EEE-enabled device, and adjust the EEE control policy.Type: GrantFiled: October 21, 2009Date of Patent: January 1, 2013Assignee: Broadcom CorporationInventors: Brad Matthews, Puneet Agarwal, Bruce Kwan
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Patent number: 8335939Abstract: A notebook computer includes a keyboard, a display, a light source arranged on the keyboard or the display, and a light source control circuit. The light source control circuit includes first to third electronic switches. A control terminal of the first electronic switch is connected to a working voltage terminal. A first terminal of the first electronic switch is connected to a first terminal of the light source and a first terminal of the third electronic switch. A second terminal of the light source is connected to a standby voltage terminal. A control terminal of the second electronic switch is connected to a sleep signal terminal. A first terminal of the second electronic switch is connected to the standby voltage terminal and a control terminal of the third electronic switch. Second terminals of the first to third electronic switches are grounded.Type: GrantFiled: September 20, 2010Date of Patent: December 18, 2012Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Chung-Chi Huang, Hai-Qing Zhou
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Patent number: 8335934Abstract: A network system forms a computer network, and includes: a collecting unit; a calculating unit; and a display unit. The collecting unit collects power consumption information from a connecting device. The power consumption information shows power consumption of the connecting device. The calculating unit calculates power consumption of the computer network based on the collected power consumption information. The calculated power consumption is itemized into constituent units based on a configuration of the computer network. The display unit displays the calculated power consumption.Type: GrantFiled: December 11, 2009Date of Patent: December 18, 2012Assignee: Alaxala Networks CorporationInventors: Yasuhiro Kodama, Mitsuru Nagasaka, Shinichi Akahane, Tomohiko Kouno, Teruo Kaganoi, Takeki Yazaki
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Patent number: 8332665Abstract: Methods and apparatuses for dynamically budgeting power usage in a data processing system. In one aspect, a data processing system, includes: one or more first components capable of being dynamically throttled to a plurality of different performance level settings; one or more second components; and one or more power usage sensors. The one or more power usage sensors are to determine information on power usage during a first time period of operation of the data processing system. The one or more first components and the one or more second components may include a computing element to determine one of the performance level settings of the one or more first components of the data processing system for a second time period subsequent to the first time period using the information on the power usage during the first time period.Type: GrantFiled: July 10, 2009Date of Patent: December 11, 2012Assignee: Apple Inc.Inventors: David G. Conroy, Keith Alan Cox, Michael Culbert
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Publication number: 20120311359Abstract: Consistent with embodiments of the present disclosure a redriver circuit is provided for a first and a second serial-unidirectional communications channel. The redriver circuit conditions received data signals by adjusting signal properties to correct for signal level attenuation and noise. The conditioned data signals are transmitted to corresponding outputs of the channels. The redriver circuit disables, in response to a first enable signal being inactive, current drawing circuitry of components for both channels on a common side of the redriver. The redriver circuit disables, in response to a second enable signal being inactive, current drawing circuitry of components for both channels on the other side of the redriver.Type: ApplicationFiled: June 3, 2011Publication date: December 6, 2012Inventor: Kenneth Jaramillo
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Patent number: 8321692Abstract: An information processing apparatus includes a plurality of storage units, a mirroring control unit configured to execute mirroring processing, which includes writing processing for writing same data on each of the plurality of storage units and reading processing for reading data from either one of the plurality of storage units, and a power control unit configured to independently control supply of power to the plurality of storage units. If the supply of power to the plurality of storage units is reduced, if the mirroring control unit starts the writing processing, the information processing apparatus resumes the power supply to the plurality of storage units, and if the mirroring control unit starts the reading processing, the information processing apparatus resumes the power supply to a specific storage unit from which the data is read, and configured to execute control not to resume the power supply to the other storage unit(s).Type: GrantFiled: December 18, 2009Date of Patent: November 27, 2012Assignee: Canon Kabushiki KaishaInventors: Fumio Mikami, Shozo Yamasaki
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Patent number: 8321702Abstract: According to one embodiment, an information processing apparatus having a power-saving function includes a monitoring module and a power-saving setting presenting module. The monitoring module monitors a usage pattern of the information processing apparatus, and stores log information indicative of the usage pattern in a storage device. The power-saving setting presenting module determines recommended values of power-saving parameters for specifying content of the power-saving function, based on the stored log information, and to display the determined recommended values.Type: GrantFiled: December 10, 2009Date of Patent: November 27, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Kaneko, Hideaki Andou
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Patent number: 8321699Abstract: A system and method is provided to measure the power consumption of circuits whereby, in one aspect, a processor's temperature is maintained so that its power consumption is measured at the point the processor throttles.Type: GrantFiled: August 19, 2011Date of Patent: November 27, 2012Assignee: Google Inc.Inventor: Jinal Dalal
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Patent number: 8316254Abstract: According to one embodiment, an information processing apparatus having a power-saving function includes a power-saving control module, a power consumption measuring module, a log accumulation module, and a log display module. The power-saving control module sets each of predetermined components in the information processing apparatus in either a normal operation state or a power-saving state, based on power-saving parameters corresponding to the predetermined components. The power consumption measuring module measures a total power amount consumed by the apparatus in a predetermined time period. The power-saving effect calculation module calculates a power-saving effect value indicative of a power amount reduced in the predetermined time period by the setting of the power-saving parameters. The log storing module stores information indicative of the total power amount and the power-saving effect value.Type: GrantFiled: April 9, 2010Date of Patent: November 20, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Kaneko, Hideaki Andou, Yasuyuki Mizuura
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Patent number: 8316247Abstract: A method and apparatus for user activity-based dynamic power management and policy creation for mobile platforms are described. In one embodiment, the method includes the monitoring of one or more sensor values of a mobile platform device to gather sensor activity data. Once the sensor activity data is gathered, the user state may be predicted according to the gathered user activity and an updated user state model. In one embodiment, the user state model is updated according to the sensor activity data. In one embodiment, a switch occurs from the present power management policy to a new power management policy if the new user state differs from a present user state by a predetermined amount. In one embodiment, at least one time-out parameter of a selected power management policy may be adjusted to comply with a predicted user state. Other embodiments are described and claimed.Type: GrantFiled: December 17, 2010Date of Patent: November 20, 2012Assignee: Intel CorporationInventors: Georgios N. Theocharous, Nilesh N. Shah, Uttam K. Sengupta, William N. Schilit, Kelan C. Silvester, Robert A. Dunstan
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Patent number: 8312301Abstract: A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.Type: GrantFiled: September 30, 2009Date of Patent: November 13, 2012Inventors: Martin Vorbach, Volker Baumgarte
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Patent number: 8312303Abstract: A power supply system for CPU is disclosed. The CPU includes a plurality of dynamic voltage identification (VID) pins, and the power supply standard of the CPU conforms to a first standard. The power supply system includes a dynamic VID signal line set and a core voltage controller. The VID signal line set is coupled to the VID pins of the CPU. The core voltage controller conforms to a second standard and is coupled to a partial line set of the dynamic VID signal line set. The core voltage controller determines a core voltage to be output to the CPU according to the partial line set to conform to the first standard.Type: GrantFiled: July 14, 2010Date of Patent: November 13, 2012Assignee: ASUSTeK Computer Inc.Inventors: Sheng-Chung Huang, Li-Chung Wang
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Patent number: 8307220Abstract: Methods, computers, and products for managing power consumption of a computer, the computer including a computer processor and managing power consumption of a computer includes: dynamically during operation of the computer, setting, by an in-band power manager in dependence upon performance metrics of the computer processor, a current performance state (‘p-state’) of the computer processor; and providing, by the in-band power manager to an out-of-band power manager, the current p-state of the computer processor.Type: GrantFiled: June 25, 2008Date of Patent: November 6, 2012Assignee: International Business Machines CorporationInventors: Thomas M. Brey, Wesley M. Felter, Sumeet Kochar, Charles R. Lefurgy, Ryuji Orita, Freeman L. Rawson, III, Malcolm S. Ware
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Patent number: 8301926Abstract: A data processing apparatus is switchable between a power saving mode and a normal operating mode. A transition triggering event determining section determines an event (e.g., detection of a document or operation of a power saving key) that causes the data processing apparatus to shift from the power saving mode to the normal operating mode, and a transition triggering event holding section stores the event. Then, a mode switching section causes the data processing apparatus to shift from the power saving mode to the normal operating mode in accordance with the event. An execution priority determining section determines based on the event, an execution priority level and/or an order of precedence in which a plurality of programs are executed during the normal operating mode. A program controlling section executes the plurality of programs in accordance with the execution priority level and/or an order of precedence.Type: GrantFiled: May 12, 2010Date of Patent: October 30, 2012Assignee: Oki Data CorporationInventor: Makoto Yamashita
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Patent number: 8301925Abstract: A system and method for establishing and dynamically controlling energy consumption in large-scale datacenters or IT infrastructures. The system including a primary configuration server, a router coupled to the primary configuration server, and a plurality of power-managed domains/clusters coupled to the router. The primary configuration server distributes an energy target to each of the power-managed domains/clusters over a predetermined interval to enable each of the power-managed domains/clusters to manage the power consumption for each of the power-managed domains/clusters to meet the energy target.Type: GrantFiled: October 20, 2011Date of Patent: October 30, 2012Assignee: Intel CorporationInventor: Matthew E. Tolentino
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Patent number: 8296592Abstract: A resume signal hold circuit holds an assertion of a resume signal instructed while the circuit block is in a stand-by mode. A resume signal mask circuit is provided between the circuit block and the resume signal hold circuit, and masks the signals while the circuit block is in the stand-by mode so that no signal can be input to the circuit block. A power saving control circuit causes the resume signal hold circuit to hold the assertion of the event signal and causes the resume signal mask circuit to mask the signals while the circuit block is in a stand-by mode. The power saving control circuit also causes the resume signal hold circuit to cancel the holding of the assertion of the resume signal after the completion of the resume setting of the circuit block and cancelling of the signal masking by the resume signal mask circuit.Type: GrantFiled: May 3, 2010Date of Patent: October 23, 2012Assignee: Renesas Electronics CorporationInventors: Tsuneki Sasaki, Shuichi Kunie, Tatsuya Kawasaki
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Patent number: 8291241Abstract: Systems and methods are disclosed for detecting the connection of a FireWire peer to a FireWire device. In one embodiment, a device may determine whether a peer connection is present based on peer detection circuit configured in each FireWire port of a FireWire device. When no peer is connected to a device, a peer connection in the circuit may be open, and a current path through the circuit may provide a low detect signal, indicating that no peer is connected. When a peer is connected to a detecting device, the current may pass through a resistance in the detected peer to provide a high detect signal, indicating that a peer is connected. In some embodiments, once a peer is detected, the FireWire system of the detecting device may be powered on, and the peer detection circuit may be powered off.Type: GrantFiled: June 4, 2009Date of Patent: October 16, 2012Assignee: Apple Inc.Inventors: Eric George Smith, Colin Whitby-Strevens, Eric Anderson
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Patent number: 8285340Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for providing a user with feedback regarding power consumption in a battery-operated electronic device. In one aspect, a method performed by data processing apparatus includes identifying, using the data processing apparatus, usage of a hardware component of a battery-operated electronic device that includes the data processing apparatus, attributing the usage of the hardware component to the hardware component or to a software application that uses the hardware component, recording, using the data processing apparatus, a power consumption resulting from the usage, and presenting power consumption feedback to a user using the data processing apparatus. The power consumption feedback identifies the hardware component or the software application of the electronic device and the power consumption resulting from the usage.Type: GrantFiled: September 26, 2011Date of Patent: October 9, 2012Assignee: Google Inc.Inventors: Dianne K. Hackborn, Daniel S. Rice, Amith Yamasani, Jason B. Parks, Evan Millar
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Patent number: 8281170Abstract: A dynamic clock frequency module includes a request evaluation module configured to generate a sum of requests to utilize a system bus from a plurality of modules. A frequency assignment module is configured to calculate a clock frequency for the system bus in response to the requests and adjust the clock frequency between at least two non-zero frequency values. A pulse stretch module is configured to increase a period of time that at least one of the requests is asserted in response to the sum.Type: GrantFiled: December 23, 2009Date of Patent: October 2, 2012Assignee: Marvell International Ltd.Inventor: Timothy J. Donovan
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Patent number: 8276003Abstract: Reducing current draw of solid state drives from a shared power supply of a computer at computer startup, each SSD including computer memory, a capacitor, a disk controller, and a charge controller, the disk controller configured to enable the charge controller to charge the capacitor upon receiving a charge command, the SSDs organized into startup groups characterized by a position in a predefined startup order. Upon startup of the computer, beginning with a first startup group in the predefined startup order and until the last startup group in the predefined startup order has received a charge command, embodiments include, sending, by a storage device initiator, a charge command to a startup group to initiate charging of the capacitor of each solid state drive in the startup group and waiting a predefined period of time before sending another charge command to a next startup group in the predefined startup order.Type: GrantFiled: December 11, 2009Date of Patent: September 25, 2012Assignee: International Business Machines CorporationInventors: Mark E. Andresen, Joaquin F. Pacheco
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Patent number: 8276004Abstract: Methods and systems to balance the load among a set of processing units, such as servers, in a manner that allows the servers periods of low power consumption. This allows energy efficient operation of the set of processing units. Moreover, the process is adaptable to variations in systemic response times, so that systemic response times may be improved when operational conditions so dictate.Type: GrantFiled: December 22, 2009Date of Patent: September 25, 2012Assignee: Intel CorporationInventors: Ren Wang, Sanjay Rungta, Tsung-Yuan Tai, Chih-Fan Hsin, Jr-Shian Tsai
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Patent number: 8276011Abstract: A system and method for tunneling control over a MAC/PHY interface for legacy ASIC support. Energy efficient Ethernet control or status information can be communicated over a MAC/PHY interface using control codes that are embedded in sequence ordered sets. These sequence ordered sets would not affect the data flow and can be tunneled within an existing interface (e.g., XAUI, XFI, xxMII or derivative interfaces) without generating errors.Type: GrantFiled: June 24, 2009Date of Patent: September 25, 2012Assignee: Broadcom CorporationInventors: Wael William Diab, Maurice David Caldwell
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Patent number: 8271816Abstract: A system and method for statistics recording of power devices is disclosed. A power circuit includes a power device to provide a specified electrical power to a load and a host controller coupled to the power device. The host controller is configured to provide issue instructions to and retrieve status information from the power device. A communications and control interface (CCI) is coupled between the power device and the host controller. The CCI is configured to operate as a communications interface between the power device and the host controller and to retrieve and store status information from the power device. The CCI may be capable of performing statistical analysis on the status information to help reduce the amount of information exchanged between the host controller and the power device, thereby reducing bandwidth requirements.Type: GrantFiled: March 11, 2008Date of Patent: September 18, 2012Assignee: Infineon Technologies Austria AGInventors: Jens Barrenscheen, Giuseppe Bernacchia, Martin Krueger, Erwin Huber
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Patent number: 8271810Abstract: Disclosed is a dynamic detector to detect an environmental condition including a power-supply level relative to a predetermined threshold signal during a training phase; and an adjustable buffer, coupled with the dynamic detector, configured to adjust output drive strength during the training phase in response to the detected environmental condition.Type: GrantFiled: July 24, 2009Date of Patent: September 18, 2012Assignee: Cypress Semiconductor CorporationInventors: Michael Fliesler, David Lindley, Morgan Whately, Vinod Rajan, Muthukumar Nagarajan, Jun Li, Jeffery Hunt
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Patent number: 8271819Abstract: An information handling system (IHS) is disclosed providing a power supply operable to provide an output current to the IHS during power initiation. The IHS may also include a first power component associated with a first power stage wherein the first power stage may have a first current threshold. Furthermore, the IHS may include a power control logic coupled to the power supply and the first power component. As such, the power control logic may be operable to communicate the first power stage to the power supply, and if the output current does not exceed the first current threshold during the first power stage, the power control logic may be operable to communicate a second power stage having a second current threshold to the power supply.Type: GrantFiled: March 31, 2009Date of Patent: September 18, 2012Assignee: Dell Products L.P.Inventors: John J. Breen, III, Scott Michael Ramsey, Timothy Thompson, Shiguo Luo
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Patent number: 8271809Abstract: Illustrative embodiments estimate power consumption within a multi-core microprocessor chip. An authorized user selects a set of activities to be monitored. A value for each activity of the set of activities is stored in a separate counter of a set of counters, forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. The set of activities are grouped into subsets. The stored values corresponding to each activity in each subset are summed, forming a total value for each subset. The total value of each subset is multiplied by a factor corresponding to the subset, forming a scaled value for each subset. The scaled value of each subset is summed, forming a power usage value. A power manager adjusts the operational parameters of the unit based on a comparison of the power usage value to a threshold value.Type: GrantFiled: April 15, 2009Date of Patent: September 18, 2012Assignee: International Business Machines CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, Michael Stephen Floyd
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Publication number: 20120226925Abstract: A method for switching an operating system (OS) and an electronic apparatus are provided. While switching to a first OS, a system firmware stored in a memory unit declares that a first segment of a system memory is in a usable state and a second segment of the system memory is in a reserved state by using a first resource description table, so that the first OS is in a working state in the first segment and a second OS is in a power-saving state in the second segment. While switching to the second OS, the system firmware declares that the second segment is in the usable state and the first segment is in the reserved state by using a second resource description table, so that the second OS is in the working state and the first OS is in the power-saving state.Type: ApplicationFiled: November 24, 2011Publication date: September 6, 2012Applicant: VIA TECHNOLOGIES, INC.Inventors: Jiang-Bo Wang, Kai Li, Xiao-Long Wang, Xiong Zhang
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Patent number: 8261101Abstract: A suspend mode is provided that can be asserted using an Internal Configuration Access Port (ICAP) of an integrated circuit such as a Field Programmable Gate Array (FPGA), as supposed to a dedicated external suspend pin typically accessed by a device external to the FPGA. The ICAP is designed to assert the suspend mode through a configuration block to maintain the state of the configuration memory array while lowering power, in a similar manner to when an external suspend pin is accessed. Internal circuits can, thus, be used to assert a suspend mode through the ICAP.Type: GrantFiled: March 31, 2008Date of Patent: September 4, 2012Assignee: Xilinx, Inc.Inventors: Honggo Wijaya, Patrick J. Crotty
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Patent number: 8261112Abstract: A method, system, and computer program product for optimizing power consumption of an executing processor executing. The method includes determining a first sensitivity relationship (SR) based on a first and a second performance metric value (PMV) measured at a first and second operating frequency (OF), respectively. The first SR predicts workload performance over a range of OFs. A third OF is determined based on the first SR and a specified workload performance floor. A third PMV is measured by executing the processor operating at the third OF. A second SR based on the second and third PMVs is then determined. The first and second SRs are logically combined to generate a third SR. Based on the third SR, a fourth OF is outputted.Type: GrantFiled: December 8, 2008Date of Patent: September 4, 2012Assignee: International Business Machines CorporationInventors: John B. Carter, Heather L. Hanson, Karthick Rajamani, Freeman L. Rawson, III, Malcolm S. Ware
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Patent number: 8261276Abstract: A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.Type: GrantFiled: March 31, 2008Date of Patent: September 4, 2012Assignee: International Business Machines CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, Richard James Eickemeyer, Susan Elizabeth Eisen, Michael Stephen Floyd, Hans Mikael Jacobson, Jeffrey R. Summers
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Patent number: 8255723Abstract: A multiple instruction execution modules device that comprises a first instruction execution module and a second instruction execution module and a context switch controller; wherein the first instruction execution module is logically identical to the second instruction execution module but substantially differs from the second instruction execution module by at least one power consumption characteristic; wherein the context switch controller controls a context switch between the first instruction execution module and the second instruction execution module; wherein an instruction execution module that its context has been transferred is shut down.Type: GrantFiled: July 24, 2009Date of Patent: August 28, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Anton Rozen, Michael Priel, Leonid Smolyansky
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Patent number: 8250382Abstract: A method of managing power consumption by a plurality of blade servers within a processing system. The speed of at least one of the plurality of blade servers is reduced in response to the processing system reaching a power or thermal threshold. At least one of the plurality of blade servers is identified as not being critical to maintain in a working state and the critical blade server is put in a sleep state. A satellite management controller may control blade server power consumption and heat generation in various ways that combine processor speed-stepping and control of processor sleep states. Known sleep states save more power than speed-stepping by turning off the processor and/or volatile memory. The processor speed and sleep-states of at least one non-critical blade server, and optionally the processor speed of a critical processor, may be changed in order to control the power consumption below a power threshold or control the temperature below a thermal threshold.Type: GrantFiled: August 22, 2007Date of Patent: August 21, 2012Assignee: International Business Machines CorporationInventors: Stephen C. Maglione, Edward Stanley Suffern
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Publication number: 20120210152Abstract: A mechanism is provided for transparently consolidating resources of logical partitions. Responsive to the existence of the non-folded resource on an originating resource chip, the virtualization mechanism determines whether there is a destination resource chip to either exchange operations of the non-folded resource with a folded resource on the destination chip or migrate operations of the non-folded resource to a non-folded resource on the destination chip. Responsive to the existence of the folded resource on the destination resource chip, the virtualization mechanism transparently exchanges the operations of the non-folded resource from the originating resource chip to the folded resource on the destination resource chip, where the folded resource remains folded on the originating resource chip after the exchange. Responsive to the absence of another non-folded resource on the originating resource chip, the vitalization mechanism places the originating resource chip into a deeper power saving mode.Type: ApplicationFiled: April 26, 2012Publication date: August 16, 2012Applicant: International Business Machines CorporationInventors: Naresh Nayar, Karthik Rajamani, Freeman L. Rawson, III
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Patent number: 8239693Abstract: The invention has disclosed a system power management circuit comprising: a printed circuit board and a hardware monitor. The printed circuit board includes at least a first power connector, a second power connector, and more than one detection circuits disposed thereon; wherein the first power connector is used for electrically connecting a power supply, the second power connector is used for electrically connecting a power connector of a motherboard, inputs of the detection circuits are electrically connected to the first power connector, respectively. The hardware monitor is electrically connected to outputs of the detection circuits, and used for converting electrical signals outputted from the outputs of the detection circuits into corresponding digital signals, as well as for transmitting the digital signals to the motherboard via a two-wire bus, the two-wire bus is bi-directional, and may be an I2C or a SM bus.Type: GrantFiled: August 6, 2008Date of Patent: August 7, 2012Assignee: MSI Corporation (Shenzhen) Co., Ltd.Inventors: San-Wei Nieh, Yu-Tsung Kao, Tung-Jung Tsai
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Patent number: 8235810Abstract: Trusted Energy Saving (TES) methods applied to server based distributed downloadable gaming for allowing casino operators to significantly reduce their energy bills by placing the main controller of selected unused gaining machines into low-power mode while retaining total control and trust.Type: GrantFiled: February 28, 2009Date of Patent: August 7, 2012Assignee: IGTInventors: Thierry Brunet de Courssou, Alexander Popovich, Cameron Anthony Filipour, Adam Singer
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Patent number: 8234507Abstract: A wireless electronic-ink display device supported in packaging, and employing a power switching mechanism which operates to prevent leakage, drainage or discharge of the electro-chemical battery until a change in predetermined state of configuration occurs. The wireless electronic-ink based display device comprises (i) a power source module with an electro-chemical battery, (ii) a power management module for managing the power levels within the wireless electronic-ink display device, and (iii) a power switching module, arranged between the power source module and the power management module, and automatically responsive to a change in at least one predefined state of device configuration, to prevent leakage, drainage or discharge of the electro-chemical battery until a change in predetermined state of configuration occurs.Type: GrantFiled: January 13, 2009Date of Patent: July 31, 2012Assignee: Metrologic Instruments, Inc.Inventors: Xiaoxun Zhu, Steven Essinger, Michael Schnee, Yong Liu
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Patent number: 8230238Abstract: A method for determining power consumption in a data storage system is provided. The method comprises determining data access patterns for at least a first storage device in a storage system based on operations performed by the first storage device; and calculating power consumption for the storage system by interpolating costs associated with the operations performed by the first storage device, wherein the cost associated with each operation is determined based on: (1) various levels of activities for the first storage device and a mix of workload characteristics, and (2) predetermined power consumption measurements obtained from one or more benchmarks for same operations performed by a second storage device in a test environment.Type: GrantFiled: August 25, 2008Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: Miriam Allalouf, Michael E. Factor, Ronen Itshak Kat, Lee Charles LaFrese, Dalit Naor, David Blair Whitworth
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Publication number: 20120173907Abstract: Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption.Type: ApplicationFiled: December 30, 2011Publication date: July 5, 2012Inventors: Jaideep MOSES, Rameshkumar G. Illikkal, Ravishankar Iyer, Jared E. Bendt, Sadagopan Srinivasan, Andrew J. Herdrich, Ashish V. Choubal, Avinash N. Ananthakrishnan, Vijay S.R. Degalahal
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Patent number: 8214663Abstract: A mechanism is provided for using a power proxy unit combined with on-chip actuators to meet a defined power target value identifying a target power consumption of a component of a data processing system. A power manager in the data processing system identifies a proxy power threshold value, for the defined power target value, identifying a maximum power usage for the component, and a power usage estimate value identifying a current power usage estimate for the component. The power manager sends a set of signals to one or more on-chip actuators in the power proxy unit associated with the component in response to the power usage estimate value being greater than the power proxy threshold value. The one or more on-chip actuators adjusts a set of operational parameters associated with the component in order to meet the defined power target value.Type: GrantFiled: April 15, 2009Date of Patent: July 3, 2012Assignee: International Business Machines CorporationInventors: Michael S. Floyd, Karthick Rajamani, Malcolm S. Ware
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Publication number: 20120166837Abstract: A multi-core processor provides a configurable resource shared by two or more cores, wherein configurations of the resource affect the power, speed, or efficiency with which the cores sharing the resource are able to operate. Internal core power state management logic configures each core to participate in a de-centralized inter-core power state discovery process to discover a composite target power state for the shared resource that is a most restrictive or power-conserving state that will not interfere with any of the corresponding target power states of each core sharing the resource. The internal core power state management logic determines whether the core is a master core authorized to configure the resource, and if so, configures that resource in the discovered composite power state. The de-centralized power state discovery process is carried out between the cores on sideband, non-system bus wires, without the assistance of centralized non-core logic.Type: ApplicationFiled: November 17, 2011Publication date: June 28, 2012Applicant: VIA Technologies, Inc.Inventors: G. Glenn Henry, Darius D. Gaskins
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Publication number: 20120159215Abstract: A network power management apparatus and method. The network power management apparatus includes a protocol management unit configured to be connected to a local communication apparatus and establish and manage a path between the local communication apparatus and neighboring communication apparatuses in the same network.Type: ApplicationFiled: December 15, 2011Publication date: June 21, 2012Applicant: Electronics and Telecommunications Research InstituteInventors: Ki-Won KIM, Ho-Young SONG
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Patent number: 8205100Abstract: A method for power managing hardware. The method includes determining hardware to power manage, sending a tracing request from a power management control to a tracing framework to obtain usage data of the hardware, and identifying a first probe to obtain first tracing data corresponding to the usage data in a first hardware control software component, where the first hardware control software is configured to interact with the hardware. The method further includes enabling the first probe, obtaining the first tracing data from the first probe, where the first tracing data is obtained when the first probe is encountered during execution of the first hardware control software, and modifying operation of the hardware using the first tracing data.Type: GrantFiled: June 19, 2008Date of Patent: June 19, 2012Assignee: Oracle America, Inc.Inventors: Eric C. Saxe, Darrin P. Johnson, Jonathan J. Chew