Programmable Calculator With Power Saving Feature Patents (Class 713/321)
  • Patent number: 8205107
    Abstract: A system includes a dual in-line memory module and a system board. The dual in-line memory module includes a plurality of dynamic random access memory devices, and a system management interface. The system management interface is configured to measure a first voltage provided to the dynamic random access memory devices, and configured to digitize the first voltage. The system board includes a test module and a voltage regulator. The test module is configured to receive the digitized first voltage via a connector pin between the dual in-line memory module and the system board, and configured to compare the first voltage to a first threshold voltage. The voltage regulator is configured to adjust a remote sense target voltage for the system management interface when the first voltage is less than the first threshold voltage.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: June 19, 2012
    Assignee: Dell Products, LP
    Inventors: Stuart A. Berke, Kunrong Wang
  • Patent number: 8200995
    Abstract: A technique for determining task allocation for reducing power consumption of an entire system is disclosed. This system includes physical computers, a cooling apparatus for cooling the physical computers, and a power-saving control server for controlling the physical computers and cooling apparatus. The power-saving control server includes a virtual server layout generator which sets up a plurality of sets of task allocations with respect to the physical computers, a server power calculator for calculating power consumption of the physical computers in each task allocation, a physical computer profile used to estimate a heat release amount of the physical computers in each task allocation, a cooling power calculator which computes power consumption of the cooling apparatus, and a virtual server relocator which determines a task allocation with a total of calculated values of the server/cooling power calculators being minimized to be the optimum task allocation for the physical computers.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: June 12, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Yoko Shiga, Keisuke Hatasaki, Yoshifumi Takamoto, Takeshi Kato, Tadakatsu Nakajima
  • Patent number: 8201004
    Abstract: An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: June 12, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy David Anderson, Lewis Nardini, Jose Luis Flores, Abhijeet Chachad, Raguram Damodaran, Joseph R. M. Zbiciak, Gary Swoboda
  • Patent number: 8195965
    Abstract: A midspan unit arranged to supply power to a powered device over data communication cabling constituted of a signal conditioner exhibiting a transfer function with a gain of not less than ?0.4 dB as compared with: (K1*(s+R/L1+a)^m)/((s+R/L2+b)^n) over a predetermined frequency range associated with the data transmitted from the powered device. s represents 2*?*(??1)*f, wherein f represents the predetermined frequency range associated with the data terminal equipment to be powered. R represents the signal source impedance in parallel with the load termination impedance. L1 represents the effective inductance of a data transformer winding of the data transmitter of the powered device, the effective inductance determined responsive to power received by the powered device from the power sourcing equipment; and L2 represents the effective inductance of the data transformer winding of the data transmitter of the powered device expected by a receiver of the switch or hub equipment.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: June 5, 2012
    Assignee: Microsemi Corp. - Analog Mixed Signal Group Ltd.
    Inventor: Yair Darshan
  • Patent number: 8195969
    Abstract: Each of a plurality of control units starts the control unit with one of a first start method and a second start. When a first control unit among the control units starts with a second start method, the first control unit instructs a second control unit among the control units to start with the second start method. Thus, all the control units are started with the same start method.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: June 5, 2012
    Assignee: Ricoh Company, Limited
    Inventor: Katsuhiko Katoh
  • Publication number: 20120137151
    Abstract: A network device, for supporting a power saving mechanism through an auto-negotiation of HDMI, includes a transmitting circuit and a receiving circuit. The transmitting circuit is arranged for generating a link pulse signal to a second network device, wherein the network device and the second network device perform the auto-negotiation of a network connection by using the link pulse signal through HDMI in order to support the power saving mechanism. After the receiving circuit of the network device receives another link pulse signal transmitted from the second network device through HDMI, the network device is controlled to be operated under the power saving mechanism.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 31, 2012
    Inventors: Liang-Wei Huang, Shieh-Hsing Kuo, Ming-Feng Hsu, Yuan-Jih Chu
  • Patent number: 8190931
    Abstract: In a method for monitoring power consumption by a system within an integrated circuit, one or more software programs are executed on the system on a chip (SOC). While the program executes, power control settings of a plurality of functional units within the SOC may be adjusted in response to executing the one or more software programs, whereby power consumption within the SOC varies over time. The power control settings may be changed in response to explicit directions from the executing software, or may occur autonomously in response to load monitoring control modules within the SOC. A sequence of power states is reported for the plurality of functional units within the SOC. Each of the sequence of power states may include clock frequencies from multiple clock domains, voltage levels for multiple voltage domains, initiator activity, target activity, memory module power enablement, or power enablement of each of the plurality of functional units.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: May 29, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Gilbert Laurenti, Dario Cardini
  • Patent number: 8176339
    Abstract: A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: May 8, 2012
    Assignee: International Business Machines Corporation
    Inventors: Gary Dean Anderson, Hoa Cong Nguyen, Thoi Nguyen
  • Patent number: 8176344
    Abstract: An information processing apparatus used to reduce power supply to nonvolatile memory when in power saving mode. To accomplish this, the information processing apparatus stores data in the nonvolatile memory that can be used in power saving mode to a volatile memory to which power will still be supplied while in power saving mode. Further, the information processing apparatus enables the operating system to recognize the storage area in which the data is stored as a replacement for the nonvolatile memory.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: May 8, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takashi Koshika, Hidenori Higashi
  • Patent number: 8176345
    Abstract: According to one embodiment, an information processing apparatus includes a media drive having a normal operation mode and a power saving operation mode in which less power is consumed than in the normal operation mode, a control module configured to control the media drive, and a determination module configured to shift, when it is determined that the control module does not execute data access to the media drive for a predetermined period, the media drive from the normal operation mode to the power saving operation mode.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: May 8, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hosui Kawakami
  • Patent number: 8176341
    Abstract: Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: May 8, 2012
    Assignee: Intel Corporation
    Inventors: Jaya L. Jeyaseelan, Neil Songer, Barnes Cooper, Paul S. Diefenbaugh
  • Patent number: 8176349
    Abstract: A look-ahead processor identifies instructions that are at least likely to be executed by a main processor. The look-ahead processor determines a power state for the main processor that is suitable for executing the instructions. The look-ahead processor signals the main processor to enter the suitable performance state.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: May 8, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Thomas P. Sawyers
  • Patent number: 8171313
    Abstract: Provided is a communication device capable of efficiently performing a power supply control when reducing power consumption by reducing the time during which the power is supplied. In the device, a CPU power saving control unit (301) switches between a normal mode in which the power is supplied to a CPU (302) and a low power consumption mode in which the power supply is stopped at predetermined timing. A session management table (321) stores transmission intervals before and after conversion. An information conversion section (322) converts the transmission intervals of session maintenance messages according to a predetermined rule so that the transmission intervals of the session maintenance messages of respective protocols are mutually synchronized between the protocols.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: May 1, 2012
    Assignee: Panasonic Corporation
    Inventors: Satoshi Iino, Kazumasa Gomyo, Tomohiro Ishihara, Yuji Hashimoto
  • Patent number: 8171319
    Abstract: Disclosed are systems, methods, and computer program products for managing power states in processors of a data processing system. In one embodiment, the invention is directed to a data processing system having dynamically configurable power-performance states (“pstates”). The data processing system includes a processor configured to operate at multiple states of frequency and voltage. The data processing system also has a power manager module configured to monitor operation of the data processing system. The data processing system further includes a pstates table having a plurality of pstate definitions, wherein each pstate definition includes a voltage value, a frequency value, and at least one unique pointer that indicates a transition from a given pstate to a different pstate.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: May 1, 2012
    Assignee: International Business Machines Corporation
    Inventors: Soraya Ghiasi, Malcolm S. Ware, Karthick Rajamani, Freeman L. Rawson, III, Michael S. Floyd, Juan C. Rubio
  • Patent number: 8171325
    Abstract: Methods, services, devices, and programmable code are provided for moving computing processes without loss of service. Powered components supporting a computing infrastructure executing computing processes are monitored for thermal characteristics, each associated with at least one of the deployed components. A thermal characteristic rule set comprising a threshold is applied to the monitored characteristics, and in response to an association with a monitored characteristic correlating with the threshold, a computing process is moved from one powered component to another having a monitored thermal characteristics not correlated with the threshold, the moving in real-time and without causing an interruption of service to an end user using the moved process.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: May 1, 2012
    Assignee: International Business Machines Corporation
    Inventors: David C. Brillhart, Christopher J. Dawson, Rick A. Hamilton, II, James W. Seaman
  • Patent number: 8166314
    Abstract: A method is provided for controlling I/O request access to an encrypted storage device when the encryption key for the encrypted storage device is not available.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: April 24, 2012
    Assignee: EMC Corporation
    Inventors: Helen S. Raizen, Jeffrey Camp, Michael E. Bappe
  • Patent number: 8166316
    Abstract: In an embodiment, a system comprises a first memory module interface unit (MMIU) configured to couple to a first one or more memory modules, and a second MMIU configured to couple to a second one or more memory modules. The first MMIU is configured to operate the first one or more memory modules at a first frequency and the second MMIU is configured to concurrently operate the second one or more memory modules at a second operating frequency different from the first operating frequency.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: April 24, 2012
    Assignee: Oracle America, Inc.
    Inventor: Sanjiv Kapil
  • Publication number: 20120096291
    Abstract: An energy-saving control apparatus comprises a power input interface, a power output interface, a controlling unit, a sampling unit, a central processing unit and a data storage unit. The power input interface is used for connecting to an external power source. The power output interface is used for connecting to an external electric appliance. The controlling unit is used for controlling the value of the current or voltage which inputted from the power input interface to the power output interface. The controlling unit can be also used for controlling the on and off of the power output interface. The sampling unit is used for sampling and outputting the electrical parameters of the external electric appliance. The central processing unit is used for processing the output signals from the sampling unit and outputting the control signals to the controlling unit. The data storage unit stores the necessary data for the operation of the central processing unit.
    Type: Application
    Filed: November 27, 2009
    Publication date: April 19, 2012
    Inventor: Jichang Guang
  • Patent number: 8156357
    Abstract: A memory has bits that fail as power supply voltage is reduced to reduce power and/or increase endurance. The bits become properly functional when the power supply voltage is increased back to its original value. With the reduced voltage, portions of the memory that include non-functional bits are not used. Much of the memory may remain functional and use is retained. When the voltage is increased, the portions of the memory that were not used because of being non-functional due to the reduced power supply voltage may then be used again. This is particularly useful in a cache where the decrease in available memory due to power supply voltage reduction can be implemented as a reduction in the number of ways. Thus, for example an eight way cache can simply be reduced to a four way cache when the power is being reduced or endurance increased.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: April 10, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Shayan Zhang, James D. Burnett, Prashant U. Kenkare, Hema Ramamurthy, Andrew C. Russell, Michael D. Snyder
  • Patent number: 8150539
    Abstract: An information processing apparatus includes an information processing unit, an interface supplying electrical power to and communicating a signal with an external electronic device through a single connector, a unit supplying electrical power to the electronic device through the interface and including a rechargeable battery. Detection units detect a connection of the electronic device to the apparatus, an external power supply. The power supply control, when the connections are detected, keeps supplying electrical power to the electronic device through the interface even after deactivation of the apparatus, in the event an instruction to turn off a power supply of the apparatus or deactivate the apparatus is issued. When the connection of the external power supply for charging the rechargeable battery to the apparatus is not detected, the power supply does not supply electrical power to the electronic device even during operation of the apparatus.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: April 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Fujihito Numano
  • Patent number: 8145921
    Abstract: A system and method for implementing a common control bus in a multi-regulator power supply integrated circuit. The integrated circuit may, for example, comprise first and second power regulator modules that control at least one characteristic of respective power signals. The integrated circuit may also, for example, comprise a communication interface module that receives power control information related to operation of the first and second power regulator modules over a shared data bus. An exemplary method may, for example, comprise receiving power control information over a data bus. The method may also, for example, comprise determining which of a plurality of power regulators corresponds to the received power control information. The method may further, for example, comprise determining a regulator control signal, based at least in part on the received power control information, and provide the regulator control signal to the determined regulator(s) to control operation of the determined regulator(s).
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: March 27, 2012
    Assignee: Broadcom Corporation
    Inventors: Chun-ying Chen, Pieter Vorenkamp, Neil Y. Kim, Sumant Ranganathan
  • Patent number: 8140870
    Abstract: A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary winding and a second transistor is coupled in series with the secondary winding. A control circuit generating control signals for controlling operation of the first and second transistors. The control signals are generated responsive to the values in certain triggered counting circuits satisfying programmable thresholds.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: March 20, 2012
    Assignee: STMicroelectronics, Inc.
    Inventor: Thomas L. Hopkins
  • Publication number: 20120066529
    Abstract: An information processing apparatus includes an information processing unit, an interface supplying electrical power to and communicating a signal with an external electronic device through a single connector, a unit supplying electrical power to the electronic device through the interface and including a rechargeable battery. Detection units detect a connection of the electronic device to the apparatus, an external power supply. The power supply control, when the connections are detected, keeps supplying electrical power to the electronic device through the interface even after deactivation of the apparatus, in the event an instruction to turn off a power supply of the apparatus or deactivate the apparatus is issued. When the connection of the external power supply for charging the rechargeable battery to the apparatus is not detected, the power supply does not supply electrical power to the electronic device even during operation of the apparatus.
    Type: Application
    Filed: November 22, 2011
    Publication date: March 15, 2012
    Applicant: KABUSHHIKI KAISHA TOSHIBA
    Inventor: Fujihito NUMANO
  • Publication number: 20120066528
    Abstract: To conserve power in a controlling device having a processing device in communication with an input element and a transmitting device the processing device is caused to be placed into a low-power state for at least a portion of a transmission inactive interval intermediate the transmission of at least a pair of command frames. The command frames are caused to be transmitted by the transmitting device in response to an activation of the input element sensed via the processing device to thereby command a functional operation of an intended target device.
    Type: Application
    Filed: February 16, 2011
    Publication date: March 15, 2012
    Applicant: UNIVERSAL ELECTRONICS INC.
    Inventors: Arsham Hatambeiki, Christopher Lee Sommerville, Weidong William Wang
  • Patent number: 8131892
    Abstract: A storage apparatus is provided that is capable of reducing data maintenance management costs with a performance that is both highly reliable and fast. The present invention is storage apparatus where an intermediary device is arranged between a controller and a plurality of disk devices of different performances arranged in a hierarchical manner. The controller unit carries out I/O accesses to and from the disk devices via the intermediary devices based on access requests sent from host apparatus. The intermediary device includes a power saving control function for the disk device and carries out operation control such as spin off and spin up of disk devices in accordance with conditions set in advance.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: March 6, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Kumasawa, Takashi Chikusa, Satoru Yamaura
  • Patent number: 8131991
    Abstract: A computer with multiple software applications has defined for it plural software profiles for selection of one of the profiles in response to a system and/or user signal. Each profile when selected enables a respective set of applications to run on the system.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: March 6, 2012
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventors: Adrian Crisan, Fredrik Carpio
  • Patent number: 8127160
    Abstract: Dynamic frequency and voltage scaling for a computer processor, including retrieving information specifying a nominal operating point of frequency and voltage and an operating range of frequency and voltage for the processor; creating, by the power management module dynamically at run time in dependence upon the retrieved information, a table of frequency, voltage pairs, each pair specifying an operating point of frequency and voltage for the processor, each pair disposed upon a line drawn in frequency-voltage space through the nominal operating point between the minimum operating point and the maximum operating point, the distance between each pair defined in dependence upon a minimum change in power supply voltage supported by the power supply; and selecting and applying, by the power management module from the table, an operating voltage and frequency for the processor in dependence upon current operating conditions of the processor.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: February 28, 2012
    Assignee: International Business Machines Corporation
    Inventors: Andreas Bieswanger, Andrew Geissler, Hye-Young McCreary, Freeman L. Rawson, Malcolm S. Ware
  • Patent number: 8127166
    Abstract: Various techniques for managing power consumption of computing devices within a data protection system are disclosed. For example, one method involves accessing policy information, which the policy information indicates when one or more data protection system activities should be performed and identifies whether a computing device is participating in the data protection system activities. Based upon this policy information, the method then identifies whether power consumption of the computing device can be reduced. In response to identifying that the power consumption of the computing device can be reduced, a power management command is automatically sent via a network. Performance of the power management command reduces the power consumption of the computing device.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: February 28, 2012
    Assignee: Symantec Corporation
    Inventor: Jeremy Dean Swift
  • Patent number: 8111502
    Abstract: An arrangement related to subsea electric power distributing AC-system and adapted for a subsea application. The arrangement is enclosed in a watertight casing. The casing exposes a main power input connection, adapted for watertight co-ordination with a first subsea cable and a main power output connection, adapted for a watertight co-ordination with a second subsea cable. The second subsea cable is adapted for a power supply to an AC-current and AC-voltage adapted device. The arrangement includes interconnected: a voltage regulator connected to the first cable, and a NO-load switching unit connected to the second cable, and a control unit. The control unit is adapted, in a first operative mode, to regulate the output AC-voltage from the voltage regulator towards and to zero, or at least almost to zero, and in a second subsequent operative mode, to bring the NO-load switching unit from an ON-position to an OFF-position or vice versa.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: February 7, 2012
    Assignee: Vetco Gray Scandinavia AS
    Inventor: Svend Rocke
  • Patent number: 8112650
    Abstract: Methods and apparatus for re-acquiring a WiMAX network after a relatively long power saving mode (e.g., sleep or idle mode) using a “pre-wakeup” scheme are provided. According to this pre-wakeup scheme, a mobile station (MS) may power up receiving circuitry to search for the current channel or, if unsuccessful, a neighbor channel. After a successful network search during sleep mode, the MS may return to sleep for the remainder of the sleep window until the circuitry is powered up a second time to wakeup and then listen for an expected message. By pre-waking up and searching before waking up for the expected message, the MS may counteract the effects of the potential error in the local oscillator frequency accumulated during the long sleep mode. In this manner, the message miss rate may be reduced, thereby saving power and extending the time in which the MS may operate between battery rechargings.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: February 7, 2012
    Assignee: Qualcomm Incorporated
    Inventors: Shan Qing, Tom Chin
  • Patent number: 8099618
    Abstract: A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: January 17, 2012
    Inventors: Martin Vorbach, Volker Baumgarte
  • Patent number: 8093759
    Abstract: A device (12) supplies energy to a rapid cycling and/or rapidly cycled integrated circuit (13, 52) which includes a circuit load (17) and an internal capacity (15) connected parallel to the circuit load (17). The integrated circuit (13, 52) has a high cycle frequency (f1) especially at least in the MHz range. A supply unit (14) especially designed as a current source is directly connected to the internal capacity (15). The supply unit (14) has an internal resistance, the impedance level of which is so high at the cycle frequency (f1) that a current (ID2) supplying the circuit load (17) originates to a greater degree from the internal capacity (15) than from the supply unit (14). At least one auxiliary load, current sink or load controller is provided as an integral component of the integrated circuit and is connected to the circuit load to smooth load fluctuations.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: January 10, 2012
    Assignees: Conti Temic microelectronic GmbH, Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung e. V., Infineon Technologies AG
    Inventors: Goeran Schubert, Thomas Steinecke, Uwe Keller, Thomas Mager
  • Patent number: 8090826
    Abstract: Managing power-consuming resources on a first computing device by time-based and condition-based scheduling of data delivery from a plurality of second computing devices. A scheduler executing on the first computing device has knowledge of recurrent schedules for activation by the second computing devices. The first computing device determines availability of the power-consuming resources and adjusts an activation time for the schedules to use the power-consuming resources when the resources are available. Managing the schedules associated with the second computing devices preserves battery life of the first computing device.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: January 3, 2012
    Assignee: Microsoft Corporation
    Inventors: Anh P. Tran, Lloyd Alfred Moore, John Eldridge, Steven Oliver Elliott
  • Patent number: 8090963
    Abstract: Based on bounds of a period of reduced operation for a base device, a base device generates a power management message for transmission to a peripheral device. In the power management message, the base device inserts bounds of a period of reduced operation for the peripheral device. As a result, the periods of reduced operation conserve battery power in both devices and the two devices may reestablish a communications channel upon reaching the end of the period of reduced operation and resuming normal operations.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: January 3, 2012
    Assignee: Research In Motion Limited
    Inventors: Neil Patrick Adams, Herbert A. Little, Michael McCallum
  • Patent number: 8086886
    Abstract: A method and apparatus for group power management of network devices. Some embodiments of an apparatus include a power management module, where the power management module is to transition the apparatus from a normal state to a low power state. The apparatus includes a wake module having a processor that remains active in the low power state, and a register to store a group address. The apparatus includes a network interface that is monitored by the processor in the low power state, where the processor detects a data packet identifying the group address at the network interface, and where the power management module returns the apparatus to the normal state upon detection of the data packet.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: December 27, 2011
    Assignee: Silicon Image, Inc.
    Inventors: Brian K. Schmidt, James G. Hanko
  • Publication number: 20110307721
    Abstract: Proposed are a storage apparatus and a power consumption estimation method capable of easily and accurately estimating the power consumption of a physical drive without having to use a wattmeter. Operational information concerning a seek amount and a data transfer amount in the relevant hard disk drive which are internally recorded and retained by the respective hard disk drives is collected from each of the hard disk drives, and power consumption of each of the hard disk drives is estimated based on the acquired operational information of each of the hard disk drives.
    Type: Application
    Filed: March 5, 2010
    Publication date: December 15, 2011
    Applicant: HITACHI, LTD.
    Inventors: Katsumi Ouchi, Masanori Takada, Akira Yamamoto
  • Patent number: 8078894
    Abstract: Power management architectures, methods and systems for programmable integrated circuit are disclosed. One embodiment of the present invention pertains to a power management software architecture which comprises power management modules each associated with a respective driver. Each driver is associated with a component of a programmable integrated circuit and displayable as a graphic image within an on-screen display of an integrated circuit design tool for programming the programmable integrated circuit. In addition, each power management module is operable to report power consumption data customized to its respective driver. The power management software architecture also comprises a power source module associated with a power source for the programmable integrated circuit for reporting power supply characteristics.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: December 13, 2011
    Assignee: Cypress Semiconductor Corporation
    Inventor: Kenneth Y. Ogami
  • Patent number: 8074090
    Abstract: Conventionally, no consideration was given to the control of the main power supply circuit in a storage apparatus. Thus, unnecessary electric power will be consumed because it is not possible to inhibit the power consumption of the main power supply circuit of the storage apparatus. With this storage system having a plurality of storage apparatuses, a storage apparatus internally has a power supply control program for controlling the respective components and the main power supply circuit, and the power supply control command program provided to the management computer migrates a storage extent to be used for business to another storage apparatus based on the operation schedule of business to use the storage extent of the storage apparatus, and commands the power supply control of the main power supply circuit in the storage apparatuses and the respective components.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: December 6, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Hirotaka Nakagawa, Masayasu Asano, Yuichi Taguchi, Masayuki Yamamoto
  • Patent number: 8074087
    Abstract: Controlling processors and processor hardware components in a computing device based on execution load and a power saving preference. The power saving preference relates to responsiveness of the processors versus power consumption of the processors to manage battery life of the device. The processors and processor hardware components may be powered on and off based on a determined execution load for the processors and based on the power saving preference. For example, arithmetic logic units, caches, vectorization units, and units for graphics or multimedia support may be individually enabled or disabled based on the execution load and the power saving preference.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: December 6, 2011
    Assignee: Microsoft Corporation
    Inventor: Chetley T. Laughlin
  • Patent number: 8069359
    Abstract: A system and method for establishing and dynamically controlling energy consumption in large-scale datacenters or IT infrastructures. The system including a primary configuration server, a router coupled to the primary configuration server, and a plurality of power-managed domains/clusters coupled to the router. The primary configuration server distributes an energy target to each of the power-managed domains/clusters over a predetermined interval to enable each of the power-managed domains/clusters to manage the power consumption for each of the power-managed domains/clusters to meet the energy target.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: November 29, 2011
    Assignee: Intel Corporation
    Inventor: Matthew E. Tolentino
  • Patent number: 8069355
    Abstract: A data path controller, a computer device, an apparatus and a method are disclosed for integrating power management functions into a data path controller to manage power consumed by processors and peripheral devices. By embedding power management within the data path controller, the data path controller can advantageously modify its criteria in-situ so that it can adapt its power management actions in response to changes in processors and peripheral devices. In addition, the data path controller includes a power-managing interface that provides power-monitoring ports for monitoring and/or quantifying power consumption of various components. In one embodiment, the data path controller includes a power-monitoring interface for selectably monitoring power of a component.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: November 29, 2011
    Assignee: NVIDIA Corporation
    Inventors: Brad W. Simeral, David G. Reed, Dmitry Vyshetsky, Roman Surgutchik, Robert William Chapman, Joshua Titus, Anand Srinivasan, Hari U. Krishnan
  • Patent number: 8065543
    Abstract: A method, apparatus, article of manufacture, and system, the method including, in some embodiments, determining an impedance of a power distribution network of a load for a range of frequencies, and adjusting a functionality of the load based on a relationship between the impedance of the power distribution network for the range of frequencies and the functionality of the load.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: November 22, 2011
    Assignee: Intel Corporation
    Inventors: Frank William Kern, Edward Stanford
  • Patent number: 8065538
    Abstract: A method and apparatus for power management of a network element. In one embodiment of the invention, a networking card configuration request is received for a type of networking card irrespective of a networking card of that type being inserted into the network element. The network element does not enable networking cards unless they are successfully configured and inserted. The amount of power that the networking card consumes is determined without reading a power consumption value from that card. If it is determined that allowing that type of networking card to be configured would exceed the power capacity of the network element, the configuration request is denied and the networking card, if or when inserted remains disabled and is not powered up. However, if allowing that type of networking card to be configured would not exceed the power capacity, the configuration request is accepted, the amount of power that type of networking card consumes is allocated, and the card will be enabled when inserted.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: November 22, 2011
    Assignee: Telefonaktiebolaget L M Ericsson (Publ)
    Inventor: Camilla L. Odlund
  • Patent number: 8060765
    Abstract: A power monitor for electronic devices, such as computer chips, is used to estimate the power consumption and to compare the estimated power consumption against the power budget. The estimated power consumption is based on activity signals from various functional blocks of the computer chip. The activity signals that are monitored correlate accurately to the total number of flip-flops that are active at a given time. If the estimated power consumption exceeds the power budget, the speed of the clock signals supplied to the computer chip is reduced.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: November 15, 2011
    Assignee: NVIDIA Corporation
    Inventors: Hungse Cha, Robert J. Hasslen, III, John A. Robinson, Sean J. Treichler, Abdulkadir Utku Diril
  • Patent number: 8054160
    Abstract: Active multi-modal RFID tags, illuminator/tag/reader systems, circuit architecture and opera-tional algorithms for battery power conservation that extends tag battery life from a typical 6 months to >5 years. The inventive system is particularly useful in asset and person tracking/inventory systems where power conservation is critical. The tag is configured with a micro-processor operational instruction set algorithm, modifiable on the fly via RF or IR, to synchro-nize a periodic tag awaken/sense envelope that overlaps the illuminator trigger pulse cycle and put the tag into deep, power conservation sleep for N periods of illuminator cycles. When the tag sees an illuminator signal with a different ID, or no illuminator signal at all, it transmits that anomaly via RF to a reader. This means the object or person with which the tag is associated has been moved out of the original illuminator field of view, permitting near real time investigation and tracking.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: November 8, 2011
    Assignee: Innovation Law Group, Ltd.
    Inventors: Anthony P. Corrado, Rex T. Logan
  • Patent number: 8051310
    Abstract: A method for reducing power consumption of a processor is disclosed comprising steps of applying time-frequency transformation to a plurality of load values of the processor to obtain the feature sampling cycle of the processor, and adjusting the voltage/frequency of the processor based on said feature sampling cycle. With the method of the present invention, the processor load value in next time interval can be accurately predicted, and thus the voltage/frequency of the processor in the next time interval can be adjusted on the basis of the load value.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: November 1, 2011
    Assignee: Lenovo (Beijing) Limited
    Inventors: Zhiqiang He, Zihua Guo
  • Patent number: 8051312
    Abstract: An integrated circuit includes an energy controller that generates a power supply voltage level for the integrated circuit based on a desired target frequency value for the integrated circuit. The energy controller configures a programmable hardware process sensor based on the power supply voltage level such that the programmable hardware process sensor is capable of mimicking the electrical characteristics of a predetermined critical path associated with the integrated circuit when operating at the power supply voltage level. By monitoring the frequency of the programmable hardware process sensor over a period of time, the energy controller can compare the monitored frequency to an expected value and determine whether the power supply voltage level can be adjusted or whether it should be maintained.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: November 1, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Denis Foley
  • Patent number: 8046598
    Abstract: A device capable of controlling a supply voltage and a supply frequency using information of a manufacturing process variation includes a data storage device storing data indicating performance of the device, a decoder decoding the data stored in the data storage device and outputting decoded data, and a frequency control block outputting a frequency controlled clock signal in response to the decoded data output from the decoder. The device further includes a voltage control block outputting a level controlled supply voltage in response to the decoded data. The voltage control block outputs a body bias control voltage controlling a body bias voltage of at least one of a plurality of transistors embodied in the semiconductor device in response to the decoded data. The performance is operational speed of the device or leakage current of the semiconductor device.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: October 25, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong Pil Lee
  • Patent number: RE43211
    Abstract: A system which includes a disk drive or other storage device coupled to a host system provides for reduction of the amount or rate of drive power consumption using procedures which are at least partially executed on the host. The system can be configured to reduce average power draw, maximum power draw, or both. Host-based procedures can be tailored to specific and/or changing environments and can decrease some or all expenses associated with previous attempts to reduce HDD power consumption.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: February 21, 2012
    Assignee: Seagate Technology LLC
    Inventor: Maurice Schlumberger
  • Patent number: RE43222
    Abstract: A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: March 6, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Masashi Horiguchi, Mitsuru Hiraki