Particular Stimulus Creation Patents (Class 714/32)
  • Publication number: 20130246851
    Abstract: An information processing apparatus may include a sender apparatus and a receiver apparatus connected to the sender apparatus. The sender apparatus includes a processor configured to output a plurality of output signals, a counter configured to send a report indicating that a predetermined time has been counted, and a pseudofault generator configured to change a value of any one of the output signals output by the processor based on the report sent from the counter. The receiver apparatus includes an error detector configured to detect an error with respect to the changed value of the one of the output signals output by the processor.
    Type: Application
    Filed: May 14, 2013
    Publication date: September 19, 2013
    Applicant: FUJITSU LIMITED
    Inventor: Yoshitsugu Goto
  • Publication number: 20130246850
    Abstract: A network communication system includes a central control system that may transmit a request packet over a network to an apparatus that is configured to operate in an alarm system. The alarm system may be configured in accordance with a standard or protocol. The request packet may include instructions that instruct the apparatus to perform one or more tests that determine whether the apparatus is compliant with the standard or protocol. The apparatus may be configured to receive the packet from over the network and perform the tests in accordance with the instructions. The apparatus may report test results of the tests to the central control system by sending a reply packet that includes the test results over the network to the central control system.
    Type: Application
    Filed: March 13, 2012
    Publication date: September 19, 2013
    Applicant: Harman International Industries, Incorporated
    Inventors: Aaron Gelter, Jeffrey L. Hutchings, Robert Boatright
  • Patent number: 8538720
    Abstract: A cold boot test system and method can control an electronic device to perform a cold boot process to test whether the electronic device is operable. The method sets time parameters for a test period of the cold boot process, drives a data communication interface of a computer to generate a period control signal according to the time parameters, and sends the period control signal to a controller via the data communication interface. The method further transfers the period control signal to the electronic device by controlling a power switch to switch on and switch off, controls the electronic device to execute the cold boot process to generate test information correspondingly. In addition, the method obtains the test information from the electronic device, and displays the test information on a display screen of the computer upon the condition that the cold boot process is abnormal.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: September 17, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Ming-Yuan Hsu
  • Patent number: 8539289
    Abstract: In a memory testing method for testing a memory module of a computing device, an operating voltage of the memory module is adjusted to a first voltage or a second voltage. A predetermined data set is written into the memory module after the operating voltage of the memory module is adjusted, and the written data set is read out from the memory module, to accomplish a data writing and reading process of the memory module. A register value that presents how many memory errors have occurred during the data writing and reading process is acquired from an ECC register of the memory module, to determine whether the memory module is stable during the adjusting of the operating voltage according to the register value.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: September 17, 2013
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Jie-Jun Tan, Yu-Long Lin, Hua Dong
  • Publication number: 20130238935
    Abstract: Methods and devices for testing a physical layer (PHY) of an asymmetrical interconnect interface using a traffic generator/analyzer (TGA) are described. At least one special PHY test sequence is transmitted to the asymmetrical interconnect interface during link start up to place the device under test in PHY testing mode in which the TGA is used to generate and analyze data. The asymmetrical interconnect interface can then receive a configuration command and configure the asymmetrical interconnect interface in response to the configuration command. The asymmetrical interconnect interface can then use the TGA to transmit test sequences to, or receive test sequences from, e.g., a tester, on at least one identified lane of the asymmetrical interconnect device, which at least one identified lane is set by the configuration command.
    Type: Application
    Filed: October 14, 2011
    Publication date: September 12, 2013
    Inventor: Andrei Radulescu
  • Patent number: 8527813
    Abstract: Systems and methods are described that dynamically reprioritize test cases for Model-Based Testing (MBT) during test execution. Test case execution is prioritized according to their potential to detect uncovered failures within a design model.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: September 3, 2013
    Assignee: Siemens Aktiengesellschaft
    Inventors: Christof Budnik, Rajesh Subramanyan
  • Patent number: 8522080
    Abstract: This invention relates to error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: August 27, 2013
    Assignee: Emulex Design & Manufacturing Corporation
    Inventors: Bruce Gregory Warren, Carl Joseph Mies, William Eugene Morgan, William Patrick Goodwin
  • Publication number: 20130219219
    Abstract: Customizing a test instrument. A plurality of pairs of code modules may be provided. Each pair of code modules may include a first code module having program instructions for execution by a processor of the test instrument and a second code module for implementation on a programmable hardware element of the test instrument. For each pair of code modules, the first code module and the second code module may collectively implement a function in the test instrument. User input may be received specifying modification of a second code module of at least one of the plurality of pairs of code modules. Accordingly, a hardware description may be generated for the programmable hardware element of the test instrument based on the modified second code module.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 22, 2013
    Inventors: Charles G. Schroeder, Christopher F. Graf, Ciro T. Nishiguchi, Nigel G. D'Souza, Daniel J. Baker, Thomas D. Magruder
  • Publication number: 20130219222
    Abstract: The embodiments described herein include a host that includes an operating system and a storage simulation module in communication with the host. The storage simulation module includes a pseudo-adapter configured to emulate a storage adapter and a pseudo-storage device coupled to the pseudo-adapter, wherein the pseudo-storage device is configured to emulate a storage device. The storage simulation module is configured to simulate an error event for the pseudo-adapter and/or the pseudo-storage device upon receipt of an operation from the operating system.
    Type: Application
    Filed: February 8, 2013
    Publication date: August 22, 2013
    Inventor: VMware, Inc.
  • Publication number: 20130219221
    Abstract: The embodiments described herein include a host that includes an operating system and a storage simulation module in communication with the host. The storage simulation module includes a pseudo-adapter configured to emulate a storage adapter and a pseudo-storage device coupled to the pseudo-adapter, wherein the pseudo-storage device is configured to emulate a storage device. The storage simulation module is configured to simulate an error event for the pseudo-adapter and/or the pseudo-storage device upon receipt of an operation from the operating system.
    Type: Application
    Filed: February 8, 2013
    Publication date: August 22, 2013
    Applicant: VMWARE, INC.
    Inventor: VMWARE, INC.
  • Publication number: 20130219220
    Abstract: A method for generating a replayable testing script for iterative use by an automated testing utility may include recording a plurality of scripts, each script relating to a separate iteration of a transaction between a user and a tested application performed by an operator. The method may also include comparing the recorded scripts to identify a location of a data item by finding different values in a pair of corresponding locations in the recorded scripts, indicative of a dynamic data item. The method may further include generating the replayable testing script comprising one of the recorded scripts and having a variable parameter at the identified location of the dynamic data item.
    Type: Application
    Filed: February 17, 2012
    Publication date: August 22, 2013
    Inventors: Moshe Eran Kraus, Lior Manor, Amichai Nitsan, Meidan Zemer
  • Patent number: 8516297
    Abstract: A copy export application implemented in a computational device receives a request to perform a copy export operation of data and metadata to a selected tape in a tape library coupled to the computational device. The copy export application copies the data from the computational device to the selected tape. The copy export application determines a medium error on the selected tape while copying the metadata from the computational device to the selected tape, subsequent to completion of the copying of the data from the computational device to the selected tape. The copy export application sends a request to a tape control application to replace the selected tape by a new tape and copy the data from the selected tape to the new tape. The copy export application copies the metadata to the new tape.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Norie Iwasaki, David Michael Morton, Yun Mou, Laura Jean Ostasiewski, Takeshi Sohda
  • Patent number: 8516305
    Abstract: Dynamic power test slave (DPTS) modules are placed at selected locations of a data processing device to provide data to a logic module of the device at a high rate during testing of the device. The DPTS module intercepts data requests targeted to another logic module and the DPTS instead provides the requested data, thus simulating data transfer by the target logic module. The simulated data transfers can provide for transitions at the data processing device from a relatively high power state to a relatively low power state. Accordingly, the DPTS modules allow for simulation of expected normal operating conditions during testing of the data processing device.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: August 20, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sebastien Nussbaum, Guhan Krishnan
  • Publication number: 20130212435
    Abstract: Integrated fuzzing techniques are described. A fuzzing system may employ a container configured as a separate component that can host different target pages to implement fuzzing for an application. A hosted target file is loaded as a subcomponent of the container and parsed to recognize functionality of the application invoked by the file. In at least some embodiments, this involves building a document object model (DOM) for a browser page and determining DOM interfaces of a browser to call based on the page DOM. The container then operates to systematically invoke the recognized functionality to cause and detect failures. Additionally, the container may operate to perform iterative fuzzing with multiple test files in an automation mode. Log files may be created to describe the testing and enable both self-contained replaying of failures and coverage analysis for multiple test runs.
    Type: Application
    Filed: February 14, 2012
    Publication date: August 15, 2013
    Applicant: MICROSOFT CORPORATION
    Inventors: Jiong Qiu, Michael Allan Friedman, Charles Patrick Mann, Kwan-Leung Chan, Jeremy Lynn Reed
  • Patent number: 8510593
    Abstract: A control apparatus includes a lower layer control unit configured to perform control of a load, an upper layer control unit configured to control the lower layer control unit, a communication unit configured to perform communication between the upper layer control unit and the lower layer control unit via a communication line, a detection unit configured to detect power supply voltage of the lower layer control unit, wherein the upper layer control unit detects communication abnormality of the communication unit and notifies the communication abnormality, the upper layer control unit notifying abnormality of power supply voltage of the lower layer control unit, in such a manner as to be identified from the communication abnormality of the communication unit.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: August 13, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Noriaki Adachi
  • Publication number: 20130198568
    Abstract: In an exemplary embodiment, a system includes a memory and a processor communicatively coupled to the memory. The processor is operable to receive a first indication that a first action keyword is selected from a plurality of action keywords and determine whether a first object requirement is associated with the first action keyword. The processor is further operable to retrieve a plurality of action objects and receive a second indication that a first action object is selected. The processor is also operable to receive a third indication that a second action keyword is selected and determine whether a first input parameter is associated with the second action keyword. The processor may also be operable to request a first user input, receive the first user input, generate a test case file comprising the first action keyword and the second action keyword, and associate the test case file with an application.
    Type: Application
    Filed: January 31, 2012
    Publication date: August 1, 2013
    Applicant: Bank of America Corporation
    Inventors: Istiak Ahmed, Shanmugaraja Senthilnayagam
  • Publication number: 20130198567
    Abstract: In an exemplary embodiment, a system includes a memory and a processor communicatively coupled to the memory. The processor is operable to receive a first indication that a first component is selected from a plurality of components and receive a second indication that a second component is selected from the plurality of components. The processor is further operable to determine a first instruction associated with the first component, wherein the first instruction corresponds to first computer logic for executing the first at least one test action, and determine a second instruction associated with the second component, wherein the second instruction corresponds to second computer logic for executing the second at least one test action. The processor is also operable to generate a test case file comprising the first instruction and the second instruction and associate the test case file with an application under test.
    Type: Application
    Filed: January 31, 2012
    Publication date: August 1, 2013
    Applicant: Bank of America Corporation
    Inventors: Istiak Ahmed, Shanmugaraja Senthilnayagam
  • Publication number: 20130198569
    Abstract: Embodiments are directed to a method of embedding configuration files in a document generated by a system, with the configuration file including settings associated with the generation of the document. A particular embodiment is directed to the embedding of configuration files of a testing system in a report document generated by the testing system. The configuration file includes system settings and external settings in association with the test results documented in the report document. For example, a testing system can generate a PDF report document associated with a test performed, and embed configuration files into the PDF report document. The embedding of configurations files in the PDF document can be done by using standard embedding mechanisms already available in the PDF file format and supported by most PDF viewing tools. The embedding of the configuration file can be performed automatically when the report document is generated.
    Type: Application
    Filed: February 1, 2012
    Publication date: August 1, 2013
    Applicant: EMPIRIX INC.
    Inventor: Sergey Eidelman
  • Patent number: 8499286
    Abstract: In one embodiment, a method for testing adjustment and configuration is disclosed. The method can include accessing source code of a test framework that is configured for testing a module, creating a configuration folder having a property override for a test suite for the module testing, determining a source root folder for the test suite, starting the test framework by passing in an identifier for the test suite, and adding a custom test to the source root folder using the configuration folder to customize the test suite. The method can further include compiling the test framework with each of the plurality of test folders enabled. The method also may use a refactoring tool to make changes in a file within the test framework.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: July 30, 2013
    Assignee: salesforce.com, inc.
    Inventors: Steven S. Lawrance, Marcus Ericsson
  • Publication number: 20130191688
    Abstract: In one embodiment, a computing device (e.g., border router or network management server) transmits a discovery message into a computer network, such as in response to a given trigger. In response to the discovery message, the device receives a unicast reply from each node of a plurality of nodes in the computer network, each reply having a neighbor list of a corresponding node and a selected parent node for the corresponding node. Based on the neighbor lists from the replies and a routing protocol shared by each of the plurality of nodes in the computer network, the device may create a reference topology for the computer network, and based on the selected parent nodes from the replies, may also determine a current topology of the computer network. Accordingly, the device may then compare the current topology to the reference topology to detect anomalies in the current topology.
    Type: Application
    Filed: January 25, 2012
    Publication date: July 25, 2013
    Applicant: Cisco Technology, Inc
    Inventors: Navneet Agarwal, Jean-Philippe Vasseur, Ajay Kumar
  • Patent number: 8494831
    Abstract: A simulator is partitioned into a functional component and a behavior prediction component and the components are executed in parallel. The execution path of the functional component is used to drive the behavior prediction component and the behavior prediction component changes the execution path of the functional component.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: July 23, 2013
    Inventor: Derek Chiou
  • Patent number: 8489943
    Abstract: A system for generating test signals to test characteristics of input-output (IO) cells includes a memory and a processor coupled together through an integrated circuit (IC) chip. The IC chip includes a controller configured to exchange signals between the memory and the processor through IO cells of the IC chip. The IC chip further includes a protocol sequence generator for generating test signals for testing characteristics of the IO cells.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: July 16, 2013
    Assignee: STMicroelectronics International N.V.
    Inventors: Anil K. Dwivedi, Akhilesh Chandra, Ajay Arun Kulkarni
  • Patent number: 8489926
    Abstract: The present disclosure generally relates to the testing of a system that includes software or hardware components. In some embodiments, a testing framework generates a set of test cases for a system under test using a grammar. Each test case may perform an action, such as provide an input to the system under test, and result in an output from the system under test. The inputs and outputs are then compared to the expected results to determine whether the system under test is performing correctly. Prior to generating the set of test cases from the grammar, the testing framework processes the grammar to identify attributes of the test cases to be derived from the grammar and facilitates the modification of the grammar.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: July 16, 2013
    Assignee: Wurldtech Security Technologies
    Inventors: Nathan John Walter Kube, Daniel Hoffman, Kevin Yoo
  • Publication number: 20130179734
    Abstract: Systems and methods for generating and traversing test cases trees are provided. A test case tree indicates an order of execution for multiple test cases, where setup and tear down or equivalent steps are not required before and after execution of each test case in the tree. The tree may allow for generation of virtual test cases to encompass multiple test cases which ordinarily would have mutually exclusive execution requirements.
    Type: Application
    Filed: January 11, 2012
    Publication date: July 11, 2013
    Applicant: Neopost Technologies
    Inventors: Robert W. Perin, Garret Blue
  • Publication number: 20130173962
    Abstract: A test system for a managed cloud computing environment may have a management system that may recruit devices in the cloud and outside the cloud to perform a test on a cloud based application. Each device may execute an agent that connects the device to several cloud services for messaging, data collection, and executable code storage. The management system may identify and gather the devices, then cause the devices to execute a test by sending commands through the messaging service. The devices may access executable code for the specific tasks of a test through the code storage service, and as the devices complete tasks for the test, the devices may publish results in the data collection service. The test system enables any type of scenario to be implemented, including operations that can only be performed inside and outside the managed cloud environment.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 4, 2013
    Applicant: Microsoft Corporation
    Inventors: Zhuowei Li, Muthu A.K. Jagannathan, Dong Wei
  • Publication number: 20130173961
    Abstract: A memory-leak source in a data structure can be identified by counting insertions into the data structure and deletions from the data structure for locations in the execution path of a computer program. These insertion and deletion values can be used to identify at least one location as a memory-leak source that corresponds to an imbalance between insertions and deletions during the execution of the computer program.
    Type: Application
    Filed: December 28, 2011
    Publication date: July 4, 2013
    Applicant: SAP AG
    Inventor: Martin Moser
  • Publication number: 20130166955
    Abstract: A keyboard automatic test method is provided. A keyboard test unit first outputs a key test command to a keyboard controller. The key test command represents a trigger element of a keyboard is triggered. The keyboard controller generates a corresponding code corresponding to the trigger element. The keyboard test unit then determines whether a relationship between the corresponding code and the trigger element is correct.
    Type: Application
    Filed: April 16, 2012
    Publication date: June 27, 2013
    Applicant: Wistron Corporation
    Inventors: Wen-Chun Tsao, Yu-Wei Tsao
  • Publication number: 20130159772
    Abstract: Verifying speculative multithreading in an application executing in a computing system, including: executing one or more test instructions serially thereby producing a serial result, including insuring that all data dependencies among the test instructions are satisfied; executing the test instructions speculatively in a plurality of threads thereby producing a speculative result; and determining whether a speculative multithreading error exists including: comparing the serial result to the speculative result and, if the serial result does not match the speculative result, determining that a speculative multithreading error exists.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 20, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Mitchell D. Felton
  • Publication number: 20130159773
    Abstract: An information processing apparatus includes a plurality of controller modules capable of performing communications with each other, and a memory included in each controller module to be stored with status information reflecting a status of an error occurring during the communications with other controller modules with respect to the controller module of a communication partner apparatus and/or the controller module of the self-apparatus, wherein, when determining whether or not a fault occurs in a certain controller module in the plurality of controller modules, the controller module different from a determination target controller module determines, based on status information of the determination target controller module that is stored on the memories of two or more controller modules different from the determination target controller module, whether the fault occurs in the determination target controller module.
    Type: Application
    Filed: October 24, 2012
    Publication date: June 20, 2013
    Inventor: FUJITSU LIMITED
  • Publication number: 20130151905
    Abstract: Methods and test systems for testing a network. A test system may emulate a plurality of users, each emulated user executing a user activity. Each emulated user activity may include one or more commands. At least some emulated user activities may include a command randomly selected from a predefined command pool in accordance with an associated probability distribution. The test system may report a result of emulating the plurality of users.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 13, 2013
    Inventors: Soumyajit Saha, Rudrarup Naskar, Luis Cazacu
  • Patent number: 8458522
    Abstract: Model-based testing is performed by repeatedly constructing a test strategy in which each test stimulus will lead to increased test coverage regardless of the nondeterministic choices made by the system under test, and following said strategy until coverage is increased. As soon as no such strategy exists, testing stops.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: June 4, 2013
    Assignee: Microsoft Corporation
    Inventor: Ernest S. Cohen
  • Publication number: 20130139004
    Abstract: Provided is a test module generation apparatus that generates a test module executed on a test apparatus for testing a device under test. The apparatus includes a condition file generating section in which a test condition is input and that generates a condition file specifying the input test condition, a test method storing section that stores a test method, a test method selecting section that receives, from a user, a selection instruction of the test method adapted to the test module to be generated, a condition file selecting section that receives, from a user, a selection instruction of the condition file corresponding to a parameter which the selected test method requires, and a test module generating section that generates the test module in which a test according to the selected test method is executed with a parameter specified by the condition file.
    Type: Application
    Filed: October 19, 2012
    Publication date: May 30, 2013
    Applicant: ADVANTEST CORPORATION
    Inventor: ADVANTEST CORPORATION
  • Publication number: 20130139003
    Abstract: Systems and methods for test data generation are described. In one implementation, the method includes receiving seed data having one or more characteristics. Further, the method includes obtaining a selection criterion indicating a selected portion of the seed data to be transformed. Based on the selection criterion, the seed data is transformed for at least a plurality of iterations to generate test data. The test data comprise a plurality of data sets including a primary data set generated in a first iteration and a secondary data set generated in each subsequent iteration. The primary data set includes transformed data corresponding to the selected portion of the seed data and non-transformed data corresponding to a remaining portion of the seed data and each secondary data set includes transformed data corresponding to the selected portion of the seed data.
    Type: Application
    Filed: March 23, 2012
    Publication date: May 30, 2013
    Applicant: TATA CONSULTANCY SERVICES LIMITED
    Inventors: Nikhil Girish PATWARDHAN, Ashim ROY, Moksha Suryakant JIVANE, Varsha JAGTAP, Eeti SANCHETI, Nandita BABU
  • Publication number: 20130132774
    Abstract: A system and method for performing automated testing of an application in a cloud environment. A controller initializes an manages a number of virtual machines (VM), each VM including a test engine. The controller retrieves configuration data, determines a number of VMs to deploy, and initializes the VMs. The controller manages each VM by providing test commands and monitoring the results. Each VM receives and executes the test commands. The system may be used to test interactive applications or non-interactive applications.
    Type: Application
    Filed: November 23, 2011
    Publication date: May 23, 2013
    Applicant: Microsoft Corporation
    Inventor: Aruna Somendra
  • Patent number: 8443239
    Abstract: The invention provides a highly resilient network infrastructure that provides connectivity between a main network such as the Internet and a subnetwork such as a server-based (e.g., web server) local area network. In accordance with the invention, a network interface incorporated into a server hosting center provides a resilient architecture that achieves redundancy in each of three different layers of the Open System Interconnect (OSI) stack protocol (i.e., physical interface, data link, and network layers). For every network device that is active as a primary communication tool for a group of subnetworks, the same device is a backup for another group of subnetworks. Based on the same connection-oriented switching technology (e.g., asynchronous transfer mode (ATM)) found in high-speed, broadband Internet backbones such as that provided by InternetMCI, the network interface architecture provides a high degree of resiliency, reliability and scalability.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: May 14, 2013
    Assignee: Verizon Business Global LLC
    Inventor: Kaustubh Phaltankar
  • Publication number: 20130117609
    Abstract: System and method for generating an enhanced test case for a computer application is disclosed. The system provides a test preparation engine including an entity extracting module and an assembly extractor for collecting information about the computer application and corresponding database schema for generating a global report. The test case designing module designs one or more test cases by using the global report. The test case execution engine includes an input evaluation module and generates an actual result for each executed test case and an expected result for one or more database query. The report generating module includes a result storage device, a result comparator and a result analyses module and performs analyses of the actual test case result and the expected results.
    Type: Application
    Filed: December 14, 2011
    Publication date: May 9, 2013
    Applicant: TATA CONSULTANCY SERVICES LIMITED
    Inventors: Madhu Dande, RameshKumar Perumal
  • Publication number: 20130117608
    Abstract: A method and system for determining the accuracy of a mesoscale weather model comprising at least one processor having at least one input for inputting a preexisting weather model and initial weather data comprising surface level and upper air temperatures and wind conditions, and actually measured surface level and the upper-air level weather conditions; the at least one processor operating to use the mesoscale weather model to generate output data comprising forecasted temperatures, wind conditions, and predicted weather conditions; the at least one processor operating to compare the output data to actually measured data obtained when same or similar initial weather data were present and subsequent resulting temperatures, wind conditions and weather conditions were measured; and the at least one processor operating to generate an accuracy rating reflecting the deviation of temperature, wind conditions and weather conditions predicted by the mesoscale weather model as compared to those actually measured.
    Type: Application
    Filed: November 7, 2011
    Publication date: May 9, 2013
    Applicant: US GOVT AS REPRESENTED BY SECRETARY OF THE ARMY
    Inventor: Stephen F. Kirby
  • Publication number: 20130117610
    Abstract: In order to rapidly perform verification processing on the basis of test patterns in a circuit to be verified, an emulator verification system comprises: an emulator verification device that verifies the normality of content to be executed on the basis of verification test information in a circuit to be verified; a moveable test pattern storage device that is connected to the emulator verification device in an attachable/detachable manner, and that inputs test information for verification processing having a larger volume than a preset data volume into the emulator verification device; and a moveable result pattern storage device that connects to the emulator verification device in an attachable/detachable manner, and that acquires and stores verification results information having a larger volume than a fixed data volume, which shows the results of the verification processing in the emulator verification device.
    Type: Application
    Filed: July 1, 2011
    Publication date: May 9, 2013
    Applicant: NEC CORPORATION
    Inventor: Shin Nakamura
  • Patent number: 8438425
    Abstract: In one aspect, a method of testing a device for use in a storage area network (SAN) system includes receiving recorded messages including messages from a host and from a storage array and messages to a host and to a storage array, sending the recorded messages from the host and the storage array to a device under test, receiving messages from the device under test in response to the recorded messages sent and determining whether the device under test functions identically to a validated device based on the messages from the device under test being substantially identical to the recorded messages.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: May 7, 2013
    Assignee: EMC (Benelux) B.V., S.A.R.L.
    Inventors: Yuval Aharoni, Saar Cohen, Nir Goldschmidt
  • Publication number: 20130111266
    Abstract: An error detection method is to detect an error in a program to control hardware, which executes predetermined processing, via a register. The error detection method includes: outputting a signal indicating whether the predetermined processing is in execution; detecting that a change is made in a register value in the register, which register value is related to control of the predetermined processing, and outputting a detection signal; and detecting an error when it is detected, based on the signal indicating whether the predetermined processing is in execution and on the detection signal, that the change is made in the register value while the predetermined processing is in execution.
    Type: Application
    Filed: October 23, 2012
    Publication date: May 2, 2013
    Inventor: Ryoh TOSAKA
  • Publication number: 20130111269
    Abstract: An inspection method for assisting in search of a first program which causes overloading in a computer is disclosed. The method comprises: (A) setting an upper-limit variable, a lower-limit variable, and a middle variable equaling a first outcome of computation according to a formula H; (B) setting a third program with its priority index equaling the middle variable; (C) setting the upper-limit variable equaling the middle variable and then the middle variable equaling a second outcome of computation according to the formula H, if the third program is run by the computer; otherwise, setting the lower-limit variable equaling the middle variable and then the middle variable equaling the second outcome; (D) repeating the steps (B) and (C), until the difference between the upper-limit or lower-limit variable and the middle variable satisfies a first predetermined value; and (E) outputting the value of the middle variable.
    Type: Application
    Filed: September 12, 2012
    Publication date: May 2, 2013
    Applicant: ACCTON TECHNOLOGY CORPORATION
    Inventor: SZU-CHENG WU
  • Publication number: 20130111268
    Abstract: A testing device is capable of simulating plugging and unplugging operations in relation to an USB port of an electronic device. The testing device comprises a processing unit to detect an electrical connection between the testing device and the USB port, and to control an indicator to cycle between a state of recognizability and a state of unrecognizability even though a physical connection to the USB port of the electronic device exists at all times. The state of recognizability indicates the testing device is capable of being recognized by the electronic device, and the state of unrecognizability indicates the testing device is incapable of being recognized by the electronic device. Reading and writing tests are carried out by the testing device each time that recognizability is indicated, to repeatedly test the integrity of the USB port being tested.
    Type: Application
    Filed: December 27, 2011
    Publication date: May 2, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventors: Yuan-Yuan GONG, Zheng-Quan PENG, Qiong CAI
  • Publication number: 20130111267
    Abstract: Provided are techniques for improving a test suite. A list of tests in a test suite is created, sorted in order of increasing run time, wherein multiple tests having a same run time are sorted in order of decreasing code block coverage. For each test on the list, it is determined whether the test covers one or more code blocks not already covered by at least one previously processed test. In response to determining that the test does cover one or more code blocks not already covered by the at least one previously processed test, the test is added to an optimized test suite. The optimized test suite is stored.
    Type: Application
    Filed: November 1, 2011
    Publication date: May 2, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dmitriy BERYOZA, Hendrik CAZEMIER, David C. CUMMINGS, Joseph P. FOURNY, Robin N. GROSSET, Roch LEFEBVRE, Richard PIGEON, Glen M. SEEDS, Qing WEI
  • Patent number: 8433964
    Abstract: Provided is a test apparatus comprising a synchronization module that operates according to a reference clock and outputs a synchronization signal with a prescribed period, and a test module that operates according to a high-frequency clock with a frequency that is n times a frequency of the reference clock. The test module includes a period emulator that emulates the synchronization signal, a phase shifter that shifts a phase of the high-frequency clock by an amount equal to a result of (i) the product of n and the emulated synchronization phase data by (ii) a period of the reference clock, and a test period generating section that generates a test period pulse signal that transitions at an edge timing of the shifted high-frequency clock and test period phase data indicating a phase difference between the test period signal and an edge timing of the test period pulse signal.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: April 30, 2013
    Assignee: Advantest Corporation
    Inventor: Tokunori Akita
  • Publication number: 20130103985
    Abstract: A method for simultaneously performing diagnosing and image downloading of a custom-configured computer is disclosed. The method includes receiving a shipping image, extracting the shipping image into a hard disk drive, partitioning a portion in a unused storage space of the hard disk drive, installing a test operating system in the portion of the hard disk drive, deleting all data corresponding to the shipping image of the hard disk drive, writing storage data of the hard disk drive into a shipping hard disk drive of at least one custom-configured computer, writing data corresponding to the shipping image in a network server into the shipping hard disk drive during the test operating system performs diagnosing of the custom-configured computer, and writing a master boot record corresponding to the shipping image into the shipping hard disk drive.
    Type: Application
    Filed: January 12, 2012
    Publication date: April 25, 2013
    Inventors: Sheng-Pao Huang, Xiaobin Ma
  • Publication number: 20130103986
    Abstract: A method for functional testing of a power device with an associated software control system includes referencing a dynamic linked library (DLL) file belonging to a software package via a method of a class; instantiating an object of the class in functional testing software; and including a call to the method of the object in the functional testing software, wherein the call to the method executes a function of the referenced DLL, such that the referenced DLL comprises an implementation of the class.
    Type: Application
    Filed: February 24, 2012
    Publication date: April 25, 2013
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Xiaojing Yan, Ellery Lewis Horton
  • Patent number: 8429466
    Abstract: The testing of services techniques include a method, a system, and a non-transitory computer-readable storage medium. In some embodiments of these techniques, the method includes receiving a first payload generated by a first service. The first service transmits the first payload to a system. The method further includes receiving a second payload from a second service. The second payload is generated based on data received from the first service. The method further includes receiving a schema associated with the second payload. The schema is configured to define the structure of the second payload. The method further includes determining one or more discrepancies between the second payload and the first payload using the schema associated with the second payload. The method further includes determining a testing result based on the one or more discrepancies. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: April 23, 2013
    Assignee: SAP AG
    Inventors: Rene Laengert, Michael Spengler
  • Patent number: 8429457
    Abstract: An apparatus and method are provided for performing verification tests for a design of a data processing system. The apparatus comprises a system under verification representing at least part of the design of the data processing system, and a transactor for connecting to an interface of the system under verification, and for generating signals for input to the system under verification via the interface during performance of the verification tests. Profile storage stores a profile providing a statistical representation of desired traffic flow at the interface, the statistical representation providing statistical information for a plurality of traffic attributes and also identifying at least one dependency between such traffic attributes. The transactor then references the profile in order to determine the signals to be generated, such that the signals generated take account of the specified dependencies identified in the profile.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: April 23, 2013
    Assignee: ARM Limited
    Inventors: Antony John Harris, Simon Crossley, Alistair Crone Bruce
  • Patent number: 8423833
    Abstract: A method for monitoring the quality-of-service (QoS) of high priority transactions in a software system includes receiving a specific QoS metric of a high priority transaction, where the QoS metric associated with a plurality of buckets and comparing the sampled specific QoS metric to an expected value for the specific QoS metric. If the sampled specific QoS metric exceeds the corresponding expected value, a bucket for the specific QoS metric is incremented, otherwise the bucket is decremented. If the bucket for the specific QoS metric overflows, the current bucket is reinitialized to zero, a depth of a next bucket for the specific QoS metric is computed, and a number of standard deviations from a mean value for the specific QoS metric is incremented. When the bucket for the specific QoS metric exceeds a threshold, a software rejuvenation routine is executed.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: April 16, 2013
    Assignee: Siemens Corporation
    Inventor: Alberto Avritzer
  • Patent number: RE44487
    Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: September 10, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: William A. Hughes, Chen-Ping Yang, Greggory D. Donley, Michael K. Fertig