Abstract: A method for automatically simulating manual testing of a computer after the computer is powered on includes the steps of: (a) connecting the computer to an external storage device having a script recorded thereon that corresponds to a manual testing operation; and (b) after the computer is powered on, enabling the computer to access the script of the external storage device for performing the manual testing operation. By providing automatic simulation of manual testing of a computer after the computer is powered on, time and labor costs incurred in a conventional method of manually inputting instructions required for the manual testing operation in the computer are saved.

Abstract: The invention relates to a method for comparing variable values obtained from different versions of an application program in an automated system. An input signal obtained from an automated process is inputted to at least two different versions of the application program residing within a same controller. The same tasks are executed based on the input signal for the different versions, and process related variable values obtained from the execution of the versions are stored in memory locations known by the controller. Variable values from the different versions and derived from corresponding execution steps of the versions are retrieved from the memory locations, and compared during an idle time. An improved way of revising an automation system is thereby achieved. The invention also relates to such controller and an automation system.

Abstract: A hot button can be pressed to cause a computer to execute a series of diagnostic tests to identify the cause of poor computer performance. When a cause is determined a website address can be presented that a user can access to purchase goods or services to alleviate the cause, and billing information may be generated in response to presentation of the website.

Abstract: The testing of services techniques include a method, a system, and a non-transitory computer-readable storage medium. In some embodiments of these techniques, the method includes receiving a first payload generated by a first service. The first service transmits the first payload to a system. The method further includes receiving a second payload from a second service. The second payload is generated based on data received from the first service. The method further includes receiving a schema associated with the second payload. The schema is configured to define the structure of the second payload. The method further includes determining one or more discrepancies between the second payload and the first payload using the schema associated with the second payload. The method further includes determining a testing result based on the one or more discrepancies. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules.

Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. In particular, the techniques and systems relate to design instrumentation circuitry that facilitates the analysis, diagnosis and debugging of the hardware designs. A HDL design instrumentation circuitry embedded within an electronic system comprises one or more probe circuits to allow storage of signal values of the electronic system upon predetermined events, one or more breakpoint registers to specify the predetermined events, and one or more trigger processing units to control the storage of signal values upon the detection of the predetermined events by the breaking registers. The present design instrumentation circuitry permits monitoring the electronic system at speed, facilitating the analysis diagnosis and debugging by giving detailed and accurate information about the operation of the electronic system.

Abstract: Policy verification arrangements effecting operations of: modifying address information of system component information for all system components, stored in a system management server, to redirect-address information to a test tool as a substitute destination in order for the test tool to be able to receive a result of system management operations during testing, instead of a corresponding system component; acquiring configuration information of the information processing system from the system management server; generating a test item specifying a test event; transmitting the test event specified by the generated test item to the policy manager and/or said system management server; and recording a result of the system management operations which is requested by the policy manager and/or system management server responsive to the test event specified by the generated test item, but which is redirected back to the test tool via the redirected-address information stored in the system management server.

Abstract: In one embodiment, a system model models characteristics of a real-world system. The system model includes a plurality of sub-portions that each correspond to a component of the real-world system. A plurality of test vectors are applied to the system model and coverage achieved by the test vectors on the sub-portions of the system model is measured. In response to a failure of the real world system, a suspected failed component of the real-world system is matched to a particular sub-portion of the system model. A test vector to be applied to the real-world system to test the suspected failed component is selected in response to coverage achieved on the particular sub-portion of the system model.

Abstract: In a first embodiment of the present invention, a method for performing regression testing on a simulated hardware is provided, the method comprising: scanning a defect database for fixed signatures; retrieving all tests in a failing instance database that correspond to the fixed signatures from the defect database; running one or more of the retrieved tests; determining if any of the retrieved tests failed during running; and for any retrieved test that failed during running, refiling the failed retrieved tests in the failing instance database and placing one or more generalized signatures for the failed retrieved tests in the defect database.

Abstract: Described is automatically processing an initial database repro (text representing a bug when corresponding script is executed in a database engine) into a min-repro (a subset of the text) that is simplified version of the initial repro yet still contains the bug. A parse tree representative of the initial database repro is processed into simplified parse trees based on language grammar rules, e.g., by replacing higher level nodes with descendant nodes. Repros of the simplified parse trees are executed to determine which simplified repros still fail execution because of the bug (that is, the simplified repros were not oversimplified). A minimum simplified parse tree with respect to a desired level of minimality is found from among those failing repros, with the simplified repro that corresponds to the minimum simplified parse tree output as the min-repro.

Abstract: A method for testing financial operations of network applications within a computer network generates a test matrix to store test data relating to testing of financial operations related to the network applications within the computer network. A unique testing scenario is developed for testing the financial operations across a plurality of network applications and stored within the test matrix. An expected financial result achieved in accordance with execution of the unique testing scenario is calculated and stored within the test matrix. The unique testing scenario is executed using the network applications within the computer network to achieve an actual financial test result which is stored within the test matrix. The expected financial result is compared with the actual financial result to detect issues within the network applications relating to financial operations.

Abstract: A method, system, and computer usable program product for energy-efficient soft error failure detection and masking are provided in the illustrative embodiments. A soft error is injected to occur during execution of a set of instructions. If an output of the execution of the set of instructions is incorrect, a record is made of the instruction that was affected by the injected soft error and led to the incorrect result. This identified instruction is designated as vulnerable to the soft error. Several soft errors are injected with different input data sets over several executions of the same set of instructions, and a probability of each instruction in the instruction set is computed, the probability of an instruction accounting for the vulnerability of the execution of the instruction sets to errors that affect the instruction. A report including several probabilities of instruction vulnerabilities is produced.

Abstract: The present invention relates to a method, device, and system for managing verification of configurable hardware and software. The solution according to the present invention solves this by applying a matrix-like method of handling test and verification parameter combinations and interacting with a user using a browser like interface for simple and fast selection of coverage.

Abstract: An apparatus to collect information about network failure includes: a normal mode packet assembly unit to assemble a transmission packet from transmission data output from an application in a normal mode being a procedure used when a transmission process is performed by specified communication protocol; a special mode packet assembly unit to assemble the transmission packet from the transmission data in a special mode being a procedure in which a procedure for collecting failure information is embedded into the procedure used when a transmission process is performed by the specified communication protocol; a switching control unit to activate the normal mode packet assembly unit or the special mode packet assembly unit selectively; and a response analysis unit to collect failure information according to a behavior of the response to the transmission packet transmitted from the special mode packet assembly unit.

Abstract: There is provided a test module comprising a random number generator that generates a pseudo random pattern and includes a controller that generates a register selection signal based on a control instruction stored on an instruction memory, a plurality of polynomial configuration registers one of which is selected by the register selection signal, each polynomial configuration register having polynomial data stored therein, a plurality of initial value configuration registers one of which is selected by the register selection signal, each initial value configuration register having an initial value stored therein, and a random number generation shift register that loads the initial value from the selected one of the plurality of initial value configuration registers and sequentially generates the pseudo random pattern based on the polynomial data stored in the selected one of the plurality of polynomial configuration registers.

Abstract: A boot test apparatus and method can repeatedly execute actions of power-on and power-off for a cold boot test of a computer to test whether the computer is operable. The boot test apparatus includes a microprocessor, a controller, and a power switch. The microprocessor generates a control signal according to a period voltage provided by an internal power supply. The control signal includes a pulse signal and a voltage signal. The controller controls a power switch to send the pulse signal to the computer through a power button of the computer, and controls the power switch to send the voltage signal to the computer through a power input port of the computer. The microprocessor further obtains test information from the computer when the computer executes a cold boot process according to the control signal, and displays the test information on an LED when the cold boot process is abnormal.

Abstract: A system and method for accurately modeling a fault log is provided for validating one or more elements of fault detection and logging logic for a real-time fault log of a digital system such as, for instance, a computer processor. The method includes injecting one or more known faults into a data path and/or a control path of the computer processor and spawning an individual tracking thread for each of the injected faults. The tracking threads may be synchronized at a predefined synchronization point that is selected as a function of a collective logging delay representing the time required for each of the injected faults to reach a real-time logging point within the computer processor. Once synchronized, the tracking threads may be input into a fault logging specification for fault behavior and/or system impact modeling and fault prioritization for use in generating a fault log model for comparison to the real-time fault log maintained within the computer processor.

Abstract: An apparatus, system, and method are disclosed for validating application server replication errors. The method includes receiving a first information message with a test sequence from a caller. The caller is engaged in a communication session with a callee according to a communication protocol and the communication session is managed by a first application server. The method also includes storing the test sequence in a replicable data structure on the first application server. The replicable data structure is replicated to a second application server to form a replicated data structure and both servers operate within an active-active configuration. The method also includes receiving a second information message from the caller. The second information message includes a confirmation sequence. In addition, the method includes determining a replication error in response to comparing the stored test sequence in the replicated data structure with the confirmation sequence.

Abstract: The present invention discloses a method for fast detection of node mergers and simplification of a circuit. The steps of the method include: (a) a circuit with a large amount of nodes is provided; (b) a target node is selected for computing mandatory assignments (MAs) of the stuck-at 0 and stuck-at 1 fault tests on the target node respectively by a computer; (c) the MAs of the stuck-at 0 and stuck-at 1 fault tests of the target node are utilized to find substitute nodes; (d) the substitute node that is closest to primary inputs is used to replace the target node; and (e) the steps (b)˜(d) are repeated for removing the replaceable nodes and simplifying the circuit.

Abstract: A method and computer program product for testing a system logger. Randomized input is provided into a logging facility and automated testing of the logging facility is performed in a multi-processing environment. Self-verification of data retrieved from the logging facility is performed to ensure no data loss occurs due to external system events or failures driven by a test tool. Real-time analysis of results received is performed by the test tool based on the randomized input into the logging facility. First failure data is captured and self-verification of results of a data recovery operation of the logging facility is performed in a disaster recovery scenario. Self-verification includes writing log blocks of random sizes to the log stream, iteratively forcing log data to be offloaded from primary storage to secondary storage, iteratively updating log stream attributes, and iteratively swapping duplexing modes.

Abstract: The invention provides a test circuit for n input/output arrays. Each of the n input/output arrays has M pairs of input/output. The test circuit includes M write drivers and M comparing circuits. The ith write driver provides an ith test signal to the ith inputs of all of the n input/output arrays, and 1?i?M. The jth comparing circuit determines if jth output signals of all of the n input/output arrays are the same, and outputs a jth comparing result correspondingly, and 1?j?M. The invention also provides a method of testing n input/output arrays. The invention also provides a storage device.

Abstract: A circuit operation verification system has: a computer; a programmable logic device in which a device under test is configured; and a test bench section configured to perform operation verification of the device under test. The test bench section has: a software section that is implemented by the computer executing software; and a hardware section configured in the programmable logic device together with the device under test. The hardware section has a hardware function that generates a test pattern and inputs the test pattern to the device under test to perform the operation verification. The hardware function is controllable by changing a control parameter, and the software section variably sets the control parameter.

Abstract: A mechanism for utilizing a virtual machine cloud for automated test system deployment is disclosed. A method of embodiments of the invention includes selecting a master image used to initialize one or more virtual machines (VMs), providing a list of repository definitions and test packages to the one or more VMs, and receiving test results from executing the test packages on a computer system of the VM defined by the master image, wherein the computer system includes an operating system and one or more software applications.

Abstract: A method for generating reliability tests for a telephone system is based upon sampling an orthogonal array which covers various combinations of test parameters. Field data is collected of actual telephone activity on a telephone system. The field data is evaluated so as to determine call-mix characteristics. Probabilistic weights for the different call-mix characteristics are obtained, and then the probabilistic weights are used to sample the test case scenarios generated in the orthogonal array which have the same call-mix characteristics. These test case scenarios are used to run tests on the telephone system. These tests are preferably performed using automated test scripts. After the test data is collected, reliability metrics are calculated from the test data.

Abstract: A computer readable medium storing a program causing a computer to execute a process for verification support, the process includes: acquiring information of a timing of transmission of a process request for operating a program to-be-verified; acquiring first record information of a transfer process in a time zone corresponding to the acquired timing of the transmission, from a transfer device which transfers the process request to any of a plurality of information processing devices capable of running the program to-be-verified and which records the transfer process; specifying the information processing device to which the process request has been transferred, on the basis of the acquired first record information of the transfer process; and acquiring second record information of a process in the time zone corresponding to the timing of the transmission, from the specified information processing device.

Abstract: A high-definition multimedia interface circuit uses a high-definition multimedia interface encoder to produce a plurality of channels of data. An output circuit, connected to the high-definition multimedia interface encoder, produces a plurality of channels of high frequency data from the data produced by the high-definition multimedia interface encoder. A multiplexer selects a channel for sampling, and a capacitive coupler capacitively couples the multiplexer to a sampling circuit. The sampling circuit produces sampled data corresponding to the high frequency data having a clock rate less than a clock rate of the high frequency data. A test circuit compares the sampled data with the data produced by the high-definition multimedia interface encoder.

Abstract: Methods and systems for debugging a software program, such as BIOS is provided. The methods and systems make use of a debugger application executing on a host computer and configured to communicate with a debugger module executing on a target computer via serial/parallel/USB port of host computer, an adapter and the SMBus of the target computer.

Abstract: A method and apparatus is described for parallel debugging on the data nodes of a parallel computer system. A data template associated with the debugger can be used as a reference to the common data on the nodes. The application or data contained on the compute nodes diverges from the data template at the service node during the course of program execution, so that pieces of the data are different at each of the nodes at some time of interest. For debugging, the compute nodes search their own memory image for checksum matches with the template and produces new data blocks with checksums that didn't exist in the data template, and a template of references to the original data blocks in the template. Examples herein include an application of the rsync protocol, compression and network broadcast to improve debugging in a massively parallel computer environment.

Abstract: A test-operation control apparatus, system and method are disclosed to reduce time and cost required for test operation by automatically performing test-operation on a control point of facilities installed on site based on a previously established template sequence and operational conditions of the situation on the spot. The test-operation control apparatus includes: a storage unit configured to store a basic sequence with respect to each of one or more control points set in the facilities installed on the spot (or site); an input unit configured to selectively receive one or more of the control points and receive operational conditions of each basic sequence with respect to each of the one or more of the selected control points; and a controller configured to combine the basic sequences with respect to each of the one or more of the selected control points according to the inputted operational conditions to generate a test-operation sequence.

Abstract: A system for testing sleep and wake functions of a computer includes a test device and a test software installed on a motherboard of the computer. The test device includes a timing module, a counting module, and a switch module. The test software includes an initialization unit, a signal transmission unit, and a comparison unit. The test device communicates with the motherboard, and an operation system of the computer sets that receiving a control signal means executing an operation of putting the computer to sleep or waking the computer up. The system employs the test software cooperating with the test device to test sleep and wake functions of the computer automatically.

Abstract: Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.

Abstract: A safety output includes an output controller to make an instruction to output normal output data and first self-diagnosis pattern data synchronously with a control cycle, a normal output unit to output the normal output data synchronously with the control cycle, a test pattern generating unit to encode the self-diagnosis pattern data into a pulse train signal having a pulse width not larger than a preset value and output the pulse train signal in accordance with a baseband transmission system, a combination output unit to combine the pulse train signal with the normal output signal and output the resultant signal, a reconfiguration unit to decode the inputted operation-terminal-portion output signal to reconfigure the operation-terminal-portion output signal as second self-diagnosis pattern data, and a comparator to compare the first self-diagnosis pattern data with the second self-diagnosis pattern data to judge the presence or absence of a difference.

Abstract: Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure.

Abstract: A test framework architecture that separates the generation of random test actions from test execution and provides a way to record the state of the system under test at user controlled intervals. This saved state is used to bring the test system to the last known state before failure and then execute the much smaller set of actions to the point of failure, thus requiring shorter run time. Given the same time constraints, this enables the execution of this smaller set more frequently, providing better bug fix verification and shorter reproduction time.

Abstract: A system for generating test signals to test characteristics of input-output (IO) cells includes a memory and a processor coupled together through an integrated circuit (IC) chip. The IC chip includes a controller configured to exchange signals between the memory and the processor through IO cells of the IC chip. The IC chip further includes a protocol sequence generator for generating test signals for testing characteristics of the IO cells.

Abstract: The present invention provides a method, test-bed and computer program product for testing an application installed on a wireless communication device. The wireless communication device communicates one or more messages wirelessly to a server through a test-bed. The test-bed is connected with the server and provides one or more testing parameters for the one or more messages. A tester, testing the application, assigns a probability to the one or more messages. Further, the tester assigns a probability to the one or more testing parameters. Thereafter, the messages are re-communicated between the server and wireless communication device through the test-bed. Subsequently, the one or more messages are identified by the test-bed and one or more wireless network conditions are emulated based on the probabilities assigned to the one or more messages and the one or more testing parameters.

Abstract: A non-transitory, computer-readable recording medium stores therein a verification program that causes a computer to execute detecting from a structure expressing a group of scenarios for verifying an operation of a design under verification and by hierarchizing sequences for realizing the operation as nodes, a similar node similar to a faulty node representing a sequence in which a fault has occurred; generating a string of sequences represented by a group of nodes on a path starting from a start node of the structure to the detected similar node; and outputting the generated string of sequences.

Abstract: A rotational vibration test system and method of a storage system set storage devices of the storage system, fan speeds of an electric fan of the storage system, and access patterns of the storage system. The electric fan is controlled to run at the fan speeds. The storage system is accessed according to the access patterns. Accordingly, the storage devices are input/output performance tested. Test results of the storage devices are output to an output device.

Abstract: A computer storage medium having a computer-readable code segment for performing a method may be provided. The method may include receiving inputs from a user using an interface, the inputs define a test that is run against the application software; associating a resource with the test, the resource selected by the user using the interface; executing the test against the application software; comparing an outputted value of the application software with an expected value; and outputting a result.

Abstract: Embodiments are described for using synchronized event types in testing an application configured to be executed on multiple types of networked devices. The method can include playing a macro containing recorded application events to be applied to the application for testing. The recorded application events can be stored in a macro queue during playback. Further, order independent events can be identified in the macro queue, which precede an order dependent event. This enables identified order independent events to be removed. In addition, an order dependent event in the macro queue can be removed after order independent events preceding the order dependent events are removed. Then the order dependent event from the macro queue can be played after the order dependent event has been removed from the macro queue.

Abstract: Network device testing equipment capable of testing network devices using small size packets and for a transferring ability and a filtering ability at a media speed is described. A configuration is adopted in which a Field Programmable Gate Array (FPGA) included in a transmitter or receiver on one or both of transmitting and receiving sides is connected directly to a physical layer chip of a network and computers on both the transmitting and receiving sides are connected thereto. Each of the FPGAs of the transmitter and receiver has a circuit which has an integrated function of transmitting a packet pattern generation function and a packet-receiving function, thereby enabling a test and an inspection in real time. When inspecting the filtering function, a hash table storing therein a hash value and a list of occurrence frequencies for hash values is utilized.

Abstract: A test system collects passing event data and failing event data, and merges the collected data into passing subsequences and failing subsequences, respectively. The test system identifies an overlap area between the passing subsequence and the failing subsequence in regards to time slices and tracepoint slices, and creates passing transactions and failing transactions using the event data corresponding to the overlap area. Next, the test system detects a timing discrepancy between the first passing transaction relative to the second passing transaction compared with the first failing transaction relative to the second failing transaction. The test system then reports the detected timing discrepancy, which allows a test engineer to perturb the test program in order to more frequently catch intermittent failures caused by asynchronous timing conditions.

Abstract: A first test script that includes at least one first step for executing a test of a test portal is provided in a computing device. An indication that an event has occurred in response to the test is received in the computing device. A second test script that includes at least one second step for executing the test is generated in the computing device, the at least one second step being at least in part a response to the event.

Abstract: In one embodiment, a method includes accessing first data describing online activities of a user and accessing second data describing online activities of each of one or more content publishers. The method includes, based at least in part on the first data and the second data, determining one or more similarities between the user and each of the content publishers. The method includes, based at least in part on one or more of the similarities, selecting each of one or more of the content publishers as a key influencer for the user and selecting particular content published by a particular one of the key influencers for summary and delivery to the user. The method includes generating a summary of the particular content and automatically delivering to the user the particular content and the summary.

Abstract: Systems and methods for item-level restoration from and verification of an image level backup without fully extracting it. The method receives backup parameters and selection of an image level backup to restore or verify and initializes virtual storage. The method attaches the virtual storage to a hypervisor to launch a virtual machine (VM) to test and restore data objects. The method stores VM virtual disk data changes resulting from restoration and verification in a changes storage. The method optionally reconfigures VMs to use an isolated network. The method optionally uses a routing appliance to provide access to VMs running in the isolated network from a production network. The method determines if the VM operating system (OS) is able to start using restored copies of selected data objects and tests applications associated with selected data objects. The method displays restoration and test results in an interface and automatically delivers the results.

Abstract: A test method for a master-slave concurrent system running on a multicore processor includes the steps of establishing a PFA, otherwise called probabilistic finite automata, or probabilistic finite state machine, for a given regular expression; generating test patterns by running the PFA; splitting and merging the test patterns to generate an interleaved test pattern; and performing test on the master-slave system according to the interleaved test pattern. In an embodiment, the method further includes a step of debugging failures of the multicore processor during testing.

Abstract: A testing method for testing a touch control device is disclosed. In a controller of the touch control device, a processor executes an operating firmware to realize a touch control function. The testing method includes a host testing device outputting a test requirement command to the controller, the controller outputting data corresponding to an operating stage selected from a plurality of operating stages of executing the operating firmware to the host testing device according to the test requirement command, and the host testing device determining an operating status of the touch device according to data provided by the touch control device.

Abstract: A method executes computerized instructions stored within a computer storage medium within an integrated and packaged semiconductor device using a centralized programming interface within the packaged semiconductor device to perform in-system preventive and recovery actions, configure and issue stimulus to chips, components and sensors within the semiconductor device. The method monitors chip, components and sensors within the packaged semiconductor device, using the centralized programming interface, to measure characteristics of the packaged semiconductor device in response to the stimulus. The structure including chips, components and sensors produce outputs representing the characteristics.

Abstract: System and method for analyzing operation of a device under test (DUT). In one embodiment, a reference component associated with a reference device may be received. The reference device may be in communication with the DUT and a component associated with the DUT can be exchanged with the reference component. A test may be performed on the DUT, wherein a result of the test may correspond to a source of a fault associated with the DUT. An indication of the source of the fault may be provided based on the test result.

Abstract: The present invention features an operational system test method, comprising defining a fault model, inserting a test agent, hooking a test location, collecting test information, and removing the test agent. The invention also features an operational system test method, comprising defining a fault model, inserting a test agent, identifying a memory area according to a test location, hooking the identified memory area, collecting test information, and removing the test agent.

Abstract: A basic input output system (BIOS) test system includes a protocol conversion module and a computer. The protocol conversion module is connected to a tested device. The computer is connected to the protocol conversion module. The computer controls the protocol conversion module to simulate a keyboard to send keyboard commands to the device. The computer storing correct setting lists and comments of the setting lists of the BIOS. The tested device selects setting lists and comments thereof according to the keyboard selection commands sent by the protocol conversion module. The tested device is connected to the computer to deliver selected setting lists and comments thereof to the computer. The computer compares the selected setting lists and comments thereof with the correct setting lists.