Abstract: One embodiment described herein provides a method and system for handling errors in a storage system. During operation a data-placement module of the storage system detects an error occurring at a first physical location within the storage system. In response to determining that the error occurs during a write access, the system writes to-be-written data into a second physical location within the storage system, and updates a mapping between a logical address and a physical address associated with the to-be-written data.

Abstract: A given packet of the packetized data flow of packets is received. The given packet (145) is selectively discarded depending on at least one of the flow history of the packetized data flow and up pseudorandom test. In some embodiments, the selectively discarding is selectively executed of the given packet is at least partially overlapping with at least one further packet of the packetized data flow. Such techniques may find particular application in network-based intrusion prevention systems.

Abstract: A decoder circuit includes an input to receive a first codeword encoded based on a quasi-cyclic low-density parity-check (QC LDPC) code and a plurality of memory banks to store the received codeword. Each column of the received codeword is assigned to one of the plurality of memory banks based at least in part on an order of the plurality of columns in the received codeword. A first reordering stage is to change the memory bank assignment for one or more of the plurality of columns by reordering the columns in the received codeword. An LDPC decoder is to decode the reordered codeword stored in the plurality of memory banks based at least in part on the QC LDPC code. A second reordering stage is to output the decoded codeword from the plurality of memory banks based at least in part on an order of the columns in the first codeword.

Abstract: The embodiments set forth a technique that enables the storage of data at a first data storage device. The technique includes, at the first data storage device, dividing the data to produce a first and second portion of the data, in which the first and second portions are associated with a computed exclusive or (“XOR”) value. Also, the technique includes deleting the second portion stored at the first data storage device, based at least in part on whether the computed XOR value is established. Also, the technique includes receiving a first replicated metadata, in which the first replicated metadata indicates a location of the second portion stored at the second data storage device. Furthermore, the technique includes communicating either the first portion or the second portion, to a remote computing device, based at least in part on the first replicated metadata.

Abstract: A system and method for an LBA RAID storage device. The LBA RAID storage device includes a plurality of data channels and a plurality of storage components. Each of the storage components is connected to one of the plurality of data channels. A storage controller is configured to receive a data and write the data to a RAID group made up of at least two storage components of the plurality of storage components that are each connected to a separate data channel.

Abstract: An apparatus comprises at least one processing device comprising a processor coupled to a memory. The processing device is configured to select a stripe column size for stripes of a data storage system, to determine a first compress block size for a first one of the stripes based on compressibility of data to be stored, to select a first prime number for computing parity blocks for the first stripe and a first number of sub-stripes for splitting stripe columns of the first stripe, to generate metadata specifying the first compress block size, the first prime number and the first number of sub-stripes for the first stripe, and to store data compressed using the first compress block size in the first stripe. The first prime number and first number of sub-stripes for the first stripe is different than a second prime number and second number of sub-stripes for a second stripe.

Abstract: Embodiments of the present disclosure provide a method for a storage system, a storage system and a computer program product. The method comprises determining a first drive in a drive array is temporarily unavailable. The method further comprises setting the first drive in a frozen state. The method further comprises: in response to receiving a write request for the first drive during the frozen state, pending the write request or recording the write request in a second drive in the drive array. The method further comprises: in response to receiving a read request for the first drive during the frozen state, reconstructing data to which the read request is directed through data stored in a third drive in the drive array.

Abstract: The embodiment of the present invention discloses a memory device and a method for operating the same. The memory device includes a memory array and a logic circuit. The logic circuit is coupled to the memory array, and is configured to perform a corresponding operation in response to an operation command from a controller. When an interruption event occurs during the corresponding operation, the logic circuit records a memory status, and the logic circuit further is configured to output the memory status to the controller in response to a status read command from the controller.

Abstract: Systems and methods are disclosed for open block stability scanning. When a solid state memory block remains in an open state, where the block is only partially filled with written data, for a prolonged period of time, a circuit may perform a scan on the block to determine the stability of the stored data. When the scan indicates that the data is below a stability threshold, the data may be refreshed by reading the data and writing it to a new location. When the scan indicates that the data is above a stability threshold, the circuit may extend the time period in which the block may remain in the open state.

Abstract: A method and wireless transmit/receive unit (WTRU) for uplink transmission are disclosed. A WTRU receives configuration information. The configuration information includes logical channel priority information and a maximum number of hybrid automatic repeat request (HARQ) transmissions. For a transmission time interval (TTI), the WTRU identifies a HARQ process to use for uplink transmission for the TTI on a condition that an uplink grant is for the TTI. The WTRU selects data for uplink transmission for the TTI. For a new uplink transmission, data is allocated in decreasing order of priority based on the logical channel priority information. The WTRU initializes a transmission counter. The transmission counter indicates a number of transmissions associated with the selected data. The WTRU transmits the selected data over an uplink channel based on the uplink grant using the identified HARQ process.

Abstract: In one example, a system for managing encrypted memory comprises a processor to store a first MAC based on data stored in system memory in response to a write operation to the system memory. The processor can also detect a read operation corresponding to the data stored in the system memory, calculate a second MAC based on the data retrieved from the system memory, determine that the second MAC does not match the first MAC, and recalculate the second MAC with a correction operation, wherein the correction operation comprises an XOR operation based on the data retrieved from the system memory and a replacement value for a device of the system memory. Furthermore, the processor can decrypt the data stored in the system memory in response to detecting the recalculated second MAC matches the first MAC and transmit the decrypted data to cache thereby correcting memory errors.

Abstract: Methods and systems for enabling recovery of lost packets transmitted over a communication network. In one embodiment, a device includes a processor and a transmitter. The processor is configured to calculate a row parity packet (RPP) and a diagonal parity packet (DPP) for n packets. Each of the RPP, the DPP, and the n packets comprises n segments. The processor utilizes each packet, from among the n packets, to update parity values in the RPP and the DPP in such a way that each segment in the packet is used to update one segment in the RPP and at most one segment in DPP. The transmitter transmits the n packets, the RPP, and the DPP over the communication network. Receiving a subset of n members of a set comprising: the RPP, the DPP, and the n packets, enables recovery of two lost packets.

Abstract: Methods and systems that enable recovery lost packets that were transmitted over a communication network. In one embodiment, a device includes a receiver and a processor. The receiver receives n packets that belong to a set comprising n+2 packets transmitted over the communication network, where the set includes: n data packets, a row parity packet (RPP), and a diagonal parity packet (DPP). Each received packet comprises n segments. Each segment of the RPP comprises a result of a parity function applied to a set comprising n segments, each belonging to a different packet from among the n data packets. Each segment of the DPP comprises a result of a parity function applied to a set comprising n segments, each belonging to a different packet selected from a group comprising the n data packets and the RPP. The processor may utilize the received packets to recover two lost packets.

Abstract: A rebuild node of a storage system can assess risk of the storage system not being able to provide a data object. The rebuild node(s) uses information about data object fragments to determine health of a data object, which relates to the risk assessment. The rebuild node obtains object fragment information from nodes throughout the storage system. With the object fragment information, the rebuild node(s) can assess object risk based, at least in part, on the object fragments indicated as existing by the nodes. To assess object risk, the rebuild node(s) treats absent object fragments (i.e., those for which an indication was not received) as lost. When too many object fragments are lost, an object cannot be rebuilt. The erasure coding technique dictates the threshold number of fragments for rebuilding an object. The risk assessment per object influences rebuild of the objects.

Abstract: A device includes a memory device and a controller. The controller is configured to receive data to be stored in the non-volatile memory and to store a first copy of the data and a second copy of the data to a volatile memory. The controller is configured, in response to detecting a bit error corresponding to the first copy of the data prior to storage of the first copy of the data to the non-volatile memory, to perform an error detection operation that includes comparing first redundancy data corresponding to the first copy of the data to second redundancy data corresponding to the second copy of the data.

Abstract: A method for execution by a dispersed storage and task (DST) execution unit that includes a processor includes receiving a slice pre-image request from a computing device via a network that indicates a data slice, a requesting entity and a plurality of storage units. A data pre-image is generated by performing a pre-image function on the data slice based on the plurality of storage units. An encrypted data pre-image is generated for transmission to the computing device by performing an encryption function on the data pre-image based on a key associated with the requesting entity.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable based on the operational instructions, is configured to perform various operations. The computing device determines data access rates corresponding respectively to storage units (SUs). In certain situations, the computing device selects at least a data access threshold number of SUs excluding a first slowest SU having the first slowest data access rate to service data access request(s) for set(s) of encoded data slices (EDSs) corresponding to a data object. The computing device facilitates servicing of the data access request(s) for the set(s) of EDSs by the at least a data access threshold number of SUs that excludes the first slowest SU having the first slowest data access rate.

Abstract: A semiconductor device includes a bitwise operation unit and a storage control unit. The bitwise operation unit performs a bitwise operation on first n-bit (n is an integer) data that is storage object data and second data of an n-bit bit pattern and generates third data of a bit pattern that the number of “1s” and the number of “0s” are almost the same as each other. The storage control unit stores the third data into a first storage destination of a storage unit and stores fourth data that is the third data or data that is converted into the third data by performing a bitwise operation that has been predetermined in advance on the data into a second storage destination of the storage unit.

Abstract: In general, embodiments of the technology relate to improving read performance of solid-state storage by using decoding schemes deemed particularly suitable for the read operation that is currently being performed. More specifically, embodiments of the technology relate to using program/erase (P/E) cycle values, retention times, and page numbers in order to determine the appropriate decoding parameters to use when reading data that has been previously stored in the solid-state storage.

Abstract: One embodiment provides a system that facilitates numerical operation-based erasure coding. During operation, the system determines the bit-width of processing capability of the computing system. The system then determines, based on the bit-width, a number of bits for representing a respective data element from a data stream and a number of data elements based on a number of a dimension of a generator matrix of erasure encoding. The system then obtains the number of data elements from the data stream and converts a respective obtained data element to a corresponding numerical representation. Here, a respective obtained data element is represented by the determined number of bits. The system then generates a code word, which comprises a plurality of coded fragments, of erasure encoding from the numerical representations based on the generator matrix of the erasure encoding.

Abstract: A smart storage device is provided. The smart storage device contains a data analysis engine and an error detection engine. An external controller sends a command indicating that data contained on a storage medium in the smart storage device which meets certain criterion should be scrubbed, and the smart storage device locates that data without the external controller passing the actual location of the data on the storage medium.

Abstract: Some embodiments include apparatuses and methods using a first memory area and a second memory area included a memory device, and using control circuitry included in the memory device to communicate with a memory controller. The memory controller includes an error correction engine. The control circuitry of the memory device is configured to retrieve the first information from the first memory area and store in the first information after the error correction engine performs an error detection operation on the first information. The control circuitry is configured to retrieve second information from the first memory area and store the second information in the second memory area without an additional error detection operation performed on the second information if a result from the error detection operation performed by the error correction engine on the first information meets a threshold condition.

Abstract: A method for execution by a dispersed storage and task (DST) execution unit that includes a processor includes receiving a slice pre-image request from a computing device via a network that indicates a data slice, a requesting entity and a plurality of storage units. A data pre-image is generated by performing a pre-image function on the data slice based on the plurality of storage units. An encrypted data pre-image is generated for transmission to the computing device by performing an encryption function on the data pre-image based on a key associated with the requesting entity.

Abstract: The techniques and/or systems described herein implement erasure coding to generate various chunks for a data collection (e.g., data chunks and at least one encoding chunk). The chunks are then distributed and stored within an individual group (e.g., a pod) of storage units, where a pod of storage units is determined based on characteristics that affect an amount of time it takes to recover a data collection or to restore lost data.

Abstract: A coding scheme for coding “code constructs” (for example, alphanumeric characters) into “bit sequences,” where at least one of the code constructs is assigned at least two different bit sequences (that is, a first bit sequence and a second bit sequence). This is sometimes referred to herein as “alternative codings for a single code construct.” In some embodiments, at least one of the alternative codings includes bits that can be used for error detection and/or correction. In some embodiments, the code scheme will be similar to a pre-existing code scheme that does not have alternative codings for a single code construct so that the alternative-codings coding scheme is back compatible with data encoded under the pre-existing coding scheme.

Abstract: A method begins by a dispersed storage (DS) processing module of a dispersed storage network (DSN), when in a rebuilding mode, determining a level of rebuilding urgency, where the level of rebuilding urgency is based on an inversely proportional function of a level of error encoded redundancy for error encoded data giving rise to the rebuilding mode. When the level of rebuilding urgency is at or above a critical level, the method continues with the DS processing module placing a set of storage units of the DSN in a critical rebuilding mode, where, when in the critical rebuilding mode, the set of storage units prioritize rebuilding of the error encoded data giving rise to the rebuilding mode over other error encoded data operations.

Abstract: A storage apparatus includes a processor. The processor is configured to sequence a plurality of data pieces. The plurality of data pieces are respectively stored in a plurality of memory devices. The processor is configured to set compensation ranges to be respectively compensated by a first predetermined number of parities. The compensation ranges are respective portions of consecutive data pieces among the sequenced data pieces. The compensation ranges include a variably set number of data pieces for the respective parities. Each of the plurality of data pieces is included in a second predetermined number of compensation ranges.

Abstract: A card computing device may include and manage multiple virtualized universal integrated circuit cards (UICCs) for use with mobile communications. The card computing device may be capable of storing information, and executing applications, for multiple mobile networks (e.g., using multiple virtual UICCs) and of managing switches among those mobile networks. A mobile network operator (MNO) may be represented by a MNO profile, which, when enabled, may look and behave like a dedicated UICC. One or more applications may be deployed on the card computing device and each may be associated with a MNO profile. When a MNO profile is enabled, one or more applications may be activated and when a MNO profile is disabled, one or more active applications may be deactivated, according to some embodiments. Thus, a card computing device may be configured to activate and deactivate applications as part of managing MNO profiles.

Abstract: A semiconductor system may include a plurality of memory devices corresponding to a plurality of channels, an address mapping unit suitable for converting addresses corresponding to provided external requests according to a selected address map among a plurality of address maps; a monitoring unit suitable for monitoring the external requests provided to each of the plurality of channels, and a control unit suitable for providing a control signal for controlling the address mapping unit to select an address map according to a result of the monitoring.

Abstract: Techniques for generating parities and repairing data erasures using repair-optimal parities are disclosed. The system includes an encoding module, which receives a request to recreate data for a subset of a plurality of content stores. The encoding module generates a new first parity and a new second parity using a subset of remaining content from the plurality of content stores. The encoding module generates a first portion of the requested data using the new first parity and a first subset of an original first parity for the plurality of content stores and a second portion of the requested data using the new second parity and a second subset of an original second parity for the plurality of content stores. The encoding module may recreate the data for the content store using the first portion of the requested data and the second portion of requested data.

Abstract: A processing system comprises one or more processor devices and other system components coupled to a stacked memory device having a set of stacked memory layers and a set of one or more logic layers. The set of logic layers implements a metadata manager that offloads metadata management from the other system components. The set of logic layers also includes a memory interface coupled to memory cell circuitry implemented in the set of stacked memory layers and coupleable to the devices external to the stacked memory device. The memory interface operates to perform memory accesses for the external devices and for the metadata manager. By virtue of the metadata manager's tight integration with the stacked memory layers, the metadata manager may perform certain memory-intensive metadata management operations more efficiently than could be performed by the external devices.

Abstract: Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values.

Abstract: An ATE system performs RA over NAND flash memory DUTs. A first UBM captures fresh failure related data from a DUT. A second UBM transmits existing failure related data. A fail engine accesses the stored existing failure related data and generates a failure list based thereon. The storing and the accessing the existing failure related data, and/or the generating the failure list, are performed in parallel contemporaneously in relation to the capturing the fresh data. The generated failure list is queued. A failure processor, which may be operable for controlling the capturing, computes a redundancy analysis based on the queued failure list. The first and second UBMs then ping-pong operably.

Abstract: A method of an aspect includes running a plurality of threads on a plurality of thread processors. Memory accesses, of a thread of the plurality that is running on a first thread processor of the plurality, are monitored to both a first memory through a first memory controller and a second memory through a second memory controller. A second thread processor of the plurality is selected for a thread based on the monitoring of the memory accesses of the thread to both the first memory and the second memory. Installation of the thread, for which the second thread processor was selected, is initiated on the second thread processor. Other methods, apparatus, and systems are also disclosed.

Abstract: A computer implemented method, system, and computer program product for non-disruptively moving a replicated volume from a first storage medium to a second storage medium, the method comprising notifying a first data protection appliance that the replicated volume is moving from a first storage medium to a second storage medium; setting a replication connection between second volume and target of the first volume while maintaining replication connection from first volume to target of the first volume.

Abstract: A method includes detecting that a first device in a memory array has degraded, the first device storing a portion of a data record, wherein the data record is encoded using a first error control technique. The method continues with recovering the data record using portions of the data record stored in devices other than the first device in the memory array and encoding the data record using a second error control technique. The method also includes storing the data record in the devices of the memory array other than the first device.

Abstract: A method begins by a processing module storing a set of encoded data slices in storage units. A data segment of data is encoded, in accordance with dispersed storage error encoding parameters, to produce the set of encoded data slices. The dispersed storage error encoding parameters include a decode threshold number and a pillar width number, which is at least twice the decode threshold number. The method continues with the processing module processing a first request for retrieval of the data segment by retrieving a first sub-set of encoded data slices, which includes the decode threshold number, and decoding them to produce a first recovered data segment. The method continues with the processing module processing a second request for retrieval of the data segment by retrieving a second sub-set of encoded data slices, which includes the decode threshold number, and decoding them to produce a second recovered data segment.

Abstract: An apparatus and method are provided for opportunistically performing scrubbing operations on a memory device. The apparatus is used for accessing the memory device in response to access requests issued by at least one requesting device and comprises interface circuitry that is configured to access the memory device in response to the access requests. The apparatus also comprises activity monitoring circuitry which generates memory access activity data that results from memory access activity between the interface circuitry and the memory device. Scrubbing circuitry is also included and is configured to issue scrubbing access requests to perform the scrubbing operations, the scrubbing access requests being issued in response to the memory access activity data indicating a trigger condition.

Abstract: Storage system comprises a second storage apparatus, which is coupled to multiple first storage apparatuses and is of a different type from the first storage apparatuses, and a first control device, which exists either inside or outside of the second storage apparatus. Row of stripes comprising multiple data elements obtained by segmenting a prescribed data unit, and a redundancy code for rebuilding the data elements, is distributively stored in multiple first storage apparatuses, which are more numerous than the total number of stripe data elements, which are either the data elements or redundancy code, in the row of stripes. The row of stripes is configured to enable the rebuilding of the stripe data elements even when a failure has occurred in up to a prescribed allowable number, which is two or more, of the first storage apparatuses storing the stripe data elements of the relevant row of stripes.

Abstract: Systems and methods are disclosed for recovering from a data access error encountered in data stripes implemented in a data redundancy scheme (e.g., RAID) in a solid state storage device. In one embodiment, the storage device holds parity data in a temporary, volatile memory such as a RAM and writes the parity data to the non-volatile memory when a full stripe's worth of new write data has been written to the non-volatile memory. In one embodiment, upon detecting that a data access error has occurred in a partially written stripe, the storage device initiates a write of the parity data for the partially written stripe to the non-volatile memory and executes a RAID recovery procedure using the newly written parity data to attempt to recover from the detected error. This approach allows for a recovery from the data access error without waiting for the full stripe to be written.

Abstract: A method for converting a disk of a physical computer into a virtual disk for use by a virtual machine is described. Contents of the disk of the physical computer are copied into an image file, wherein the image file has a different sector-by-sector organization of the contents than the disk but a logically equivalent file system organization. Hardware configuration information from the image file is then extracted, wherein the hardware configuration information relates to hardware of the physical computer and, based on a comparison of the extracted hardware configuration information and a virtual hardware configuration of the virtual machine, hardware dependent files in the image file are replaced with substitute files that are compatible with the virtual hardware configuration of the virtual machine.

Abstract: A method begins with a processing module of a centralized digital video storage (DVS) system storing, for playback, a plurality of sets of encoded data slices in storage units, where multi-media content is encoded to produce the plurality of sets of encoded data slices. The method continues with the processing module monitoring the storage units for a failure mode and monitoring a number of subscriber devices requesting playback of the multi-media content. The method continues with the processing module determining whether a sufficient number of unique combinations of a decode threshold number of encoded data slices per set of slices exists to service playback of the multi-media content. When the sufficient number of the unique combinations do not exist, the method continues with the processing module reassigning unique combinations of the decode threshold number of encoded data slices per set of encoded data slices to some of the subscriber devices.

Abstract: A data retention methodology for use in electrically rewritable nonvolatile storage systems is disclosed. The methodology collects characterization data of the storage system (e.g., time stamps, program/erase cycles, sensed temperature over time, and others) and uses at least a portion of that data to associate various data retention schemes with the collected characterization data. At power-on, the methodology determines a duration of a time during which power was not supplied to the storage system. The methodology also uses the power-on time to trigger the selection of an appropriate data protection scheme (e.g., enhanced ECC and/or read/scrub frequency). Dynamic selection and adjustment of the applied protection scheme may be based on the predetermined and/or calculated association between various protection schemes and the collected characterization data of the storage system.

Abstract: A memory device is provided with an instruction decoding unit, a control and logic unit, a first memory, and a second memory. The memory device serves to decode an inputted instruction and producing a decoding signal. The control and logic unit serves to produce a control signal based on the decoding signal. The first memory has a first memory array and a first page buffer, and the second memory with a second memory array and a second page buffer. When the inputted instruction is a preset instruction, the preset instruction is used to simultaneously execute data access on a first memory and access the backup data on a second memory based on a same data.

Abstract: A circuit may be configured to increase the data retention reliability of non-volatile solid state memory (NVSSM) by writing a parity block, which can contain user data pages and parity data pages. A circuit can also be configured to store the parity data pages based on whether the user data pages in the block have been filled, on elapsed time, or during a power down event.

Abstract: A method for calculating parity values including calculating a first set of parity values using datum stored in RAID Grid locations in a first PCB, where datum associated with the RAID Grid locations in the first PCB is obtained in a first order that is based on a Hilbert curve. The method further includes calculating a second set of parity values using datum stored in RAID Grid locations in a second PCB, where datum associated with the RAID Grid locations in the second PCB is obtained in a second order that is based on the Hilbert curve. The method further includes storing at least a portion of the first set of parity values and a second set of parity values in a cache, memory, or persistent storage, where each of the first parity values and second parity values is associated with a separate RAID Grid location in the RAID Grid.

Abstract: A method for surveying a data storage subsystem for latent errors before a failing disk drive of the data storage subsystem fails and recovering unreadable data usable to reconstruct data of the failing disk drive. The method includes determining that a disk drive of a plurality of disk drives of the data storage subsystem meets a threshold for being identified as a failing disk drive, and prior to failure of the failing disk drive, surveying at least a portion of the data on the remaining plurality of disk drives to identify data storage areas with latent errors. The identified data storage areas may be reconstructed utilizing, at least in part, data stored on the failing disk drive.

Abstract: Embodiments are directed towards efficient erasure coding for storage systems. A smallest integer in a set may be determined based on a number of storage devices in the storage system such that the determined integer is greater or equal to the number of storage devices. The smallest integer in the set may be determined from the set {2N?1} where N is an integer based on the number of storage devices. A matrix may be generated based on a number of columns equal to the determined integer and a number of rows equal to the number of columns plus a number of global repair symbol devices and plus a number of virtual repair symbol devices. Each virtual repair symbol device enables an additional of level of protection against failures in the storage system.

Abstract: A method for data storage includes storing two or more data items in a non-volatile memory. Redundancy information is calculated over the data items, and the redundancy information is stored in a volatile memory. Upon a failure to retrieve a data item from the non-volatile memory, the data item is reconstructed from remaining data items stored in the non-volatile memory and from the redundancy information stored in the volatile memory.

Abstract: There is disclosed a memory system and method. The memory system may include a plurality of memory planes including two or more data memory areas, and a memory controller adapted to controlling reading, writing, and erasing of the plurality of memory planes. When any one of the data memory areas is occupied with one of a write operation and an erase operation, the controller may reconstruct data stored in the one occupied data memory area by reading parity information and data stored in the plurality of memory areas other than the one occupied data memory area.