Ecc, Parity, Or Fault Code (i.e., Level 2+ Raid) Patents (Class 714/6.24)
  • Patent number: 8898513
    Abstract: A method begins by a processing module identifying a plurality of dispersed storage networks (DSNs) for storing copies of dispersed storage encoded data based on global data retrieval accesses of the copies of the dispersed storage encoded data. The method continues with the processing module determining a set of error coding dispersal storage parameters for at least one of the plurality of DSNs based on local data retrieval accesses allocated to the at least one of the plurality of DSNs. The method continues with the processing module encoding data in accordance with the set of error coding dispersal storage parameters to produce a copy of the copies of the dispersed storage encoded data and outputting the copy of the copies of the dispersed storage encoded data to the at least one of the plurality of DSNs.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: November 25, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 8898380
    Abstract: Disclosed is a RAID data checking system. I/O controllers to read data RAID data from the storage devices and transfer that data to virtual memory address ranges. The P+Q checking function receives the data sent to the virtual memory address ranges. However, instead of storing the incoming data, the P+Q checking function updates intermediate values of the P and Q redundant data calculations associated with the incoming data. When all of the strips have been received, the P+Q checking function will have completed the calculation of P and Q redundant data. In this case, after all the strips and the P or Q data have been received, the P+Q checking function will hold zeroes if all the data and the P and Q data was correct and hold non-zero values if there was an error.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: November 25, 2014
    Assignee: LSI Corporation
    Inventor: William Patrick Delaney
  • Publication number: 20140344616
    Abstract: A storage subsystem receives writes via a storage subsystem interface and reduces a number of the writes. Data associated with the reduced number of writes is stored in storage devices of a single drive. Computed redundancy information is stored in the storage devices. A data redundancy scheme is implemented via a disk controller that is enabled to operate without a loss of data in the presence of at least a single failure of any of the storage devices.
    Type: Application
    Filed: May 11, 2014
    Publication date: November 20, 2014
    Applicant: LSI CORPORATION
    Inventor: Radoslav Danilak
  • Patent number: 8892940
    Abstract: A method includes, in at least one aspect, receiving a command for a group of data units to be transmitted to a host in a first sequence; for each data unit of the group of data units, receiving an identifier of the data unit and a signal indicating that the data unit has been retrieved and processed for errors, wherein the identifiers and the signals are received in accordance with the group of data units being retrieved from one or more memory devices in a second sequence that is different from the first sequence; tracking the group of data units retrieved in the second sequence; determining, by processing circuitry, that the group of data units has been retrieved and processed for errors; and initiating transmission of the group of data units to the host in accordance with the first sequence.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: November 18, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Cheng Kuo Huang, Siu-Hung Frederick Au, Lau Nguyen, Perry Neos
  • Publication number: 20140331085
    Abstract: A distributed storage integrity system in a dispersed storage network includes a scanning agent and a control unit. The scanning agent identifies an encoded data slice that requires rebuilding, wherein the encoded data slice is one of a plurality of encoded data slices generated from a data segment using an error encoding dispersal function. The control unit retrieves at least a number T of encoded data slices needed to reconstruct the data segment based on the error encoding dispersal function. The control unit is operable to reconstruct the data segment from at least the number T of the encoded data slices and generate a rebuilt encoded data slice from the reconstructed data segment. The scanning agent is located in a storage unit and the control unit is located in the storage unit or in a storage integrity processing unit, a dispersed storage processing unit or a dispersed storage managing unit.
    Type: Application
    Filed: July 15, 2014
    Publication date: November 6, 2014
    Applicant: CLEVERSAFE, INC.
    Inventors: Greg Dhuse, Andrew Baptist, Zachary J. Mark, Jason K. Resch, Ilya Volvovski
  • Patent number: 8880981
    Abstract: A data access request is received specifying a data block stored in a stripe of a parity group that includes a plurality of data storage devices to store data blocks and a parity storage device to store parity information for the data. The stripe includes a data block from each of the plurality of data storage devices and the stripe includes a parity block from the parity storage device. An error is detected in the data block specified by the data access request. The error is identified as a lost write error for the data block or a lost write error for the parity block. Identifying the error includes comparing a first storage device signature stored in a metadata field associated with the data block to a second storage device signature stored in a label block identifying a data storage device where the data block is stored.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: November 4, 2014
    Assignee: NetApp, Inc.
    Inventors: Tomislav Grcanac, Atul Goel, Jagadish Vasudeva, Gururaj Mj
  • Publication number: 20140325265
    Abstract: Technology is disclosed for performing background initialization on protection information enabled storage volumes or drives. In some embodiments, a storage controller generates multiple I/O requests for stripe segments of each drive (e.g., disk) of multiple drives of a RAID-based system (e.g., RAID-based disk array). The I/O requests are then sorted for each of the drives according to a pre-determined arrangement and initiated in parallel to the disks while enforcing the pre-determined arrangement. Sorting and issuing the I/O requests in the manner described herein can, for example, reduce drive head movement resulting in faster storage subsystem initialization.
    Type: Application
    Filed: July 31, 2013
    Publication date: October 30, 2014
    Applicant: NetApp, Inc.
    Inventors: Wei Sun, Donald Humlicek, Theresa Segura
  • Patent number: 8874825
    Abstract: A data storage device and methods of performing memory operations using location-based parameters are disclosed. A method includes identifying a set of parameter values associated with a physical block of a memory array on a memory die. The set of parameter values is identified based on a physical location of the physical block. A physical location may include an edge or a central region of the memory array or the memory die. The memory die may comprise a nonvolatile semiconductor memory (e.g., flash memory). Parameter values may include a size or a number of programming steps, pulse widths, maximum programming or erase voltages, reading or verify reference voltages, and parameters relating to error correction, among others, including time dependent parameters. A memory access operation, such as a reading, programming, or erasing operation, is initiated with respect to the physical block in accordance with the set of parameter values.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: October 28, 2014
    Assignee: Sandisk Technologies Inc.
    Inventors: Idan Alrod, Eran Sharon
  • Publication number: 20140317447
    Abstract: A system and method for adaptive RAID geometries. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to determine a first RAID layout for use in storing data, and write a first RAID stripe to the device group according to the first RAID layout. In response to detecting a first condition, the controller is configured to determine a second RAID layout which is different from the first RAID layout, and write a second RAID stripe to the device group according to the second layout, whereby the device group concurrently stores data according to both the first RAID layout and the second RAID layout.
    Type: Application
    Filed: May 21, 2014
    Publication date: October 23, 2014
    Applicant: PURE Storage, Inc.
    Inventors: John Colgrove, John Hayes, Bo Hong, Ethan Miller
  • Patent number: 8862931
    Abstract: A data processing module includes a first interface connected to (i) a host via a second interface, and (ii) storage arrays. The first interface receives, from the host via the second interface, blocks of data for storage in one or more of the storage arrays. A memory stores the blocks of data received by the first interface. A processor (i) determines error checking and correcting processing to be applied to each block of data of the blocks of data, and (ii) for each block of data, (a) transfers the block of data from the memory to a selected storage array of the storage arrays, and (b) assigns, to the selected storage array, the error checking and correcting processing to be applied to the block of data. The memory stores a map. The map indicates storage of the blocks of data among the storage arrays.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: October 14, 2014
    Assignee: Marvell World Trade Ltd.
    Inventor: Pantas Sutardja
  • Patent number: 8862847
    Abstract: A distributed data storage method, apparatus, and system for reducing a data loss that may result from a single-point failure. The method includes: splitting a data file to generate K data slices, splitting each data slice of the K data slices to generate M data blocks for each data slice, and performing check coding on the M data blocks by using a redundancy algorithm to generate N check blocks; determining, by using a random algorithm, a first physical storage node corresponding to one block of the M data blocks and the N check blocks, and determining at least M+1 different physical storage nodes based on the determined first physical storage node and according to a first rule-based sorting manner; and storing at least M+1 blocks of the M data blocks and the N check blocks onto the at least M+1 different storage nodes, where K, M, and N are integers.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: October 14, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Bin Feng, Cheng Huang, Xuewen Gong
  • Publication number: 20140298090
    Abstract: Methods for data recovery and memory systems are provided. According to at least one such method, when defective data is read from a memory location, the data is recovered by an XOR operation on the remaining good data and associated RAID data to reconstruct the defective data. The defective data is excluded from the XOR operation.
    Type: Application
    Filed: May 15, 2014
    Publication date: October 2, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Troy Larsen, Martin Culley, Troy Manning
  • Patent number: 8850108
    Abstract: A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. The chassis includes power distribution, a high speed communication bus and the ability to install one or more storage nodes which may use the power distribution and communication bus. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: September 30, 2014
    Assignee: Pure Storage, Inc.
    Inventors: John Hayes, John Colgrove, Robert Lee, Peter Vajgel, Par Botes
  • Patent number: 8850100
    Abstract: A system, a method and a non-transitory computer readable medium are disclosed. The non-transitory computer readable medium may store instructions for: (I) interleaving at least two portions of a first codeword of a group of codewords between at least two flash memory planes while violating at least one ordering rule out of (a) an even odd ordering rule, (b) a programming type ordering rule, and (c) a codeword portions ordering rule; and (II) interleaving different portions of other codewords of the group of codewords between multiple flash memory planes while maintaining the even odd ordering rule, the programming type ordering rule and the codeword portions ordering rule. The at least two portions may be programmed to rows in different flash memory blocks, and the flash memory planes may belong to the same or multiple flash memory dies. The programming type ordering may define different decoupling sequence steps with sizes set for different programming types according to sensitivity to noise.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: September 30, 2014
    Assignee: Densbits Technologies Ltd.
    Inventors: Avi Steiner, Hanan Weingarten, Guy Azrad, Avigdor Segal
  • Publication number: 20140281691
    Abstract: A mass storage memory device is disclosed. The device includes a plurality of blades where two blades are used to store parity data corresponding to data stored in the other blades. The device also includes a controller configured to write data to the blades along stripes extending from the other blades to the two blades, where the parity data within a stripe is based on the data written to the other blades in the stripe, and wherein the parity data includes two or more types of parity data.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 18, 2014
    Applicant: Skyera, Inc.
    Inventors: Radoslav Danilak, Guiqiang Dong, Ladislav Steffko
  • Patent number: 8839024
    Abstract: Embodiments of the invention provide a device and method for warm booting whereby data restoration occurs at the powering-on of the host, and can therefore be performed by the boot disk. Specifically, when the system is powered on, a backup controller will send a notification to a DMA controller indicating the data restoration is needed. The backup controller will automatically resorts contents of a backup storage device to main memory. During the process, when the host requests data, the DMA controller reads the data from the backup storage unit and sends it to the host. Then, once data restoration is complete, normal operations can commence.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: September 16, 2014
    Assignee: Taejin Info Tech Co., Ltd.
    Inventor: Byungcheol Cho
  • Patent number: 8839028
    Abstract: A method is used in managing data availability in storage systems. A request to write new data to a disk of a plurality of disks of a data storage system is received. The plurality of disks includes first and second parity areas. The first parity area includes first parity information and the second parity area includes second parity information. Up to two disks of the plurality of disks are having a problem. Old data of the disk is reconstructed in a memory of the data storage system. The reconstructed old data of the disk is written to a parity area. The parity area is selected from the first or second parity areas based on a configuration preference. The new data is written to the parity area.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: September 16, 2014
    Assignee: EMC Corporation
    Inventors: Michael J. Polia, Jean Marie (Montes) Schiff, Kevin Schleicher, Kimchi Mai
  • Patent number: 8832493
    Abstract: A method begins by a processing module dispersed storage error encoding data to produce encoded data slices and updating directory metadata regarding storing the data in a dispersed storage network (DSN) memory to produce updated directory metadata. The method continues with the processing module dispersed storage error encoding the updated directory metadata to produce encoded directory metadata slices and transmitting one or more data slice write requests to the DSN that each include a first transaction number. The method continues with the processing module transmitting one or more directory metadata write requests to the DSN memory, wherein the one or more directory metadata write requests includes a second transaction number, and when a favorable write response condition exists, transmitting a commit request to the DSN memory to commit storage of at least one of: the encoded data slices and the encoded directory metadata slices.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: September 9, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Ilya Volvovski, Andrew Baptist, Wesley Leggette
  • Patent number: 8826067
    Abstract: A method begins by a processing module dispersed storage error encoding data to produce a set of encoded data slices and sending a set of write request messages to a set of dispersed storage (DS) units, wherein each of the set of write request messages includes an encoded data slice of the set of encoded data slices. The method continues with the processing module determining whether a pillar width number of favorable write response messages has been received within a write acknowledgement (ACK) time period. The method continues with the processing module executing a retry write process to at least one DS unit of the set of DS units from which a favorable write response message was not received during the write ACK time period when the pillar width number of favorable write response messages has not been received within the write ACK time period.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: September 2, 2014
    Assignee: Cleversafe, Inc.
    Inventor: Greg Dhuse
  • Patent number: 8819482
    Abstract: A distributed storage integrity system in a dispersed storage network includes a scanning agent and a control unit. The scanning agent identifies an encoded data slice that requires rebuilding, wherein the encoded data slice is one of a plurality of encoded data slices generated from a data segment using an error encoding dispersal function. The control unit retrieves at least a number T of encoded data slices needed to reconstruct the data segment based on the error encoding dispersal function. The control unit is operable to reconstruct the data segment from at least the number T of the encoded data slices and generate a rebuilt encoded data slice from the reconstructed data segment. The scanning agent is located in a storage unit and the control unit is located in the storage unit or in a storage integrity processing unit, a dispersed storage processing unit or a dispersed storage managing unit.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: August 26, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Greg Dhuse, Andrew Baptist, Zachary J. Mark, Jason K. Resch, Ilya Volvovski
  • Publication number: 20140237287
    Abstract: The present disclosure includes systems and techniques relating to implementing fault tolerant data storage in solid state memory. In some implementations, a method includes receiving a data request for a solid state memory; identifying a logical block grouping corresponding to the data request, wherein the logical block grouping indicates physical data storage blocks spanning at least two distinct memory units of the solid state memory; reading stored data and parity information from at least a portion of the physical data storage blocks spanning the at least two distinct memory units; and recovering data of at least one block of the logical block grouping based on the stored data and the parity information.
    Type: Application
    Filed: April 23, 2014
    Publication date: August 21, 2014
    Applicant: Marvell World Trade Ltd.
    Inventor: Gregory Burd
  • Patent number: 8812933
    Abstract: A memory system includes a nonvolatile memory device and a memory controller configured to control the nonvolatile memory device and configured to provide the nonvolatile memory device with error flag information including error location information of an error of data read from the nonvolatile memory device.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: August 19, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Sang-Hyun Joo, Kitae Park, Sangyong Yoon, Jinman Han
  • Patent number: 8799745
    Abstract: A controller of a storage control apparatus creates a fixed value, which is one or higher values conforming to a prescribed data pattern, with respect to first data, which is smaller than the size of a storage area of a storage device, creates a guarantee code related to a data area comprising the first data and the fixed value, and writes the data group comprising the data area and the guarantee code to the storage area. The controller reads a data group from the storage area, and determines whether or not more errors than the number of errors correctable by the guarantee code are included in this data group. In a case where the result of this determination is affirmative, the controller determines whether or not an error exists in the fixed value inside the data group.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: August 5, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Hideyuki Koseki
  • Patent number: 8799705
    Abstract: A disk array memory system comprises: a plurality of disks in a disk array for storage of content data and parity data in stripes, content data in a same stripe sharing parity bits of said parity data, each disk having a spare disk capacity including at least some of a predefined array spare capacity, said array spare capacity providing a dynamic space reserve over said array to permit data recovery following a disk failure event; a cache for caching content data prior to writing to said disk array; and a controller configured to select a stripe currently having a largest spare stripe capacity, for a current write operation of data from said cache, thereby to write all said data of said current write operation on a same stripe, thereby to maximize sharing of parity bits per write operation and minimize separate parity write operations.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: August 5, 2014
    Assignee: EMC Corporation
    Inventors: Renen Hallak, Tal Ben Moshe, Niko Farhi, Erez Webman
  • Publication number: 20140215263
    Abstract: A method begins with a set top box determining whether a content request is regarding playback of stored content or streaming of broadcast content. When the content request is regarding playback of stored content, the method continues with the set top box determining whether to retrieve the stored content for a group of set top boxes in a common area or from storage units DSN memory. When the stored content is to be retrieved from the group of set top boxes, the method continues with the set top box obtaining, from at least some of the set top boxes, the decode threshold number of encoded data slices for each set of encoded data slices corresponding to the stored content. The method continues with the set top box decoding, for each set of encoded data slices, the decode threshold number of encoded data slices to reconstruct the stored content.
    Type: Application
    Filed: March 31, 2014
    Publication date: July 31, 2014
    Applicant: CLEVERSAFE, INC.
    Inventors: Gary W. Grube, Timothy W. Markison
  • Publication number: 20140208156
    Abstract: A disclosed example apparatus includes a row address register (412) to store a row address corresponding to a row (608) in a memory array (602). The example apparatus also includes a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder (606) to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.
    Type: Application
    Filed: January 27, 2011
    Publication date: July 24, 2014
    Inventors: Naveen Muralimanohar, Aniruddha Udipi, Chatterjee Niladrish, Balasubramonian Rajeev, Alan Lynn Davis, Norman Paul Jouppi
  • Publication number: 20140201567
    Abstract: A method begins by a dispersed storage (DS) processing module encoding data using a dispersed storage error coding function to produce a set of encoded data slices. The method continues with the DS processing module encoding a first encoded data slice of the set of encoded data slices using a zero information gain (ZIG) function based on a second encoded data slice of the set of encoded data slices to produce a ZIG encoded data slice. The method continues with the DS processing module outputting the ZIG encoded data slice and a subset of encoded data slices of the set of encoded data slices, wherein the subset of encoded data slices includes less than a decode threshold number of encoded data slices and does not include the first or the second encoded data slice.
    Type: Application
    Filed: March 18, 2014
    Publication date: July 17, 2014
    Applicant: CLEVERSAFE, INC.
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 8775860
    Abstract: The invention relates to a method and a system for regenerating a failed storage node from one or more storage nodes storing an original file and also reconstructing the said original file. The method involves encoding the file segments using a XOR operation, decoding the encoded file segment using the XOR operation and regenerating the failed node by using the storage nodes which are in active position. The regenerated file segments are further written to a new storage node.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: July 8, 2014
    Assignee: Tata Consultancy Services Limited
    Inventors: Swanand Kadhe, Balaji Janakiram, Mariswamy Girish Chandra, Balamuralidhar Purushothaman
  • Patent number: 8775868
    Abstract: A system and method for adaptive RAID geometries. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to determine a first RAID layout for use in storing data, and write a first RAID stripe to the device group according to the first RAID layout. In response to detecting a first condition, the controller is configured to determine a second RAID layout which is different from the first RAID layout, and write a second RAID stripe to the device group according to the second layout, whereby the device group concurrently stores data according to both the first RAID layout and the second RAID layout.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: July 8, 2014
    Assignee: PURE Storage, Inc.
    Inventors: John Colgrove, John Hayes, Bo Hong, Ethan Miller
  • Publication number: 20140189424
    Abstract: A method for parity resynchronization in disk arrays, in which an intent log comprising a list of addresses of pieces of data stored in a data write cache is generated. The pieces of data of the data write cache are written to a disk while the pieces of data are withdrawn from the data write cache. When power supply is interrupted during writing of the data to the disk, a processor supplies power to the disk to resume an operation of the disk, checks whether parity mismatch has occurred on the data of the disk corresponding to the data address list, and corrects a parity mismatch block using a parity block. When the consistency of data is damaged by unexpected power interruption, data being written is compared with a pre-stored intent log, shortening the time required for parity resynchronization.
    Type: Application
    Filed: May 24, 2013
    Publication date: July 3, 2014
    Inventors: Jaeki Sim, Sung Hoon Baek
  • Publication number: 20140181578
    Abstract: A dispersed storage system includes a plurality of storage units that each include a partial rebuild grid module. The partial rebuild grid module includes partial rebuilding functionality to reconstruct one of a plurality of encoded data slices wherein the plurality of encoded data slices are generated from a data segment based on an error encoding dispersal function. In the partial rebuilding process, a data slice is rebuilt by combining in any order slice partials generated from at least a threshold number T of the plurality of data slices.
    Type: Application
    Filed: February 27, 2014
    Publication date: June 26, 2014
    Applicant: CLEVERSAFE, INC.
    Inventors: Greg Dhuse, Andrew Baptist, Zachary J. Mark, Jason K. Resch, Ilya Volvovski
  • Publication number: 20140164825
    Abstract: A data access request is received specifying a data block stored in a stripe of a parity group that includes a plurality of data storage devices to store data blocks and a parity storage device to store parity information for the data. The stripe includes a data block from each of the plurality of data storage devices and the stripe includes a parity block from the parity storage device. An error is detected in the data block specified by the data access request. The error is identified as a lost write error for the data block or a lost write error for the parity block. Identifying the error includes comparing a first storage device signature stored in a metadata field associated with the data block to a second storage device signature stored in a label block identifying a data storage device where the data block is stored.
    Type: Application
    Filed: November 22, 2013
    Publication date: June 12, 2014
    Applicant: NetApp, Inc.
    Inventors: Tomislav Grcanac, Atul Goel, Jagadish Vasudeva, Gururaj Mj
  • Patent number: 8751862
    Abstract: A fast rebuild mechanism that includes a background initialization mechanism. The fast rebuild mechanism allows a RAID controller to be made aware of what blocks are actually in use so that only those blocks are rebuilt after a disk drive failure. The fast rebuild mechanism also includes functionality for an IO controller (such as storage controller) to detect whether a block has stored data to indicate that the block has valid data when the block is accessed.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: June 10, 2014
    Assignee: Dell Products L.P.
    Inventors: Jacob Cherian, Rohit Chawla
  • Patent number: 8751859
    Abstract: A data validation method comprises associating a validation chunk with one or more data chunks stored on one or more storage mediums. The validation chunk comprises validation information for verifying whether data recorded in a subdivision of the one or more data chunks is lost. A request is received for an operation to be performed on first data stored in a first subdivision of a first data chunk from among said one or more data chunks. One or more portions of the validation information are examined to determine whether the data recorded in said first subdivision is deemed to be lost.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: June 10, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ralph A. Becker-Szendy, Veera W. Deenadhayalan, D. Scott Guthridge, James C. Wyllie
  • Publication number: 20140149788
    Abstract: Systems and methods are disclosed for storing the firmware and other data of a flash memory controller, such as using a RAID configuration across multiple flash memory devices or portions of a single memory device. In various embodiments, the firmware and other data used by a controller, and error correction information, such as parity information for RAID configuration, may be stored across multiple flash memory devices, multiple planes of a multi-plane flash memory device, or across multiple blocks or pages of a single flash memory device. The controller may detect the failure of a memory device or a portion thereof, and reconstruct the firmware and/or other data from the other memory devices or portions thereof.
    Type: Application
    Filed: February 3, 2014
    Publication date: May 29, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Cory Reche
  • Patent number: 8738963
    Abstract: A system comprising a plurality of storage systems, which uses storage devices of multiple levels of reliability. The reliability as a whole system is increased by keeping the error code for the relatively low reliability storage disks in the relatively high reliability storage system. The error code is calculated using hash functions and the value is used to compare with the hash value of the data read from the relatively low reliability storage disks.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: May 27, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Tomohiro Kawaguchi, Akira Yamamoto
  • Publication number: 20140136886
    Abstract: A method and system of optimizing the performance, capacity and data redundancy in a storage system by defining the LBA range on each storage element managing that corresponding range (slice) on each device using a data protection method optimized for the performance and level of data protection required. The creation of such a storage array along with the replacement of failed elements and the expansion of the capacity through the addition of additional elements is managed is an automatic and transparent manner.
    Type: Application
    Filed: November 12, 2012
    Publication date: May 15, 2014
    Applicant: GREENBYTES, INC.
    Inventor: Robert Petrocelli
  • Patent number: 8726120
    Abstract: A method begins with a processing module receiving an access request for the data object. The method continues by ascertaining that the data object is divided into a plurality of data segments and that plurality of data segments are dispersed storage error encoded to produce a plurality of sets of encoded data slices. The method continues by ascertaining batching of the plurality of sets of encoded data slices, wherein the plurality of sets of encoded data slices are arranged into a set of batched encoded data slices. The method continues by outputting a set of access requests for the set of batched encoded data slices to storage units of the DSN.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: May 13, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Andrew Baptist, Ilya Volvovski, Wesley Leggette, Greg Dhuse, Jason K. Resch
  • Patent number: 8726127
    Abstract: A method begins by a computing device determining that dispersed storage network (DSN) memory is to be accessed regarding data. The method continues when the computing device is paired with a DSN access token module with the DSN access token module retrieving a plurality of sets of at least a threshold number of dispersed storage (DS) error coding function slices from the DSN memory via the computing device. The method continues with at least one of the computing device and the DSN access token module decoding the plurality of sets of the at least a threshold number of DS error coding function slices using a default DS error coding function to recapture a DS error coding function and executing, by one or more of the computing device and the DSN access token module, the DS error coding function to access the DSN memory regarding the data.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 13, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Gary W. Grube, Timothy W. Markison, Greg Dhuse, Jason K. Resch, Ilya Volvovski, Wesley Leggette
  • Patent number: 8726070
    Abstract: Out-of-order reconstruction of a RAID storage device at a replacement storage device enables the replacement storage device to execute I/O for reconstructed regions during reconstruction of the replacement storage device. In one embodiment, the failed storage device is analyzed to find recoverable information, which is copied to the replacement storage device to reduce the need for reconstruction. In another embodiment, the priority for region's reconstruction is increased upon detection of an I/O to the region. The I/O is queued until reconstruction of the region and then executed after reconstruction of that region so that I/O at the region need not be repeated during reconstruction of the remainder of the replacement storage device.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: May 13, 2014
    Assignee: Dell Products L.P.
    Inventors: Chandrashekar Nelogal, Bang Kim Le, Frank Widjaja Yu
  • Patent number: 8725944
    Abstract: The present disclosure includes systems and techniques relating to implementing fault tolerant data storage in solid state memory. In some implementations, a method includes receiving a request for data stored in a solid state memory, and identifying a logical block grouping for logical data blocks of the requested data, the logical data blocks corresponding to the solid state memory, and the logical block grouping comprising at least one physical data storage block from two or more solid state physical memory devices. The method also includes reading the stored data and a code stored in the identified logical block grouping, and comparing the code to the stored data to assess the requested data.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 13, 2014
    Assignee: Marvell World Trade Ltd.
    Inventor: Gregory Burd
  • Patent number: 8719620
    Abstract: The present invention reduces the amount of rebuild processing and executes a rebuild process efficiently. Multiple storage devices configure a parity group. Of the multiple storage devices, a prescribed storage device in which a failure has occurred is blocked. Each storage device stores management information. The management information manages from among the storage areas of the storage device a prescribed area having data from a higher-level apparatus. A controller determines whether a storage area of the prescribed storage device is the prescribed area based on the management information, and executes a rebuild process with respect to the area determined to be the prescribed area.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: May 6, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Toshiya Seki
  • Patent number: 8719621
    Abstract: A system includes a write module, a read module, and a parity module. The write module is configured to modify first user data stored on a first member of a redundant array of independent disks (RAID) using second user data. The read module is configured to read the first user data and first parity data corresponding to the first user data from a solid-state disk associated with the RAID if at least one of the first user data and the first parity data are stored on the solid-state disk, or from the RAID if the at least one of the first user data and the first parity data are not stored on the solid-state disk. The parity module is configured to generate second parity data based on the first user data, the second user data, and the first parity data.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: May 6, 2014
    Assignee: Marvell International Ltd.
    Inventor: Sandeep Karmarkar
  • Publication number: 20140122925
    Abstract: A method begins by a dispersed storage (DS) processing module of a storage unit receiving, over time, access requests regarding reading or writing of various data blocks. The method continues with the DS processing module establishing an internal verification access rate for verifying data blocks stored in a memory device of the storage unit based on a rate of the access requests and a maximum access rate of the memory device. The method continues with the DS processing module generating internal verification requests in accordance with the internal verification access rate, coordinating the internal verification requests and the access requests for accessing the memory device, and accessing the memory device based on the internal verification requests to verify the data blocks.
    Type: Application
    Filed: September 16, 2013
    Publication date: May 1, 2014
    Applicant: CLEVERSAFE, INC.
    Inventors: Andrew George Peake, Jason K. Resch, Ilya Volvovski
  • Patent number: 8713358
    Abstract: A method begins a first rebuilder application identifying a data slice having a storage error. The method continues with the first rebuilder application or a second rebuilder application identifying a data segment based on the identified data slice. The method continues with the second rebuilder application identifying one or more other slice servers that are storing other data slices of the encoded data segment. The method continues with the second rebuilder application receiving a sufficient number of the other data slices to reconstruct the data segment and decoding them to reconstruct the data segment. The method continues with the second rebuilder application encoding the reconstructed data segment in accordance with the information dispersal algorithm to produce a new set of data slices and selecting one of them as the rebuild data slice.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: April 29, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Vance T. Thorton, Jamie Bellanca, Dustin M. Hendrickson, Zachary J. Mark, Ilya Volvovski
  • Publication number: 20140115384
    Abstract: A storage system comprises a first storage device having a first plurality of hard disk drives and a first controller. The first controller stores data in the first plurality of hard disk drives by stripes. Each stripe includes M data and N parity data allocated to M+N hard disk drives of the first plurality of hard disk drives. A first hard disk drive includes data or parity data of both a first stripe of the stripes and a second stripe of the stripes, while a second hard disk drive includes data or parity data of only one of the first stripe or the second stripe. During data recovery involving failure of one of the first plurality of hard disk drives, the data in the failed hard disk drive is recovered for each stripe by calculation using data and parity data in other hard disk drives for each stripe.
    Type: Application
    Filed: December 24, 2013
    Publication date: April 24, 2014
    Applicant: Hitachi, Ltd.
    Inventor: Tomohiro KAWAGUCHI
  • Patent number: 8707104
    Abstract: Embodiments of the solid-state storage system provided herein are configured to perform improved mechanisms for testing of error recovery of solid state storage devices. In some embodiments, the system is configured to introduce or inject errors into data storage commands or operations performed in the non-volatile memory. Injected errors include corruption of data stored in the non-volatile memory, deliberate failure to execute storage operations, and errors injected into communication protocols used between various elements of the device. In some embodiments, injected errors can include direct errors that trigger an immediate execution of error recovery mechanisms and delayed errors that trigger execution of error recovery mechanisms at a later time. Error recovery mechanisms can be tested in an efficient, reliable, and deterministic manner to help ensure effective operation of storage devices. The integrity of non-volatile memory can also be tested.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: April 22, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventor: Sebastien A. Jean
  • Patent number: 8707134
    Abstract: According to one embodiment, a data storage apparatus comprises a channel controller, an encoding module, and a data controller. The channel controller configured to control data input and output to and from nonvolatile memories for channels. The encoding module configured to generate encoded data for an interchannel error correction process, using data stored in each of the nonvolatile memories. The data controller configure to manage the encoded data in units of logical blocks when the channel controller writes the encoded data in parallel to the channels, and to allocate parity data contained in the encoded data to planes of the same channel in each logical block.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: April 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kyosuke Takahashi, Motohiro Matsuyama
  • Patent number: 8707093
    Abstract: A system, method and program product, the system in embodiments comprising: one or more computers operably connected to one or more computer-readable storage media comprising computer-readable program code to perform steps: associating a first plurality of data disk blocks; generating checksum data on a second plurality of checksum disk blocks, using an m-out-of-n encoding algorithm; generating a third plurality of redundant storage disk blocks, using an 1-out-of-n encoding algorithm that allows for reconstruction using a second recovery algorithm of a selected disk block by reading a proper subset of remaining data disk blocks, reconstructing a single one of the data disk blocks when one or more reconstruction criteria are met, using the second recovery algorithm; reconstructing, when two or more of the data disk blocks are lost, the two or more of the data disk blocks and/or checksum disk blocks that are lost, using the first recovery algorithm.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: April 22, 2014
    Assignee: Google Inc.
    Inventor: Richard Lee Sites
  • Patent number: 8707092
    Abstract: Memory devices and methods are described that include serially chained memory devices. In one or more of the configurations shown, a serial chain of memory devices includes a number of memory devices, and an error recovery device at an end of the chain. In one configuration shown, the serial chain of memory devices includes a chain of devices where each device is a stacked die memory device. Methods are described that show using the error recovery device in write operations and data recovery operations.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventor: David R. Resnick