Abstract: A network equipment test device provides a user interface for user specification of a test traffic source, a test traffic destination, SUT and waypoint topology and one or more test cases. In response to receiving the specified input from the user via the interface, the test traffic source is automatically configured to send the test traffic to the destination via the SUT. The waypoint is automatically configured to measure the test traffic. When the test is initiated, test traffic is sent from the test traffic source to the test traffic destination via the SUT and the at least one waypoint. Test traffic is measured at the waypoint, and traffic measurement results are displayed on a visual map of SUT topology.

Abstract: The subject matter described herein includes methods, systems, and computer readable media for providing for specification or autodiscovery of DUT topology information and for using the DUT topology information to generate DUT-topology-specific test results. One exemplary method includes, providing for specification or autodiscovery of DUT topology information associated with or more devices under test (DUT). The method further includes transmitting test packets to the at least one DUT. The method further includes receiving packets transmitted from or through the at least one DUT. The method further includes using the DUT topology information and the received packets to generate DUT-topology-specific test results.

Abstract: A system employing vector signal generator (VSG) and vector signal analyzer (VSA) modules or cards that are configured to test multiple devices under test simultaneously. Each VSG is configured to generate multiple RF test signals and send them to multiple devices under test simultaneously. Similarly, each VSA is configured with multiple signal receiving modules connected to a single controller or memory. Each signal receiving module receives an RF signal from a device under test, converts it to a baseband digital signal, and transmits this digital signal to the VSA's memory. A single RF testing system can employ multiple such VSGs and VSAs, each capable of evaluating multiple devices under test. Each VSG/VSA can further be tuned for operation in discrete or defined frequency bands, which are narrower than those for conventional RF testers, and which can correspond to various wireless standards.

Abstract: The present disclosure provides a method, a device and a baseband chip for receiving service data in a communication system. The method includes: receiving service data including a plurality of data blocks, where each of the plurality of data blocks comprises an information code and a check code; performing a first check and a second check on the service data; and outputting a predetermined number of information codes which pass the first check and are performed with a second check computation of the second check. The present disclosure saves memory space of the baseband chip.

Abstract: A method of using tester data packet signals and control instructions for testing a radio frequency (RF) data packet signal transceiver device under test (DUT) capable of communicating using multiple radio access technologies (RATs) having one or more mutually distinct signal characteristics. During mutually alternating time intervals, selected ones of which are substantially contemporaneous, tester data packet signals and control instructions are used for concurrent testing and configuration for testing, respectively, of multiple RATs of the DUT.

Abstract: Various techniques relating to drive train control are disclosed. In an embodiment, in a first mode of operation communication between a controller and a submodule of the drive train takes place via a first communication channel and optionally additionally via a second communication channel. In a second mode of operation, upon failure of the first communication channel, communication with the submodule of the drive train takes place via the second communication channel.

Abstract: Exemplary receiving apparatus receives serial data that includes contiguous blocks each having M-bit known pattern. The apparatus includes a serial-parallel conversion circuit that arranges bits in the serial data to generates N-bit wide (N<M) parallel data, a register group including a first register that stores a word of the parallel data and second registers to which the word of the parallel data is sequentially shifted and stored, a comparing circuit that compares the known pattern with storage patterns each including M contiguous bits stored in the register group, and a detecting circuit. The detecting circuit detects reception of the serial data if the comparing circuit detects a first match between the known pattern and a first one of the storage patterns, and a second match between the known pattern and a second one of the storage patterns that starts with a specific bit during a specific clock cycle.

Abstract: An apparatus for network testing receives data from a test network, validates, via a physical layer controller (PHY), a link to the test network based on the received data. A rate of the received data is throttled from the test network to a lower rate in response to a first condition. The received data is then processed at the lower rate via a media access controller (MAC).

Abstract: A system for parallel radio frequency (RF) testing. The system includes a plurality of signal generators, a plurality of signal analyzers, a data bus connected to the plurality of signal generators, and a controller. The controller has a connection to the data bus so as to be in electronic communication with the plurality of signal generators, and has a plurality of point to point links to respective ones of the signal analyzers so as to be in electronic communication with the plurality of signal analyzers.

Abstract: A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.

Abstract: A communication link analyzer is disclosed for analyzing a communication link. The communication link analyzer may analyze bitstreams that have been FEC encoded and are transmitted according to one or more 10 Gigabit Ethernet standards, 40 Gigabit Ethernet standards, and other such standards. The communication link analyzer may maintain a running count of the errors detected for the bit positions of a 2112-bit FEC-encoded datablock. These errors may include, but are not limited to, baseline wander, deterministic jitter, and predictive-interval errors. When a given error threshold is met or exceeded for one or more received bitstreams, the communication link analyzer may then attempt a diagnosis of the communication link. Using previously provided empirical data, the communication link analyzer may provide a diagnosis of the communication link based on the error type threshold that was met or exceeded and the bit position associated with the error type threshold.

Abstract: A data processing system is disclosed including a data detector, a data decoder and a microcontroller. The data detector is operable to apply a data detection algorithm to generate detected values for data sectors. The data decoder is operable to apply a data decode algorithm to a decoder input derived from the detected values to yield decoded values. The microcontroller is operable to configure the data detector and the data decoder to apply the data detection algorithm and the data decode algorithm.

Abstract: A communication circuit (an interface section) includes an input section (a input shift register) to which a data signal is input, an output section (and output shift register) adapted to output a reply signal in a case in which the data signal is input, and a command determination section adapted to perform propriety determination of a command signal included in the data signal, and the output section outputs a negative acknowledgement signal as the reply signal in a case in which it is determined in the propriety determination that the command signal is improper.

Abstract: A chip applied to a serial transmission system includes an input terminal, a core circuit, an output terminal, a first transmission line, a second transmission line and a spare transmission line, where the input terminal is used to receive an input signal from a source outside the chip, the output terminal is used to output an output signal, the first transmission lines is coupled between the input terminal and the core circuit, the second transmission line is coupled between the core circuit and the output terminal, and the spare transmission line is coupled between the input terminal and the output terminal. When the core circuit cannot process the input terminal normally, the input signal is directly transmitted to the output terminal via the spare transmission line, and the input signal serves as the output signal to be outputted from the output terminal.

Abstract: A method for analyzing a cause of link failure, a method of network optimization and an apparatus. The method includes: determining, when link failure occurs, detailed triggering information causing the link failure; analyzing a cause of link failure according to the detailed triggering information causing the link failure; and transmitting the cause of link failure obtained by analysis to a network side. With the embodiments of the present invention, the UE may transmit detailed causes in detailed configuration information obtained by analysis to the network side, so that the network side determines a root cause of link failure according to the cause or according to the cause in combination with a measurement result, so as to take corresponding measures to optimize the network more accurately.

Abstract: A wireless device couples an electronic device employing a wired-link protocol to, for example, a wireless personal area network (WPAN). The wireless device comprises a wired interface configured for coupling to the electronic device, a wired transceiver coupled to the wired interface, the at least one wired transceiver configured for functioning as a terminus of a wired link coupled to the electronic device, and a wireless transmitter or transceiver coupled to the wired transceiver and configured for functioning as a terminus of a wireless link in the WPAN. The wireless device may be configured for coupling a plurality of dissimilar wired devices together via a wireless link.

Abstract: A system includes a packet generator and a packet checker. The packet generator is operable to operable to generate a packet for transmission to a destination device. The packet includes a plurality of fields, including a code field that is operable to store a code generated based on an expected modification to the packet during transmission. The packet checker is associated with the destination device and is operable to receive the packet.

Abstract: Systems, methods, and devices related to testing receive equipment. A test signal generator is coupled to both a receiver and an antenna. The receiver is also coupled to the antenna and a test signal verifier. A test signal is synthesized at the generator and is routed to the receiver. Once the verifier verifies that the test signal was received by the receiver, this ensures that the equipment coupled to the receiver, as well as the receiver itself, is in operating condition. Switches or other means of routing the test signal between the different components of the system can also be present.

Abstract: Systems, methods and computer program products are disclosed for managing availability of a slave components executing in a distributed system. A master server and a heartbeat protocol may be provided. The heartbeat protocol may define state machines for the master server and/or the slave components. The master server and/or the slave components may act in accordance with the state machines to manage availability of the slave components in the distributed system.

Abstract: A system and method for the execution of a program comprises a user-defined sequence of standard hardware and analysis module commands of an instrument, in the context of a tester comprising a plurality of VSAs and VSGs, or other hardware measurement modules types, where the coordination of command execution and resource availability is built into the system as an inherent part of its overall architecture. As such, the commands are the same as those ordinarily executed in piecemeal fashion, but are now automatically and sequentially executed in an atomic and deterministic manner through the coordinated interaction of embodiments of the invention.

Abstract: A method and apparatus for multi-site testing of computer memory devices. An embodiment of a method of testing computer memory devices includes coupling multiple memory devices, each memory device having a serializer output and a deserializer input, wherein the serializer output of a first memory device is coupled with a deserializer input of one or more of the memory devices of the plurality of memory devices. The method further includes producing test signal patterns using a test generator of each memory device, serializing the test signal pattern at each memory device, and transmitting the serialized test pattern for testing of the memory devices, wherein testing of the memory devices includes a first test mode and a second test mode.

Abstract: A method and system for preserving privacy related to networked media consumption activity including: Source privacy zones are defined and associated with privacy standards. Privacy standards include frequency criteria governing the storage of datasets including information associated with networked media consumption activity collected from the source privacy zone. Transaction requests including a networking protocol address are received over a network from a client device at a target location by a networked privacy system. The source privacy zone associated with the client device is identified. Using the networking protocol address to access characteristics having characteristic value(s), a dataset can be created including associating the networked media consumption activity with the characteristic and characteristic value(s). The dataset is pre-processed to comply with the privacy standards. The networking protocol address is discarded.

Abstract: A management device comprises a failure detection unit 10 which detects a failure in a plurality of paths connecting servers, on at least one of which a virtual machine operates, with a storage device, a specifying unit 11 which specifies the virtual machine operating on the failed server that is the server connected by the path in which the failure is detected, a redundancy calculation unit 12 which calculates, for each of the servers, a first redundancy degree of the server with respect to the storage device, a selection unit 13 which selects, among the servers, a server having the degree of redundancy higher than the degree of redundancy of the failed server on the basis of the first redundancy degrees of the servers, and a transmission unit 14 which transmits migration instruction information including an identifier of the specified virtual machine and an identifier of the selected server.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: A method is provided for improving the acquisition of a data set transmitted repeatedly in a difficult environment, which is particularly appropriate to satellite radionavigation systems. The main characteristic of the method is to provide “contextual” aid relating to the transmitted data by indicating the nature and the possible updating of these data so that the receiver can accumulate the energy when the data are repeated in an identical manner. These aid data being short, it is possible to obtain good quality of reception and protection of this aid by virtue of its longer coding than that of the data.

Abstract: A testing apparatus includes a scenario processing unit that executes a test scenario for operating the testing apparatus to imitate the operation of a base station, a communication unit capable of transmitting and receiving a message to and from a mobile communication terminal, a layer processing unit for processing a message for each layer, a log data storing unit for storing log data indicating transmission of messages between the layers, and a display controller for creating a transmission schedule based on the extracted data associated with system information and causing a display unit to display the transmission schedule. The transmission schedule is written in a tabular form in which a block type of the system information is displayed at a position to which a frame for transmitting the system information is allocated.

Abstract: A method and an apparatus for performing link equalization testing via a physical layer test and measurement system. The system includes a protocol aware test apparatus for transmitting testing data, a device under test for receiving the transmitted testing data, and an oscilloscope for receiving an output waveform from the device under test. The protocol aware test apparatus selects a first of a plurality of preset values, sends an equalization signal from the protocol aware test apparatus to the device under test, and changes a speed of communication to a predetermined speed and sends a compliance pattern to the device under test after placing the device under test in a loopback mode. A waveform output from the device under test is captured by the oscilloscope, and is analyzed to determine compliance of the device under test with a predetermined link equalization speed in accordance with a predetermined protocol.

Abstract: System and method for testing a radio frequency (RF) device under test (DUT) communicating using multiple radio access technologies (RATs). Single data signal sequences having characteristics of multiple RATs as prescribed by signal standards are exchanged between a tester and DUT. The tester and DUT process received signal sequences substantially in parallel with their reception. A pattern of contemporaneous signal sequence reception and processing continues for as many RATs as the DUT is capable of supporting.

Abstract: A method (400) for creating a group shared distributed reservation in a wireless network. The method comprises collecting information about the distributed reservation availabilities of devices in the wireless network (S410); selecting a group of shared devices to be included in the group shared distributed reservation based on the collected information (S420); sending a reservation request to each device in the group of shared devices (S430); and updating the group of shared devices to include only devices that accept the reservation request (S460), thereby creating a group shared distributed reservation of medium access time slots.

Abstract: The present disclosure provides a method, a device and a baseband chip for receiving service data in a communication system. The method includes: receiving service data including a plurality of data blocks, where each of the plurality of data blocks comprises an information code and a check code; performing a first check and a second check on the service data; and outputting a predetermined number of information codes which pass the first check and are performed with a second check computation of the second check. The present disclosure saves memory space of the baseband chip.

Abstract: A method and an apparatus for data management through timer compensation in a wireless communication system are provided. In the method, when a data loss occurs at a first point, whether a data loss has occurred previously and so whether a timer is being driven are determined. Whether the driven timer stops or expires at a second point is determined. When the timer stops or expires at the second point, a timer value is compensated for with consideration of a time difference between the first point and the second point. A timer for the data loss of the first point is restarted based on the compensated timer value. Therefore, a delay of a retransmission request time for lost data in an RLC (Radio Link Control) layer may be minimized.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells.

Abstract: The present invention relates to a fault protection method and a fault protection device for an inter-domain link of a multi-domain network. The invention may be particularly applied to multi-domain networks providing end to end services such as an Ethernet service. Embodiments of the invention use a link protection group for an inter-domain link. Link protection group information relating to the link protection group is used to identify a replacement inter-domain link for a faulty inter-domain link that is configured for an inter-domain service. Once the replacement link is identified, the routing of the inter-domain service may be re-configured from the network element ports of the faulty inter-domain link to the network element ports of the identified second inter-domain link.

Abstract: To improve performance of a decoder even in a system with the coder configuration determined by inserting a doping bit sequence known between a transmission apparatus and a reception apparatus in an information bit sequence to transmit, the transmission apparatus is a transmission apparatus that transmits radio signals to the reception apparatus, and is provided with a doping section 23 that inserts a doping bit sequence which is known between the transmission apparatus and the reception apparatus in an information bit sequence to transmit to the reception apparatus, coding sections 11a, 11b that perform error-correcting coding on a bit sequence with the doping bit sequence inserted therein, a puncturing section that performs puncturing on a bit sequence subjected to the error-correcting coding, and a wireless transmission section 24 that transmits a bit sequence subjected to the puncturing.

Abstract: A chip operating method is provided which includes enabling a transmission mechanism or a receiving mechanism of the chip while normally operating the chip. The method further includes enabling both of the transmission mechanism and the receiving mechanism of the chip while testing the chip.

Abstract: A Joint Test Action Group (JTAG) apparatus and a method for implementing JTAG data transmission are disclosed. The JTAG apparatus includes an isolation circuit connected with a processor and pins of a JTAG programmable logic device, wherein the isolation circuit has a register/registers corresponding to the pins of the JTAG programmable logic device. Based on a high or low level signal written into the register/registers of the isolation circuit by the processor, the isolation circuit drives the pins of the JTAG programmable logic device, and transmits the JTAG data corresponding to the high or low level signal from the processor to the JTAG programmable logic device. The isolation circuit is used to implement protection of a JTAG interface or a serial port of a personal computer connected with the JTAG apparatus.

Abstract: Systems and methods are disclosed for precise event time measurement. High speed serializer and deserializer circuitry are combined with high speed logic elements, such as exclusive-OR (XOR) or exclusive-not-OR (XNOR) logic circuitry, to achieve a measurement precision based upon a bit period associated with the high speed circuitry rather than upon slower reference clock signals. In certain embodiments, the disclosed systems and methods generate digital signal patterns, serialize them, transmit them as a high speed bit stream, utilize an event occurrence signal and logic circuitry to produce a modified bit stream, deserialize the modified bit stream to produce a modified digital signal pattern, compare the modified signal pattern with a predicted signal pattern, and determine bit positions or bit periods at which events occur based upon this comparison. These bit positions can then be used to generate precise timestamps and related time information for detected events.

Abstract: A test device 50 includes a message processing unit 53 capable of generating a message to be transmitted to a mobile communication terminal 10 that is a test subject, according to a test scenario, a layer processing unit 54 that processes data of the generated message for each layer, a communication unit 55 capable of transmitting data of the message processed by the layer processing unit to the mobile communication terminal, a log data generation unit 56 that generates as log data, and a specific message processing unit 51 that specifies log data in downlink related to a designated log and outputs communication data included in the specified log data as specific communication data to the layer processing unit, in which the test device 50 outputs the specific communication data from the communication unit to the mobile communication terminal through the layer processing unit.

Abstract: Methods and apparatuses for identifying a physical link interconnecting network devices and/or correlating a designation of an interface on a network device to a physical location of the interface on the network device are disclosed herein. A method for identifying a physical link interconnecting a network device and a peer network device, where the network device and the peer network device each have an interface and a corresponding indicating light, may include: sending a packet from the interface of the network device to the interface of the peer network device over the physical link; causing the indicating light corresponding to the interface of the peer network device to blink at a predetermined cadence for a predetermined period of time upon receipt of the packet to enable recognition of the peer network device.

Abstract: A communication control apparatus includes a storage unit and a processor. The storage unit stores, in association with a port number, first address information regarding apparatuses connected to a port identified by the port number. The processor receives a first affected address list containing second address information regarding apparatuses which may be affected by a trouble, extracts the first address information stored in the storage unit in association with a port number of a port via which the first affected address list has been received, selects third address information which is included in both the first and second address information, updates the first affected address list by replacing the second address information with the third address information to acquire a second affected address list, and transmits the second affected address list via each port other than the port via which the first affected address list has been received.

Abstract: System and method for testing a radio frequency (RF) device under test (DUT) communicating using multiple radio access technologies (RATs). Single data signal sequences having characteristics of multiple RATs as prescribed by signal standards are exchanged between a tester and DUT. The tester and DUT process received signal sequences substantially in parallel with their reception. A pattern of contemporaneous signal sequence reception and processing continues for as many RATs as the DUT is capable of supporting.

Abstract: The invention relates to a method for transmitting digital data, in particular in automation technology, in which a digital code word (R) received via a channel is corrected and verified as to its validity by means of a channel decoder (7), and an invalid code word is rejected and optionally requested once again, while a valid code word (C?) is further processed. If a metric (8) is cumulatively used with an encoding process, the probability of remaining bit errors in the whole method can be significantly reduced, thus making it possible to use the method in automation technology.

Abstract: A system and method for the execution of a program comprises a user-defined sequence of standard hardware and analysis module commands of an instrument, in the context of a tester comprising a plurality of VSAs and VSGs, or other hardware measurement modules types, where the coordination of command execution and resource availability is built into the system as an inherent part of its overall architecture. As such, the commands are the same as those ordinarily executed in piecemeal fashion, but are now automatically and sequentially executed in an atomic and deterministic manner through the coordinated interaction of embodiments of the invention.

Abstract: A system includes a transmitting device configured to transmit a packet, and a receiving device connected through a switch device to the transmitting device, the receiving device being configured to receive the packet, wherein the switch device includes a first memory storing first expected value information indicative of an expected value of a fixed value region, the fixed value region being a region whose value is determined in advance in a transaction layer packet, and a switch control unit configured to compare a value of the fixed value region of the transaction layer packet received from the transmitting device with the expected value and make an error response to the transmitting device if the value of the fixed value region is different from the expected value.

Abstract: In one or more embodiments, an intelligent communications device is disclosed. In one embodiment, an apparatus for managing a network connection of the intelligent communications device is disclosed. The apparatus includes a communication module for monitoring the network connection through a first port that is independent of a network port. The first port is associated with a computer-executable application that is operative to detect failure of the network connection. The apparatus further includes a detection module for detecting a failure of the network connection at the network port and, in response to the failure, causing the intelligent communications device to reconnect to the network. The apparatus also includes a power supply module for iteratively power-cycling operation of the intelligent communications device in response to a failed network connection.

Abstract: A method includes generating trace data at a device associated with data communication to and from a computer storage device through an appropriate communication link therefor and transmitting the trace data through the appropriate communication link. The trace data is configured to enable debugging of a set of instructions associated with the device. The method also includes capturing the trace data transmitted through the appropriate communication link through a protocol analyzer, a host system or the protocol analyzer coupled to the host system and analyzing the trace data therein to obtain information associated with the set of instructions associated with the device. The protocol analyzer, the host system or the protocol analyzer coupled to the host system is configured to be external to the device associated with the data communication to and from the computer storage device.

Abstract: A self-test loopback apparatus for an interface is disclosed. In one embodiment, a bidirectional interface of an integrated circuit includes a transmitter coupled to an external pin, a first receiver coupled to the external pin, and a second receiver coupled to the external pin. During operation in a test mode, the first receiver may be disabled. The transmitter may transmit test patterns generated by a built-in self-test (BIST) circuit, and compare those test patterns to patterns received by the second receiver. The second receiver may be implemented as a Schmitt trigger (wherein the first receiver may be a standard single-bit comparator). When operating in functional mode, the second receiver may be disabled.

Abstract: A system and method for the execution of a program comprises a user-defined sequence of standard hardware and analysis module commands of an instrument, in the context of a tester comprising a plurality of VSAs and VSGs, or other hardware measurement modules types, where the coordination of command execution and resource availability is built into the system as an inherent part of its overall architecture. As such, the commands are the same as those ordinarily executed in piecemeal fashion, but are now automatically and sequentially executed in an atomic and deterministic manner through the coordinated interaction of embodiments of the invention.

Abstract: A system and method for the execution of a program comprises a user-defined sequence of standard hardware and analysis module commands of an instrument, in the context of a tester comprising a plurality of VSAs and VSGs, or other hardware measurement modules types, where the coordination of command execution and resource availability is built into the system as an inherent part of its overall architecture. As such, the commands are the same as those ordinarily executed in piecemeal fashion, but are now automatically and sequentially executed in an atomic and deterministic manner through the coordinated interaction of embodiments of the invention.