Abstract: An apparatus for testing a communication circuit includes a detection module and a capture module. The detection module provides an enable signal in response to receiving at least one predetermined plurality of data from a communication device under test. The capture module captures at least one other predetermined plurality of data in response to the enable signal.

Abstract: Relating with board numbers of the boards mounted with the logic circuits and mounted places on the boards and in relation to log information to be collected from the logic circuits, analysis information describing information to be processed when the log information is generated, information of a condition for which the log information is to be valid, and information of a condition for which the log information is to be invalid are defined for analyzing failures using the analysis information based on the logic circuits. Upon the realization of the failure analysis based on the logic circuits, the analysis information further describes information of the priority of the log information to realize a thorough analysis of critical failures.

Abstract: A system includes a plurality of electrical switches. Every switch is associated with at least one monitoring device for detecting the respective switching condition of the switch. All of the monitoring devices are interconnected through a data connection through which the switching conditions of all of the switches are made known to every monitoring device.

Abstract: Provided is a semiconductor test apparatus that tests a device under test, comprising a test unit that tests a device under test; and a serial transmitting section that transmits transmission data back and forth between the test unit and a control section controlling the test unit. The serial transmitting section includes a data sending section that sends a plurality of pieces of the transmission data in a predetermined order; a resending control section that resends the transmission data; and an expected acknowledgement ID storage section that stores an expected acknowledgement ID indicating identification data that is expected to be attached to an acknowledgement signal received on a transmission side. The resending control section judges whether resending is necessary based on (i) whether resend count information indicates that a piece of transmission data is resent data and (ii) the expected acknowledgment ID in the expected acknowledgement ID storage section.

Abstract: A system and method for verifying the receive path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., networks) and output sources (e.g., hosts, host buses) is modeled in a verification layer that employs multiple queues to simulate receipt of packets, calculation of destination addresses and storage of the packet data by the device. Call backs are employed to signal completion of events related to storage of packet data by the device and modeling of data processing within the verification layer. Processing of tokens within the verification layer to mimic the device's processing of corresponding packets is performed according to a dynamic DMA policy modeled on the device's policy. The policy is dynamic and can be updated or replaced during verification without interrupting the verification process.

Abstract: In a method of handling errors in a digital system that includes a root complex in data communication with at least one endpoint, the endpoint including at least one advanced error reporting register, an error is detected by the endpoint. Error data indicative of the error is stored in an advanced error reporting register. An indication of which transaction caused the error is stored in a secondary location. An error message packet that includes the error data and the indication of which transaction caused the error is generated. The error message packet is transmitted to the root complex. The root complex is caused to take a preselected action in response to the error message packet.

Abstract: An approach is provided for bit error rate characterization. A test signal representing one or more Ethernet frames exhibiting a particular bit error rate is generated. The test signal is output to a device under test. Traffic is received from the device under test. A determination is made as to whether a link failure condition exists at a port on an Ethernet switch.

Abstract: A system and method for enabling portable diagnostics in a configurable device. Physical layer device technology can be implemented into a configurable device (e.g., handheld device) to perform diagnostics. The configurable device can be enabled for diagnostics through an authentication module that performs an authentication and/or licensing function. Diagnostic information (e.g., channel characteristics, data analysis, traffic analysis, packet analysis, bit analysis, etc.) can be displayed on a display of the configurable device to assist field personnel.

Abstract: In one embodiment, the semiconductor device includes at least one circuit element configured to generate output data. At least one control circuit is configured to adaptively control a power of the output data based on feedback from a receiving semiconductor device, which receives the output data.

Abstract: An RFID reader control system and method is provided. A protocol for controlling an RFID reader and an RFID reader control unit of a mobile phone is defined. Messages, information, commands, responses, and notification are constructed and transmitted between the RFID reader and the RFID reader control unit.

Abstract: A transmission method includes generating a control information signal relating to control information of a data signal. A transmission frame is formed by repeating and discretely arranging the same control information signal. The data signal and the control information signal are transmitted using the transmission frame.

Abstract: Shadow selection logic is used to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. In addition, shadow compare logic is used to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare Shadow counters are used to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.

Abstract: Shadow selection logic is used to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. In addition shadow compare logic is used to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: Testing an integrated circuit (IC) having numerous terminals coupled to numerous digitally controlled impedance (DCI) modules, where the numerous DCI modules control configurable impedances of the numerous terminals. The IC further includes a control circuit having outputs coupled to enable inputs of the numerous DCI modules, where operating the IC in a test mode configures the control circuit to selectively couple a control signal to the enable terminals of the numerous DCI modules. One DCI module of the numerous DCI modules can be enabled at a time facilitating testing of the configurable impedances of the I/O terminals.

Abstract: A tester that generates various data patterns to assure that link receivers and transmitters are functioning properly (i.e., are functioning according to a relevant network specification) across the entire storage area network. In various embodiments, this tester may be used in Fibre Channel type SANs or in fiber connectivity (FICON) type SANs.

Abstract: A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.

Abstract: A method, device, and system are disclosed. In one embodiment method includes determining a left edge and right edge of a valid data eye for a memory. The method continues by periodically checking the left and right edges for movement during operation of the memory. If movement is detected, the method retrains the valid data eye with an updated left edge and right edge.

Abstract: A circuit includes a receiver channel and a built-in self-test circuit. The receiver channel has a serializer and a deserializer. The built-in self-test circuit generates test signals that are transmitted in parallel to the serializer during a test of the receiver channel. The serializer converts the test signals into serial test signals. The deserializer converts the serial test signals into parallel test signals that are transmitted to the built-in self-test circuit.

Abstract: A communication terminal device and a reception environment reporting method produce a more excellent throughput, by making a report of a reception environment with higher accuracy. An SIR measuring section measures an SIR from a reception signal that has been received from a base transceiver station. A CQI converter converts the SIR that has been measured by the SIR measuring section into a CQI value. A BLER calculating section calculates a block error rate of the reception signal. A CQI correcting section corrects the CQI value that has been calculated by the CQI converter, in accordance with the block error rate. A CQI transmitter transmits the CQI value that has been corrected by the CQI correcting section, to the base transceiver station.

Abstract: A communication device configured for transmission of Acknowledgement and Negative Acknowledgement (ACK/NACK) is described. The communication device includes a processor and instructions stored in memory. The communication device determines one or more thresholds based on a size of one or more code words and generates a compressed ACK/NACK sequence. The compressed ACK/NACK sequence identifies one or more correctly received code words and one or more incorrectly received code words if the number of incorrectly received code words is less than the threshold. If the number of incorrectly received code words is greater than the threshold, the compressed ACK/NACK sequence indicates that all of the one or more code words were incorrectly received.

Abstract: A system and method for loopback self testing. A system includes a host device and an endpoint device. The host device transmits unencoded test symbols. The endpoint device loops back the unencoded test symbols to the host device. The host device drives at least some bits of each unencoded test symbol onto host device data signals and drives at least some bits of each unencoded test symbol onto host device control signals.

Abstract: The present invention relates to the domain of reception and transmission of data streams, for example audio and video. More specifically, the invention relates to the optional use of an error correction stream associated with a data stream.

Abstract: A system for processing errors in a processor comprising, an error counter, a pass counter, and a processing portion operative to determine whether a first error is active, increment an error counter responsive to determining that the first error is active, increment the pass counter responsive to determining that all errors have been checked, and clear the error counter responsive to determining that the pass counter is greater than or equal to a pass count threshold value.

Abstract: Disclosed herein are systems, methods, and computer readable-media for detecting and identifying network faults. The method includes recording cyclic redundancy check (CRC) errors gathered by a data stream analyzer, if the number of CRC errors exceeds a threshold, sending a notification to an automated fault manager which (1) analyzes the number of CRC errors, (2) determines a cause of the CRC errors, and (3) takes appropriate corrective action based on the analysis. The method can further include storing CRC error measurements in a log organized by date and time, analyzing stored CRC error measurements to anticipate future CRC errors, and taking preventive action in advance of anticipated future CRC errors. The automated fault manager can be a rule-based fault/performance management system. The notification can be a Simple Network Management Protocol (SNMP) trap. The data stream analyzer can be an MPEG transport stream analyzer.

Abstract: A test circuit can use a simple test pattern data without customization for each substrate and considerably reduce a test preparation process. A connection test circuit is generated by receiving the input of the data of the connection relation indicating the devices mutually line-connected among a plurality of devices, the number of connection lines corresponding to the respective connection relations, and the device outputting a test result, sequentially searching for a connection destination device from the output terminal of an output device, and embedding a test circuit module in a test route.

Abstract: A method of testing a proximity communication system for voltage margin by impressing a voltage upon the data link between the transmitter on one chip and the receiver on the other chip coupled to the transmitter through a capacitively coupling circuit formed by juxtaposed capacitor pads on the respective two chips. The impressed voltage is varied and the output of the receiver is monitored to determine an operational voltage margin. The floating inputs on the receiver may be continuously biased by connecting them to variable biasing supply voltages through high impedances. When the floating inputs are periodically refreshed to a refresh voltage during a quiescent data period, the refresh voltage is varied between successive refresh cycles. The variable test voltage may be applied to transmitter output when it is in a high-impedance state, and the output of the receiver is measured.

Abstract: The degree of degradation imposed on signals transmitted over a communications link from a transmitter to a receiver is tested. A predetermined test signal is transmitted using spare capacity detected by a voice activity detector when no speech is to be transmitted over the communications link. The test signal received by the receiver is compared with the reference signal, and a measure of the degradation of signals caused by the communications link is generated therefrom.

Abstract: A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features.

Abstract: The present application describes a method and system for testing the compliance of a PCIE expansion system to verify that data signals transmitted through multiple data lanes in the expansion system comply with the PCIE requirements. The method for testing a PCIE expansion system comprises delivering the data signals from the data lanes to a compliance board that is configured to loop back at least a first portion of the data signals and transmit a complementary second portion of the data signals to a testing device, and testing a compliance of the second portion of the data signals with the PCIE requirements. The first portion of the data signals is then tested through a second compliance board that is configured to loop back the second portion of the data signals and transmit the first portion of the data signals to the testing device.

Abstract: An approach is provided for bit error rate characterization. A test signal representing one or more Ethernet frames exhibiting a particular bit error rate is generated. The test signal is output to a device under test. Traffic is received from the device under test. A determination is made as to whether a link failure condition exists at a port on an Ethernet switch.

Abstract: In a media gateway, a single RTM is placed in bi-directional communication with a active TPM and also in bi-directional communication with a backup TPM. This is accomplished in part by implementation of a signaling and control bus interface between the LIU/Framer hardware of the RTM and the control processing unit (CPU) of the TPM. This interface provides for arbitration between multiple control sources, and for snooping of the input connection state and signaling information between the LIU/Framer and any other control entity. The interface also prevents contention by multiple control sources driving signal information to the LIU/Framer device.

Abstract: Systems and methods for testing an implementation of a routing protocol in a device are disclosed. Generally, a sequence of protocol messages is provided and a test is performed to test how a device reacts to a specific playback rate for the sequence of protocol messages, wherein the specific playback rate causes a protocol state transition in the device which differs from an expected protocol state transition absent a specific playback delay.

Abstract: Included are embodiments for back channel communication. At least one embodiment of a method includes receiving data at customer premises equipment and determining at least one error in the received data. Some embodiments include formatting the determined error for communication to a central office and sending the formatted error to the central office via a back channel.

Abstract: A method and system for performing diagnostic tests on a real-time system controlled by a state machine. A sequence of states recorded as the state machine operates is used to determine error conditions. The sequence of states is compared to expected sequences of states to determine what, if any, errors have occurred. If the real-time system, such as a transceiver in a communication system, has adaptive components, the status of the adaptive components is used to estimate the condition of any external systems coupled to the real-time system.

Abstract: A system includes a plurality of devices that are connected in series and a controller that communicates with the devices. Each of the devices has a plurality of input ports and corresponding output ports. The outputs of one device and the inputs of a next device are interconnected. The controller is coupled to the first device and the last device of the series-connection. The controller applies a test pattern to the plurality of input ports at the first device connected in series, by the controller. Each data channel defines a data path between corresponding pairs of input and output ports of the first and last devices. A data channel is enabled if the test pattern is detected at its corresponding output port.

Abstract: In a transmission error logging device, method and computer-readable medium for logging transmission errors that occur on a high speed transmission route of a medical technology diagnostic apparatus, the in-feed port for a signal is provided on the high speed transmission route and an error signal is generated upon detection of an error. The transmission volume is detected by a transmission volume counter and the number of errors is detected by a transmission error counter. The transmission volume counter makes a transmission volume count, representing the transmission volume, available as an output from the transmission volume counter, and the transmission error counter makes a count of the number of errors detected by the error detection device available at an output of the transmission error counter.

Abstract: In one embodiment, the present invention includes a system having an electromagnetic coupler probe to electromagnetically sample signals from a device under test or a link under test and a receiver, e.g., configured as an integrated circuit that is to receive the sampled electromagnetic signals from the probe and output digital signals corresponding thereto. Other embodiments are described and claimed.

Abstract: Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of read data received through the read data lanes. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames.

Abstract: A method, apparatus and program product improve computer reliability by, in part, identifying a plurality of error occurrences from Error Correction Codes. It may then be determined if the plurality of error occurrences are associated with a single bit of a bus. The determined, single bit may correspond to a faulty component of the bus. This level of identification efficiently addresses problems. For instance, a corrective algorithm may be applied if the plurality of error occurrences are associated with the single bit. Alternatively, the bus may be disabled if the plurality of error occurrences are not associated with the single bit of the bus. In this manner, implementations may detect, identify and act in response to multiple failure modes.

Abstract: Systems and methods are disclosed herein to provide improved communication system test techniques. For example, in accordance with an embodiment of the present invention, a wireless device test system is disclosed having a channel emulator for multipath and/or MIMO applications to allow the testing of wireless devices (e.g., WLAN devices) in a cabled environment.

Abstract: The invention relates to a protective system for an installation, in particular for a gas-turbine installation, in which all the fail-safe protective circuits with reaction time requirements of greater than 50 milliseconds are routed via a more fail-safe programmable logic automation system. For all the other protective circuits with reaction time requirements of less than 50 milliseconds, fail-safe control relays are connected in a configuration which is tolerant to single faults, in which the automation system can check the operation of the control relay circuit cyclically during operation of the installation.

Abstract: A method for implementing program execution integrity (PEI) for a communication-based sensor includes receiving an output communication message from the sensor, the output communication message including sensor output data internally processed within the sensor. The output communication message further includes raw data used by the sensor in internally processing the sensor output data. The raw data is independently processed, and the results thereof are compared with the internally processed sensor output data so as to verify the processing integrity of the sensor to a desired tolerance.

Abstract: An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin. After being enabled, the Trace domain acquires data from a functioning circuit within the IC in response to a first clock and outputs the acquired data from the IC in response to a second clock. An addressable two pin interface loads and updates instructions and data to a TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller.

Abstract: A system for measuring performance of a serial communications link includes a system under test including at least one transmitter and at least one receiver coupled together via a serial data communications link, wherein at least one of the transmitter and the receiver has at least one tunable parameter, at least one controller coupled to at least one of a transmitter and a receiver via a joint test action group JTAG interface, and logic configured to perform a bit error ratio test (BERT) at a plurality of receiver phase locations over a defined time period and concluding the BERT for a particular phase location if a BERT error count is greater than 0 at the particular phase location.

Abstract: A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

Abstract: A system and method for adaptive error correction that optimizes bandwidth by taking into account expected, or predicted, interferences. The bandwidth used for error correction is applied judiciously based on the value of the content and the need to receive the content the first time it is broadcast. The present invention further applies local optimizations in the case of spot-beam satellite broadcasts. As each spot corresponds to a particular geographic region, different input parameters may be used, thereby maximizing efficiency.

Abstract: A system for testing hardware components includes a test pattern injector and a test pattern detector coupled to verification paths that pass through hardware components. The test pattern injector generates unique test patterns. A test pattern tests hardware features of the hardware components of a corresponding verification path. The test pattern injector injects the test patterns into the corresponding verification paths. The test pattern detector establishes expected test patterns. An expected test pattern matches an injected test pattern of a corresponding verification path. The test pattern detector determines whether received test patterns match the expected test patterns.

Abstract: Method and related system for testing a chip with high speed I/O functions are provided. The testing method of a chip includes the steps of: receiving a testing signal from a low speed bus; then transmitting the testing signal according to a transmission control signal; then receiving the testing signal according to a receiving control signal; and comparing the transmitted testing signal and the received testing signal to identify the I/O functions of the chip.

Abstract: An electronic apparatus having a RF tag communication function is provided which includes a RF tag reader/writer and a main controller for controlling the RF tag reader/writer. The RF tag reader/writer includes a radio communication section for executing radio communication with a RF tag and a controller for controlling the radio communication section. The main controller is capable of communication with the controller. A command which requests a reply is transmitted from the main controller to the RF tag reader/writer, and the controller is diagnosed based on the reply from the RF tag reader/writer.