Abstract: Systems and methodologies are described that facilitate verifying correctness of FLO test application protocol (FTAP) data packets. According to various aspects, systems and/or methods are described that enable generating an expected test signature at an FTA client (e.g., mobile device), receiving FTAP flow data packets and/or effectuating comparisons between received and expected data. Such systems and/or methods may further resynchronize client-side generation to an FTA server.

Abstract: A method of transmitting data through a link comprises encoding digital data into encoded digital data in a transition minimized differential signaling encoder, serializing the encoded digital data into encoded and serial digital data in a serializer, generating test data in a pseudo-random binary sequence generator circuit, transmitting the encoded and serial digital data through a multiplexer to a transmission medium in a normal mode of operation, and transmitting the test data through the multiplexer to the transmission medium in a test mode of operation. The encoder, the serializer, the sequence generator circuit, and the multiplexer are fabricated in a single integrated chip. The test data includes data to generate colors in a visual image, and the encoded and serial digital data is received, deserialized, decoded, and displayed in a display unit.

Abstract: The ‘IP Diagnostics’ software is a new and innovative method of aiding the deployment and troubleshooting of IP enabled POS terminals. Its purpose is to identify where a failure in the IP connection is occurring. The IP Diagnostics application does this by testing major failure points within the IP chain from the POS terminal to the host.

Abstract: The current invention provides a mechanism for detecting and recovering from glitches on data strobes. In one embodiment, data is captured from an interlace by a receiver using at least one data strobe that is provided by the transmitter along with the data. A write address counter that is clocked by the data strobe is used to count the active edges of the data strobe. A read address counter that is periodically synchronized with the write address counter, but that is clocked by an internal clock of the receiver, is used to count units of data being received from the interface. Periodically, the contents of the read and write counters are compared. If the contents are not the same, a glitch has occurred on the data strobe. The glitch is recoverable if it occurs on, or after, a last strobe edge of a data transfer.

Abstract: A detecting method for the consistency of a link scrambling configuration, comprises: setting the first threshold of the data packet error rate received by the receiving end; when the receiving end receiving date from the link, counting the received data packet error rate; judging whether the error rate is above the set first threshold; if yes, determining that the link scrambling configurations between transmitting end and receiving end are inconsistent; if not, determining that the link scrambling configurations between transmitting end and receiving end are consistent. The invention provides that the ports could detect the consistency of the link scrambling configuration automatically when configuring the link scrambling code, thereby enables the receive device to adjust the configuration of scrambling code to achieve the consistency of scrambling code between both ends of the link, and improves the maintenance of devices.

Abstract: An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin. After being enabled, the Trace domain acquires data from a functioning circuit within the IC in response to a first clock and outputs the acquired data from the IC in response to a second clock. An addressable two pin interface loads and updates instructions and data to a TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller.

Abstract: Using the attribute “priority” to achieve a stronger Forward Error Correction (FEC) for Radio Link Control (RLC) Control Protocol Data Units (PDUs) transmitted via the High Speed Downlinik Shared Channel (HS-DSCH) also entails prioritized handling so that an RLC Control PDU is likely to overhaul an RLC Data PDU. As a consequence the RLC protocol operation can severely be disturbed, since it relies on in-sequence delivery of control and data PDUs. According to an exemplary embodiment of the present invention, two types of containers are provided in which data packets may be transmitted, wherein the first type of container is provided with a stronger error coding than the second type of container and wherein data packets which comprise control instructions are only transmitted in the first container type with the stronger error correction. Due to this, an improved forward error correction for control PDUs of the AM RLC protocol of Universal Mobile Telecommunications System (UMTS) may be provided.

Abstract: A testing system for a device under test (DUT) includes a test parameter-generating device and a platform module. The test parameter-generating device stores test information, and is operable so as to execute a test algorithm, so as to generate a transmission signal upon execution of the test algorithm, and so as to generate a test environment with reference to the transmission signal. The platform module is operable so as to conduct testing of the DUT using the test information stored in the test parameter-generating device under the test environment generated by the test parameter-generating device.

Abstract: A method is provided to align clock and data signals over a source-synchronous link. The method includes sending header data and a default clock signal over the link. The header indicates a start of a training packet and the default clock signal ensures that the header is received without error. The method further includes providing a long clock pulse, phase shifting the clock signal during the long clock pulse, and thereafter sending training data and the clock signal over the link. The above steps are repeated until the training data are received with error. At that point, the phase shift of the clock signal is saved as a boundary of an optimal alignment. The above steps are then repeated with the clock signal shifted in a different direction. Once another boundary is located, the boundary midpoint is saved as the phase shift that provides the optimal alignment.

Abstract: A physical layer device includes a coding circuit to transmit first data, and to receive second data, at one of a plurality of data rates. A communication circuit transmits first signals representing the first data, and receives second signals representing the second data, over one or more of a plurality of channels. A test circuit determines a condition of the channels. A control circuit selects the one of the plurality of the data rates, and selects the one or more of the plurality of the channels, based on the condition of the channels determined by the test circuit.

Abstract: Systems and methods that identify the Upper Layer Protocol (ULP) message boundaries are provided. In one example, a method that identifies ULP message boundaries is provided. The method may include one or more of the following steps: attaching a framing header of a frame to a data payload to form a packet, the framing header being placed immediately after the byte stream transport protocol header, the framing header comprising a length field comprising a length of a framing protocol data unit (PDU); and inserting a marker in the packet, the marker pointing backwards to the framing header and being inserted at a preset interval.

Abstract: A multi-chip module (MCM) assembly has two modules interconnected by respective interposers and a printed circuit board, and diagnostic logic within the modules uses the principal of signal reflection to located any open fault in the circuit path across the interposers. A first test signal is sent from module to the other and a determination is made as to whether any reflected signal represents an open fault of the circuit path at either of the interposers. If a reflected signal is received during a predetermined time, the diagnostic logic concludes that a single open fault exists only at the far interposer. If no reflected signal is received then the diagnostic logic concludes that there is at least one open fault at the near interposer, and the second module runs a similar test to check to see if both interposers have failures.

Abstract: In a preferred embodiment, the invention provides a circuit for reducing bit error rates. A data recovery circuit recovers data from a first HSS link to differential bit pair inputs. Data from the differential bit pair outputs of the data recovery circuit drive differential bit pair inputs to a plurality of FIFOs. The data is then driven from a parallel output of the plurality of FIFOs to the parallel input of a synchronizer. The data is then driven from the parallel output of the synchronizer to the parallel input of a serializer. The serializer, through different bit pair outputs, drives a second serial HSS link.

Abstract: The present invention provides systems, devices and methods for generating user-defined test patterns within serial controller to facilitate signal testing and verification. These user-defined test patterns may be generated to more accurately reflect the actual traffic of a device-under-test or system, as well as allow a test engineer to more accurately test the boundaries of the device or system. In various embodiments of the invention, a programmable patterns generator is provided for generating user-defined test patterns that may be used during a testing procedure. This programmable pattern generator allows a user to define a particular test pattern by providing bit-by-bit test values, by defining a combination of canned sequences, or by supplementing one or more canned sequences with additional test bits.

Abstract: Systems and methods of controlling control and/or monitoring devices are provided. A controller can include a software defined radio in order to communicate with control and/or monitoring devices that employ different communication protocols. The controller can be in the form of a memory stick, memory card or dongle.

Abstract: A method and system for performing diagnostic tests on a real-time system controlled by a state machine. A sequence of states recorded as the state machine operates is used to determine error conditions. The sequence of states is compared to expected sequences of states to determine what, if any, errors have occurred. If the real-time system, such as a transceiver in a communication system, has adaptive components, the status of the adaptive components is used to estimate the condition of any external systems coupled to the real-time system.

Abstract: A system and method for self-test of an integrated circuit are disclosed. As one example, an integrated circuit is disclosed. The integrated circuit includes a digital signal processing chain, a random sequence generator coupled to an input of the digital signal processing chain, and a checksum calculator coupled to an output of the digital signal processing chain.

Abstract: An access management system includes an access administration apparatus which permits access to a database when the access request satisfies an access permission condition, and a policy determination apparatus which determines whether the access permission condition is satisfied by the access request; in which the access administration apparatus stores decision information containing a decision as to whether the access permission condition is satisfied, determines that the access request satisfies the access permission condition if the decision information has a predetermined inclusion relation with the access request, receives a decision as to whether the access permission condition is satisfied by the access request from the policy determination apparatus if it is determined that the decision information does not have the inclusion relation with the access request, and permits access to the database if it is determined that the access request satisfies the access permission condition.

Abstract: An apparatus, system, and method are disclosed for assessing error over a communication link. The apparatus for assessing error is provided with a logic unit containing a plurality of modules configured to execute the necessary steps of creating one or more test packets, determining an amount of test packets to send over a communication link to a receiving node, sending a plurality of test packets over the communication link to a receiving node, interspersing test packets throughout a plurality of data packets such that the receiving node is able to continually process the data packets, and checking test packets received by the receiving node for errors.

Abstract: A voltage identifier (VID) sorting system is provided that optimizes processor power and operating voltage guardband at a constant processor frequency. The VID sorting system determines a voltage versus current curve for the processor. The VID sorting system then uses the voltage versus current characteristics to calculate the power for each VID to determine an acceptable range of VIDs within the maximum power criteria. The VID sorting system then tests VIDs in the range and selects a VID from the range to optimize for minimum power and/or maximum voltage guardband at a constant processor frequency.

Abstract: Methods, circuits, architectures, software and systems for error detection in transmitted data. The method generally includes receiving data and non-data, the data including fixed length data portions, removing non-data; and if the data includes a remainder, adding a zero-pad vector to generate a zero-padded data portion, then checking the data and zero-padded data portions for a transmission error. The circuit generally includes a circuit to detect non-data; a circuit configured to replace non-data with a zero-pad vector; and a circuit to detect a transmission error in data and zero-padded data portions of information, and combine the zero-pad vector with a remaining data portion to form the zero-padded data portion. The present invention enables a single error detection circuit to detect errors, thereby reducing chip area, increasing efficiency, and reducing power consumption.

Abstract: Embodiments of the present invention include a system and method of dynamic space-frequency-division multiple-access for the uplink from terminals to a base-station. The system includes a base-station and multiple terminals. According to different spatial mapping modes, the base-station performs an optimization computation using an optimization function in order to obtain control information for controlling terminals; after receiving the control information, the user terminal controls the transmitting mode using this control information. The method includes the following operations: at the base-station, performing an optimization computation using an optimization function according to different spatial mapping modes respectively, in order to obtain control information for controlling terminals; at the user terminal, controlling a transmitting mode using the control information after receiving the above control information.

Abstract: A method, device, and system are disclosed. In one embodiment, the method comprises discovering a failure on a PCI Express interconnect, determining whether a failure override bit has been set to override the standard PCI Express Polling. Compliance state for the failure on the PCI Express interconnect, and if the failure override bit has been set, entering PCI Express Polling. Configuration state if any one lane of the interconnect successfully completes the transmitting and receiving training sequence requirements in PCI Express Polling.Active state.

Abstract: The present invention assesses memory (DIMM) strength by calculating frequency content of a radiated field which is collected by an apparatus, such as a dipole antenna. Radiated field is created by accelerated charge, which is a function of the slew rate or DIMM strength. Radiated power is directly proportional to the frequency at which bits are driven. By separating the radiated field from the near field or stored field, the DIMM strength content is isolated from other functional DIMM issues, such as tRCD latency, refresh cycles, addressing mode, etc. By examining the radiated power, the disadvantages of the prior art, such as by probing the DIMM's contacts, are avoided.

Abstract: A method and apparatus that is configured to issue an echo extended link service with a payload of data patterns that are known in the art of fiber channel to produce jitter. The inventive apparatus is configured to use an echo extended link service to send data with a specified data pattern. Failing data patterns are compared against data patterns that are known in the art of fiber channel to create jitter and the results may be presented to the user.

Abstract: A method and system for testing a modular data-processing component. Register information associated with a modular data-processing component to be tested at a test location can be identified and stored. The modular data-processing component can then be tested and removed from said test location. Thereafter, the register information can be retrieved and provided for use with testing of a new data-processing component at said test location without losing said register information during testing of multiple modular data-processing components. The register information can be, for example, PCI configuration data and the modular data-processing component can be an HAB.

Abstract: Disclosed is serial communication control system including: a first microcomputer; and a second microcomputer connected to the first microcomputer through a serial line, wherein the second microcomputer includes an R/B signal sending section to send one of a READY signal and a BUSY signal, the first microcomputer includes an R/B signal receiving section to receive the signal, and a first sending section to send first serial data to the second microcomputer when the R/B signal receiving section receives the READY signal, the second microcomputer includes a first receiving section to receive the first serial data, and a second sending section to send second serial data after the receiving operation of the first serial data by the first receiving section is completed and the R/B signal sending section thereafter sends the BUSY signal, and the first microcomputer includes a second receiving section to receive the second serial data.

Abstract: A method and apparatus for testing a data transfer system. The method comprises the steps of storing a first table, the first table noting at least a time of issuance of at least one command and a time of completion of the command and comparing the time of issuance of the command and the time of completion of the command. A timeout condition is registered if the processor determines that a time longer than a predetermined time elapsed between the time of issuance of the command and the time of completion of the command.

Abstract: A method of controlling a transceiver module which includes a physical-layer integrated circuit having a physical-layer register unit, and a control integrated circuit having a control-side register unit. In the method, the physical-layer register unit is emulated by the control-side register unit and the physical-layer integrated circuit is prohibited from generating a first error signal giving notice of detection of a specific error directly to a higher-layer device. A second error signal is output from the physical-layer integrated circuit to the control integrated circuit, giving notice of a high-speed error associated with communication processing and that is detected by the physical-layer integrated circuit. The high-speed error is specified in response to the outputting of the second error signal. A bit is set in the control-side register unit in response to the specifying of a high speed error and the control integrated circuit delivers to the higher-layer device the second error signal.

Abstract: A network relay apparatus relays data accompanied by additional information among plural networks through input ports and output ports. In the apparatus, a deciding unit decides, from the output ports, an objective output port to which the data inputted via any one of the input ports is to be inputted, on the basis of the additional information of the data inputted. An output unit outputs the inputted data through the decided objective output port. A producing unit produces diagnostic data to which the additional information including information indicating the decided objective output port is added, and a providing unit provides the deciding unit with the produced diagnostic data. Further, a fault diagnostic unit is provided to determine whether a fault has occurred in the network relay apparatus on the basis of information concerning the diagnostic data and the decided objective output port.

Abstract: A system and method are disclosed for testing operation of a memory card within an electronic host device. The system includes a flat flexible cable, or strip, for electrically coupling between the memory card slot in a host device and a test assembly. The test assembly may have a card slot for accepting an external memory card, and a debug header for receiving a cable connected to a debug apparatus such as a logic analyzer and/or an oscilloscope.

Abstract: An apparatus and method for synchronous communications using a serial data stream employs a housing with a controller and a back plane. The housing accepts one or more modules for interconnection with the back plane. The back plane distributes power to the modules and provides a communication link from the controller to each module. Each communication link includes a data out line, a data in line and a clock line, where each clock line is derived from one clock source.

Abstract: A system and method to operate an electronic device, such as a memory chip, in a test mode using the device's built-in ODT (on die termination) circuit is disclosed. One or more test mode related signals, which include on-die signals and other relevant information, may be transferred from the integrated circuit of the electronic device to an external processor using the device's ODT circuit instead of the output data signal driver circuit. Therefore, no capacitive loading of output drivers occurs during test mode operations. Thus the speed of the output data path (i.e., the circuit path propagating non-test mode related signals from the electronic device to other external units in the system) is not affected by test mode operations, allowing a system designer to increase the speed of the data output path as much as desired. Further, deterioration in the quality of signals output from the output drivers is also avoided.

Abstract: Receiver-side apparatus for a transmission link, the link using different transport formats for blocks of data, and using convolutional coding with additional error detection code information, for transmitting the blocks to the receiver side, the apparatus having a decoder for performing a trellis decode and tracebacks of one of the received coded blocks, to produce decoded data candidates, an error detection element for carrying out one or more speculative error detections on the candidates, assuming part of each candidate is the additional error detection code, and part is the block of data, and a format detector for determining a transport format based on a result of the speculative error detections, the apparatus being arranged to determine a probability of a candidate being valid, and prioritize carrying out the tracebacks or the speculative error detections according to the probabilities.

Abstract: A pleisiochronous repeater system and components thereof are disclosed. In one particular exemplary embodiment, a pleisiochronous repeater system component may be realized as a receiver circuit comprising a clock multiplier that multiplies a reference clock signal by an integer multiple to generate a data clock signal. The receiver circuit may also comprise a divider circuit that generates a timing reference signal having a frequency that is not an integer divisor of a frequency of the reference clock signal.

Abstract: A self-synchronizing data bus analyzer is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.

Abstract: Disclosed is a system and method for testing a dual mode interface. The dual mode interface includes a first strobe circuit and a second strobe circuit configured to be inoperable during a first operational mode of the interface and operable during a second operational mode of the interface. The dual mode interface also includes a first data circuit and a second data circuit configured to be operable during the first operational mode and the second operational mode. The dual mode interface also includes a signal line connecting an output of the second strobe circuit with an input of the first strobe circuit and a switch element configured to activate said signal line in response to receipt of a test signal.

Abstract: A channel characteristic of a transmission channel between a remote terminal and a central office is estimated by collecting information in the remote terminal, transferring this information from the remote terminal to the central office and matching the received information at the central office with a channel and remote terminal simulation model. The values of parameters of the latter simulation model, which define the channel characteristic to be estimated, are determined as a result of the matching process. The information collected by the remote terminal typically is information that is automatically collected by the remote terminal for operational purposes, such as equalizer setting and bit allocation.

Abstract: A physical coding sublayer (PCS) device includes a first data scrambler, a second data scrambler, and a selector. The first data scrambler scrambles first data and implements a first scrambling cycle. The second data scrambler scrambles second data and implements a second scrambling cycle. The second data is different than the first data. The second scrambling cycle is shorter than the first scrambling cycle. The selector selects the first data scrambler to scramble the first data during normal operations. The selector selects the second data scrambler to scramble the second data during testing. The first data scrambler does not scramble the second data. The second data scrambler does not scramble the first data.

Abstract: A test system is disclosed wherein a device under test (DUT) includes a trace logic analyzer (TLA) that receives and stores test data. The test system includes both a master tester and a slave tester. The slave tester operates at a high speed data rate substantially faster than that of the master tester. The master tester instructs the TLA to monitor data that the DUT receives from the slave tester to detect a predetermined data pattern within the data. The slave tester transmits data including the predetermined data pattern to the DUT. The DUT receives the data. When the TLA in the DUT detects the predetermined data pattern in the received data, the TLA stores that data pattern as a stored data pattern. The master tester retrieves the stored data pattern and compares the stored data pattern with the original predetermined data pattern. If the master tester determines that the stored data pattern is the same as the original predetermined data pattern, then the master tester generates a pass result.

Abstract: A method according to one embodiment may include communicating, by a far end device with a near end device, using a Serial ATA (SATA) communications protocol; receiving, by the far end device, a SATA signal sequence having two bits, the state of which define at least one loopback mode; defining, by the far end device, a reserved and/or error state if both of the bits are set; and processing, by the far end device, the two bits together to determine if the two bits are in a state that defines at least one loopback mode or if the two bits are set. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: An interface test can be performed by, for example, only a self apparatus when interface operation specifications are different between the self apparatus and an original connection partner apparatus. An LSI has a plurality of interfaces (IFs) for transmission/reception of data with an external device, and the LSI includes an emulation control unit for allowing one of the two of the plurality of IFs to perform an operation of emulating an IF of a connection partner device having operation specifications different from those of the LSI, when two IFs are connected to each other via a transmission line.

Abstract: In a high-speed serial link, an eye finder diagnostic circuit has improved performance by being on-chip with the existing capture latch(es) of a receive equalizer. The eye finder circuit employs an additional capture latch with its input tied to the same input node as the existing capture latch(es) of a receive equalizer. The additional capture latch has a clock input and reference voltage input. The clock input is adjusted through a phase interpolator (or variable delay line) while the reference voltage input is adjusted by a voltage generator. A digital post processing circuit then compares the output of the additional capture latch with the output of the other existing capture latch(es), in order to determine the receive eye opening. The horizontal eye opening is measured by changing the phase of the additional capture latch through the phase interpolator, while the vertical eye opening is measured by changing the reference voltage of the voltage generator of the additional capture latch.

Abstract: A port selector, a device testing system and a method using the same. The port selector includes: a plurality of terminal ports to which a device is respectively coupled; an integration port which is connected to the plurality of terminal ports through a signal transmitting line; a plurality of terminal switches which are disposed to correspond to each terminal port, and open and close the signal transmitting line; and a control unit which independently controls each terminal switch. Thus, the present general inventive concept provides a port selector, a device testing system and a method using the same including a plurality of terminal ports to which devices are respectively coupled, and independently controlling each terminal port, thereby selecting a port.

Abstract: In a communication system transmitter, a baseband processor is configured for coupling via an upconverter to an input of a power amplifier of the transmitter. The baseband processor comprises a crest factor reduction element implementing an adaptive peak windowing algorithm for application to an input signal, the adaptive peak windowing algorithm comprising a function that is adaptively adjustable for reducing interference among different peaks of the input signal.

Abstract: One embodiment of the invention provides apparatus and a method for testing a transmission path across one or more printed circuit boards. According to the method, a test signal is presented at a first location on the transmission path. The test signal is generally low frequency compared to normal data communications on the transmission path. A pickup line is capacitively coupled at a second location to the transmission path. The pickup line is monitored with a detector to see whether or not the test signal is present. If the test signal is not present, it is determined that there is a fault on the transmission path between the first location and the second location.

Abstract: A method and apparatus for determining the characteristics of a communications channel within a high speed memory system includes generating a first signal having a known and repeating pattern and generating a second signal having a pseudo-random pattern. The first and second signals are combined to produce a combined signal. The combined signal is transmitted over a communications channel of a memory system and received by the memory devices of the memory system. Each memory device removes the second signal from the received combined signal to produce a received first signal. Parameters associated with transmitting and receiving may be adjusted by examining the pattern of the received first signal to determine if it has the known pattern of the first signal. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: Techniques used in an automatic failover configuration having a primary database system, a standby database system, and an observer for preventing divergence among the primary and standby database systems while increasing the availability of the primary database system. In the automatic failover configuration, the primary database system remains available even in the absence of both the standby and the observer as long as the standby and the observer become absent sequentially. The failover configuration further permits automatic failover only when the observer is present and the standby and the primary are synchronized and inhibits state changes during failover. The database systems and the observer have copies of failover configuration state and the techniques include techniques for propagating the most recent version of the state among the databases and the observer and techniques for using carefully-ordered writes to ensure that state changes are propagated in a fashion which prevents divergence.

Abstract: A repeater-installed fault location mechanism conducts parametric measurements on a segment of wireline to which the repeater is connected, and adjusts taps of an echo cancellation operator in the repeater transceiver equipment, in accordance with the response of the wireline to an electrical stimulus imparted to the wireline segment. Information representative of the echo canceler tap coefficients is then transmitted over an overhead to a processor, to determine fault the location of a fault.

Abstract: A system for validating data collected in a first clock domain. A performance counter is disposed in a second clock domain to perform performance computations relative to the data. Validation circuitry is in communication with the data in order to provide to the performance counter a validation signal indicative of the validity of the data.