Read-in With Read-out And Compare Patents (Class 714/719)
  • Patent number: 10719388
    Abstract: A system for maintaining a repository replication system includes an interface and a processor. The interface is to receive a request to modify a repository, wherein the repository comprises repository copies. The processor is to determine whether modifying the repository resulted in an indication of an error, wherein the indication of the error is based at least in part on a plurality of checksums, wherein a checksum of the plurality of checksums is associated with a repository copy of the repository copies; and in the event that modifying the repository resulted in the indication of the error: queue a repair request to repair the error; and execute a repair process to repair the error associated with the repair request, wherein executing the repair process occurs asynchronously to queuing the error request.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: July 21, 2020
    Assignee: GITHUB, INC.
    Inventor: Patrick Reynolds
  • Patent number: 10699791
    Abstract: A non-volatile memory includes a plurality of physical pages each assigned to one of a plurality of page groups. A controller of the non-volatile memory performs a first calibration read of a sample physical page of a page group of the non-volatile memory. The controller determines if an error metric observed for the first calibration read of the sample physical page satisfies a calibration threshold. The controller calibrates read voltage thresholds of the page group utilizing a first calibration technique based on a determination that the error metric satisfies the calibration threshold and calibrates read voltage thresholds of the page group utilizing a different second calibration technique based on a determination that the error metric does not satisfy the calibration threshold.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: June 30, 2020
    Assignee: International Business Machines Corporation
    Inventors: Roman A. Pletka, Nikolaos Papandreou, Sasa Tomic, Nikolas Ioannou, Charalampos Pozidis, Timothy Fisher, Aaron D. Fry
  • Patent number: 10636460
    Abstract: A mode register control circuit may include a masking signal generation circuit and a storage control pulse generation circuit. The masking signal generation circuit may be configured to generate a masking signal from data. The storage control pulse generation circuit may be configured to generate a storage control pulse for controlling a mode register write operation, from a mode register write pulse in response to the masking signal.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: April 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Seung Hun Lee, Won Kyung Chung
  • Patent number: 10622084
    Abstract: Methods for verifying data path integrity are provided. One such method includes reading a partially programmed first set of data from an array of memory cells of the memory device into a page register of the memory device, loading the partially programmed first set of data into a cache register of the memory device, writing a partial set of test data to a portion of the cache register not containing the partially programmed first set of data during a read of a second set of data from the array of memory cells to the page register, reading the partial set of test data from the cache register during the read of the second set of data from the array of memory cells to the page register, and comparing the partial set of test data read from the cache register to the original partial set of test data.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Terry Grunzke
  • Patent number: 10573358
    Abstract: A driver of a multi-level signaling interface is provided. The driver may be configured reduce noise in a multi-level signal (e.g., a pulse amplitude modulation signal) generated by the driver using switching components of different polarities. The driver may include a pull-up circuit and/or a pull-down circuit. The pull-up circuit and the pull-down circuit may include at least one switching component of a first polarity (e.g., nmos transistor) and at least one switching component of a second polarity different from the first polarity (e.g., pmos transistor). Such a configuration of pull-up and pull down circuits may generate a more linear relationship between an output current and an output voltage of an output of the driver, thereby improving one or more characteristics of the multi-level signal.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Justin D. Butterfield
  • Patent number: 10541041
    Abstract: A semiconductor device is comprised of a memory cell array with multiple memory cells arranged in a matrix, multiple bit-line pairs provided for each memory cell column in the memory cell array, multiple input/output circuits provided respectively corresponding to the multiple bit-line pairs, and as interface control circuit that controls the data input/output to the multiple input/output circuits when performing the data write and data read for each memory cell row in a normal mode. The interface control circuit is comprised of a selection circuit. When the data write and data read are performed for each memory cell row in a test mode, the selection circuit selects the data input/output to one of first input/output circuit and a second input/output circuit, respectively corresponding to a first memory cell included in the memory cell row and a second memory cell adjoining the first memory cell, according to a test address.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: January 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shinji Tanaka
  • Patent number: 10510405
    Abstract: A soft information module is coupled between one or more flash memory devices and a decoder. The soft information module receives a putative value of one or more memory cells of the one or more flash memory devices based on a read of the one or more memory cells at an initial read level, and one or more respective indicators of whether the putative value was read at one or more respective different read levels offset from the initial read level, and receives a page indicator for the read. The soft information module determines a cell program region for the read based on the putative value, the one or more respective indicators, and the page indicator, identifies a predetermined confidence value for the region, and provides the confidence value to the decoder for association with the putative value, the confidence value being representative of a likelihood that the one or more memory cells was programmed to the putative value.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: December 17, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Richard David Barndt, Xinde Hu, Anthony Dwayne Weathers
  • Patent number: 10497457
    Abstract: A method of operation in an integrated circuit (IC) memory device. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: December 3, 2019
    Assignee: Rambus Inc.
    Inventors: Ely Tsern, Frederick A Ware, Suresh Rajan, Thomas Vogelsang
  • Patent number: 10473721
    Abstract: Various aspects of the disclosed technology relate to streaming data for testing identical circuit blocks in a circuit. The system for streaming data comprises a first network for transporting equal-sized data packets consecutively and a second network for configuring interface devices of the first network. Each of the data packets comprises bits of test patterns and bits of good-machine test responses. Comparison bits (pass/fail status bits) of an identical circuit block instance may be unloaded directly or may merge with those from other identical circuit block instances to generate accumulated comparison bits which are unloaded. A sticky pass/fail bit may also be generated for each of the identical circuit block instances.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: November 12, 2019
    Assignee: MENTOR GRAPHICS CORPORATION
    Inventors: Jean-Francois Cote, Mark A. Kassab, Janusz Rajski
  • Patent number: 10453480
    Abstract: A method of forming a read head. The method includes forming first and second read sensors. A first read measurement is performed on a storage medium using the first read sensor. A second read measurement is performed on the storage medium using the second read sensor. Based on a comparison of the first and second read measurements to a predetermined quantity, either the first read sensor or the second read sensor is selected to be operational in a data storage device.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: October 22, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Victor Sapozhnikov, Mohammed Shariat Ullah Patwari, Jason B Gadbois, Taras Grigorievich Pokhil
  • Patent number: 10437669
    Abstract: Apparatuses and methods are described for selective determination of data error repair. An example apparatus includes a memory array and a controller coupled to the memory array. The controller is configured to direct performance, responsive to a request, of a read operation at an address in the memory array, direct detection of an error in data corresponding to the read operation address, and direct storage of the read operation address in an address error register. The controller is further configured to direct a response be sent to the enable selective determination of data error repair, where the response does not include the read operation address.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Ryan S. Laity, Christopher S. Johnson
  • Patent number: 10408876
    Abstract: Embodiments include novel approaches for scan-based device testing using a march controller. A march data store can have sets of march element data stored thereon, each defining a respective march element of a march test sequence. A march select register can select each stored set of march element data according to the predefined march test sequence, and a march data loader can iteratively and sequentially output each set of march element data selected by the march select register. A memory built-in self-test controller can generate, in response to receiving each set of march element data output by the march controller, test stimulus data corresponding to the received set of march element data. The test stimulus data can input to a scan chain of the integrated circuit under test, and response data can be captured from the scan chain and assessed to determine whether the integrated circuit passed the test.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: September 10, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Thomas Ziaja, Lancelot Kwong
  • Patent number: 10403337
    Abstract: A driver of a multi-level signaling interface is provided. The driver may be configured reduce noise in a multi-level signal (e.g., a pulse amplitude modulation signal) generated by the driver using switching components of different polarities. The driver may include a pull-up circuit and/or a pull-down circuit. The pull-up circuit and the pull-down circuit may include at least one switching component of a first polarity (e.g., nmos transistor) and at least one switching component of a second polarity different from the first polarity (e.g., pmos transistor). Such a configuration of pull-up and pull down circuits may generate a more linear relationship between an output current and an output voltage of an output of the driver, thereby improving one or more characteristics of the multi-level signal.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Justin D. Butterfield
  • Patent number: 10394647
    Abstract: A memory device, a memory system, and corresponding methods are provided. The memory device includes a non-volatile random access memory. The non-volatile memory includes a suspect bit register configured to store addresses of bits that are determined to have had errors. The non-volatile memory further includes a bad bit register configured to store addresses of bits that both (i) appeared in the suspect bit register due to a first error and (ii) are determined to have had a second error. Hence, the memory device overcomes the aforementioned intrinsic write-error-rate by identifying the bad bits so they can be fused out, thus avoiding errors during use of the non-volatile random access memory.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John K. DeBrosse, Daniel C. Worledge
  • Patent number: 10387259
    Abstract: An apparatus is described. The apparatus includes a memory controller having a programmable component. The programmable component is to implement a data checking function. The programmable component is to receive and process partial results of the data checking function from two or more DIMM cards that are coupled to the memory controller.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Karthik Kumar, Martin Dimitrov, Thomas Willhalm
  • Patent number: 10340025
    Abstract: The present invention provides a data-storage device. The data-storage device includes a flash memory and a controller. The flash memory has a plurality of blocks and each of the blocks has a plurality of pages. The blocks include a plurality of bad blocks that are labeled as damaged. The controller selects one of the bad blocks as a test block, and reads the pages in the test block to determine whether the pages in the test block are damaged. When all the pages in the test block are undamaged, the controller labels the test block as a spare block.
    Type: Grant
    Filed: January 6, 2018
    Date of Patent: July 2, 2019
    Assignee: SILICON MOTION, INC.
    Inventors: Pin-Chang Liu, Tai-Yu Tsou, Yi-Ming Liu
  • Patent number: 10276247
    Abstract: Methods and apparatus are provided for read retry operations that estimate written data based on syndrome weights. One method comprises reading a codeword from a memory multiple times using multiple read reference voltages; obtaining a syndrome weight for each of the readings of the codeword; identifying a given reading of the codeword having a substantially minimum syndrome weight; and estimating a written value of the codeword based on the given reading. Two cell voltage probability distributions of cell voltages are optionally calculated for each possible cell state of the memory, based on the estimated written value and plurality of readings of the codeword. The cell voltage probability distributions are used to (i) dynamically select log likelihood ratio values for a failing page, (ii) determine a read reference voltage that gives a desired log likelihood ratio value, or (iii) dynamically select log likelihood ratio values for the page populations associated with the distributions.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: April 30, 2019
    Assignee: Seagate Technology LLC
    Inventors: AbdelHakim S. Alhussien, Sundararajan Sankaranarayanan, Thuy Van Nguyen, Ludovic Danjean, Erich F. Haratsch
  • Patent number: 10247778
    Abstract: A semiconductor apparatus includes first and second chips sharing first and second data channels. The first chip compresses first test data of the first chip and outputs the compressed first test data through the first data channel in a first test mode, and the second chip compresses second test data of the second chip and outputs the compressed second test data through the second data channel in the first test mode.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: April 2, 2019
    Assignee: SK hynix Inc.
    Inventor: Ki Up Kim
  • Patent number: 10229146
    Abstract: Embodiments of the present invention provide a method, computer program product, and computer system for masking indexes. The method may include masking the index if the index contention exceeds a defined threshold. The method may also include configuring the mask type for the index to insert the index without masking. In response to determining that the mask type for the index is configured to insert the index without masking, the index is masked according to a set of rules.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Shuo Li, Ping Liang, Xin Ying Yang, Jian Wei Zhang
  • Patent number: 10139445
    Abstract: A technical solution for improving test times and costs associated with IC production includes a central test engine (CTE) functional test block integrated onto an IC. The CTE functions as a hardware abstraction layer (HAL), and provides testing capabilities by transferring a large test data file to a device under test and performing a closed-loop monitoring of receipt of the expected test data results. The CTE also reduces the number of external interfaces and interface controllers used during testing. The reduction in external interfaces reduces the size of the IC, which enables smaller and more efficient IC manufacturing, and may be used to improve small form-factor high-volume manufacturing (HVM). This reduction in IO pins also enables significant reduction in IO resources (e.g., IO drivers) within the IC, and reduces or eliminates IO test hardware dependencies.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: November 27, 2018
    Assignee: Intel Corporation
    Inventors: Chin Keat Teoh, Satheesh Chellappan, Lay Cheng Ong, Terrence Huat Hin Tan
  • Patent number: 10134484
    Abstract: A semiconductor system includes a controller and a semiconductor device. The controller outputs a burn-in test signal, a clock signal and command/address signals. The semiconductor device enters a first test mode if the burn-in test signal is inputted. The semiconductor device enters a second test mode according to a level combination of the command/address signals in synchronization with the clock signal after the semiconductor device enters the first test mode. The semiconductor device enters a third test mode according to an other level combination of the command/address signals in synchronization with the clock signal after the semiconductor device enters the second test mode.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: November 20, 2018
    Assignee: SK hynix Inc.
    Inventors: Myung Kyun Kwak, Bok Rim Ko
  • Patent number: 10102084
    Abstract: A system for maintaining a repository replication system includes an interface and a processor. The interface is to receive a request to modify a repository, wherein the repository comprises repository copies. The processor is to determine whether modifying the repository resulted in an indication of an error, wherein the indication of the error is based at least in part on a plurality of checksums, wherein a checksum of the plurality of checksums is associated with a repository copy of the repository copies; and in the event that modifying the repository resulted in the indication of the error: queue a repair request to repair the error; and execute a repair process to repair the error associated with the repair request, wherein executing the repair process occurs asynchronously to queuing the error request.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: October 16, 2018
    Assignee: GitHub, Inc.
    Inventor: Patrick Reynolds
  • Patent number: 10037817
    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows; and a data control circuit configured to, sequentially read a first unit of data from N memory cell rows of the plurality of memory cell rows, generate merged test results by comparing bits read from the first units of the N memory cell rows, and output the merged test results, during the test mode of the semiconductor memory device. Therefore, test time for testing the semiconductor memory device may be greatly reduced because a test device may determine pass/fail of the data of the unit of repair unit on one read operation.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: July 31, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Jun Her, Dong-Wook Kim, Dong-Hak Shin
  • Patent number: 9972404
    Abstract: A semiconductor test device and a semiconductor test method are disclosed. A semiconductor test device may include a DQ signal receiver, a test mode register set signal processor, and a test mode command generator. The DQ signal receiver may receive a first DQ signal through a first DQ pin. The test mode register set signal processor may receive a test mode register set signal in response to the first DQ signal, and may output a test mode register set pulse signal. The test mode command generator may generate a test mode command corresponding to an input address in response to the test mode register set pulse signal.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: May 15, 2018
    Assignee: SK hynix Inc.
    Inventor: Min Sik Han
  • Patent number: 9959184
    Abstract: An input/output (I/O) line test device and a method for controlling the same are disclosed, which may relate to a technology for testing a base die having no cell using various patterns. The I/O line test device may include an interface controller configured to perform signal transmission/reception between a pad and an input/output line (IOL), and a signal transceiver configured to perform signal transmission/reception between the IOL and a through silicon via (TSV). The I/O line test device may include a latch unit configured to latch output data of the signal transceiver, and a test controller configured to output a control signal for controlling whether the signal transceiver performs a reception operation in response to a write enable signal and a test signal.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: May 1, 2018
    Assignee: SK hynix Inc.
    Inventors: Min Su Park, Young Jun Ku
  • Patent number: 9946620
    Abstract: A memory built-in self test (“BIST”) system comprises: a controller; a single port memory engine coupled to one or more single port memories; and a non-single port memory engine coupled to one or more non-single port memories. The controller receives operation codes (“op-codes”) for testing a plurality of memory types. An output of the controller is coupled to inputs of the single port memory engine and the non-single port memory engine. The controller generates test instructions based on the received op-codes. The single port memory engine and the non-single port memory engine interpret the test instructions to test the one or more single port memories and the one or more non-single port memories.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: April 17, 2018
    Assignee: Invecas, Inc.
    Inventors: Kevin W. Gorman, Thomas Chadwick, Nancy Pratt
  • Patent number: 9899103
    Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: February 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Prakash Narayanan, Nikita Naresh, Vaskar Sarkar, Rajat Mehrotra
  • Patent number: 9886738
    Abstract: A data processing apparatus includes a circuit selector and a data processor. The circuit selector makes a selection, in data processing in which multiple unit processes are each selected and repeated, from a generalized circuit that executes the multiple unit processes and one of dedicated circuits that are each dedicated to a corresponding one of the unit processes, the selection being made repeatedly on a basis of a judgment made using continuous repeat counts each of which indicates how many times a corresponding one of the unit processes is continuously repeated. The data processor selectively configures one of the generalized circuit and the dedicated circuit that corresponds to one of results serially obtained from the selection repeatedly made by the circuit selector, the data processor performing the data processing.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: February 6, 2018
    Assignee: FUJI XEROX CO., LTD.
    Inventor: Daisuke Matsumoto
  • Patent number: 9852170
    Abstract: Embodiments of the present invention provide a method, computer program product, and computer system for masking indexes. The method may include masking the index if the index contention exceeds a defined threshold. The method may also include configuring the mask type for the index to insert the index without masking. In response to determining that the mask type for the index is configured to insert the index without masking, the index is masked according to a set of rules.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Shuo Li, Ping Liang, Xin Ying Yang, Jian Wei Zhang
  • Patent number: 9852171
    Abstract: Embodiments of the present invention provide a method, computer program product, and computer system for masking indexes. The method may include masking the index if the index contention exceeds a defined threshold. The method may also include configuring the mask type for the index to insert the index without masking. In response to determining that the mask type for the index is configured to insert the index without masking, the index is masked according to a set of rules.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Shuo Li, Ping Liang, Xin Ying Yang, Jian Wei Zhang
  • Patent number: 9805772
    Abstract: The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to sensing circuitry and is configured to cause storing of an indication of whether a logical operation is to be selectively performed between an operand stored in the sensing circuitry and an operand stored in the sense amplifier.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: October 31, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Harish N. Venkata
  • Patent number: 9778975
    Abstract: A method of isolating hidden data in a solid state memory system is disclosed including obtaining a logical block address (LBA) image from the memory system, obtaining a physical block address (PBA) image, determining whether an error exists in the PBA image and correcting the error, calculating an ETCRC on each sector of the LBA image and building a search tree indexed on the ETCRC value. For each sector in the PBA image, the method also includes computing an error tolerant cyclic redundancy check (ETCRC) value and searching for the ETCRC value in the LBA search tree. If the ETCRC value is found, also included is comparing the cyclic redundancy check (CRC) of the LBA and PBA sectors, and outputting to an output file the PBA sector as hidden data if either the ETCRC value is not found in the LBA search tree or the CRC comparison fails.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: October 3, 2017
    Assignee: S34A, Inc.
    Inventors: Henry B. Wallace, David Sun
  • Patent number: 9740631
    Abstract: Provided are methods and systems for managing memory using a hardware-based page filter designed to distinguish between active and inactive pages (“hot” and “cold” pages, respectively) so that inactive pages can be compressed prior to the occurrence of a page fault. The methods and systems are designed to achieve, among other things, lower cost, longer battery life, and faster user response. Whereas existing approaches for memory management are based on pixel or frame buffer compression, the methods and systems provided focus on the CPU's program (e.g., generic data structure). Focusing on hardware-accelerated memory compression to offload CPU translates higher power efficiency (e.g., ASIC is approximately 100× lower power than CPU) and higher performance (e.g., ASIC is approximately 10× faster than CPU), and also allows for hardware-assisted memory management to offload OS/kernel, which significantly increases response time.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: August 22, 2017
    Assignee: Google Inc.
    Inventor: Shinye Shiu
  • Patent number: 9659650
    Abstract: A multistate register, comprising: a flip-flop that comprises a first latch, a second latch and an intermediate gate coupled between the first and second latches; multiple memristive devices; and an interface coupled between the multiple memristive devices and the flip-flop; wherein the multistate register is arranged to operate in a memristive device write mode, in a memristive device read mode and in a flip-flop mode; wherein when operating in the memristive device read mode, the interface is arranged to write to a first selected memristive device of the multiple memristive devices a first logic value stored in the first latch; wherein when operating in the memristive device write mode, the interface is arranged to write to the second latch a second logic value stored in a second selected memristive device of the multiple memristive devices; and wherein when operating on a flip-flop mode logic the interface is prevented from transferring values between the flip flop and the memristive devices.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: May 23, 2017
    Assignee: TECHNION RESEARCH & DEVELOPEMENT FOUNDATION LTD.
    Inventors: Avinoam Kolodny, Shahar Kvatinsky, Ravi Patel, Eby Friedman
  • Patent number: 9652323
    Abstract: A computer memory access method includes: receiving external data with a prefetching length, the external data having an unmasked first data portion and a masked second data portion; writing the unmasked first data portion to a corresponding data storage unit of a computer memory by a writing unit and reading a third data portion corresponding to the masked second data portion from the data storage unit by a reading unit; producing modified external data by merging the unmasked first data portion and the third data portion in place of the masked second data portion; generating parity bits from the modified external data by an error correction code encoding circuit according to a given rule; and then writing the parity bits to a parity bit storage unit of the computer memory by the writing unit, in substitution of previous information in the parity bit storage unit.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: May 16, 2017
    Assignee: XI'AN UNIIC SEMICONDUCTORS CO., LTD.
    Inventors: Alessandro Minzoni, Ni Fu
  • Patent number: 9651617
    Abstract: Transitioning to all addresses of a memory array during BIST includes arranging the addresses as a matrix with rows of the matrix corresponding one to one to the plurality of addresses of the memory array and columns of the matrix corresponding one to one to the plurality addresses of the memory array. A column of a selected current location can correspond to a destination address of a memory transition. The destination addresses can identify a candidate row of the matrix which corresponds to the destination address. The candidate row can be different from a row of the current location. A next location can be determined that has not been recorded in the candidate row that has a minimum column distance from the column of the first location as compared to other locations that have not been recorded in the candidate row.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: May 16, 2017
    Assignee: NXP USA, Inc.
    Inventors: Edward Bryann C. Fernandez, David W. Chrudimsky, Thomas Jew
  • Patent number: 9640253
    Abstract: A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: May 2, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Kevin Michael Conley, Raul-Adrian Cernea, Eran Sharon, Idan Alrod
  • Patent number: 9634861
    Abstract: Techniques for reducing error in time-of-flight measurement due to transceiver latency are disclosed. A method includes determining a first indicator of a first latency of a first transceiver of a first system using a first loopback configuration of the first transceiver. The method includes receiving a second indicator of a second latency of a second transceiver determined by a second system using a second loopback configuration of the second transceiver. The method includes determining a third indicator of a roundtrip latency of a communication from the first transceiver to the second transceiver and back to the first transceiver. The method includes determining a time-of-flight between the first system and the second system based on the first indicator, the second indicator, and the third indicator.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: April 25, 2017
    Assignee: Silicon Laboratories Inc.
    Inventor: Aaron J. Caffee
  • Patent number: 9612940
    Abstract: A device receives test methods that include input arguments that match parameters. The test methods are used to test one or more portions of dynamically-type programming code, and the parameters define conditions for the test methods. The device receives one or more values for each of the parameters, and applies the parameters and the one or more values to different ones of the test methods. The device executes the different ones of the test methods, with the applied parameters and the applied one or more values, to generate results, and outputs or stores the results.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: April 4, 2017
    Assignee: The MathWorks, Inc.
    Inventors: David Hruska, Andrew T. Campbell, David A. Foti, David M. Saxe
  • Patent number: 9602134
    Abstract: An operating method of an ECC decoder includes receiving first chunk data and second chunk data from a nonvolatile memory device, the second chunk data subsequent to the first chunk data, performing error correction on the first chunk data, determining if the first chunk data includes an uncorrectable error bit and determining not to perform error correction on the second chunk data in response to the first chunk data including the uncorrectable error bit.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: March 21, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Sik Kim, Young-Jin Cho
  • Patent number: 9575861
    Abstract: A system on chip is provided which performs a built-in self-test operation using an error access pattern. The system on chip includes a master device and a slave device. A bus is configured to transfer an instruction from the master device to the slave device. A built-in instruction capture circuit is configured to receive and store the instruction. The built-in instruction capture circuit stores the instruction as the error access pattern when an error occurs in the slave device due to the instruction.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: February 21, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yong-Jun Hong
  • Patent number: 9563527
    Abstract: A server stores multiple configuration data which respectively provide different functions to a test system. A tester hardware is configured to be capable of changing at least a part of its functions according to the configuration data stored in nonvolatile memory included in the tester hardware. A control program is installed on an information processing apparatus. The control program provides the information processing apparatus with (i) a function of displaying multiple configuration data candidates on a display when the test system is set up, and (ii) a function of writing the configuration data selected by the user to the nonvolatile memory of the tester hardware.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: February 7, 2017
    Assignee: ADVANTEST CORPORATION
    Inventor: Tomoyuki Yamane
  • Patent number: 9557379
    Abstract: According to one embodiment, a semiconductor integrated circuit includes memories, comparison circuits, first registers and a BIST. The comparison circuits compare output values of the memories with expected values, respectively. The first registers store comparison result data in the comparison circuits, respectively. The BIST controls tests of the memories and generates the expected values. A relief data generator generates relief data indicating the presence of a defect of each of the memories and a failure position on the basis of the comparison result data stored in a second register in the BIST. A third registers store the relief data and are smaller in number than the memories. A judgment circuit outputs a relief impossible signal when the total number of the relief data is greater the number of the third registers.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: January 31, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chikako Tokunaga, Kenichi Anzou
  • Patent number: 9508404
    Abstract: A semiconductor memory device includes, in part, a first data I/O block and a second data I/O block. During a write operation, the first data I/O block transmits input data supplied through a first pad to a first global I/O line, and further generates a write internal signal. The second data I/O block transmits the write internal signal to a second pad in response to a monitor enable signal. During a read operation, the first data I/O block supplies data from the first global I/O line to a first pad, and further generates a read internal signal. The second data I/O block transmits the read internal signal to the second pad in response to a monitor enable signal.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: November 29, 2016
    Assignee: SK hynix Inc.
    Inventor: Jin Ah Kim
  • Patent number: 9443601
    Abstract: The various embodiments described herein include circuits, methods and/or devices used to protect data in a storage device. In one aspect, a method includes performing a power fail operation on a first section of the storage device. The power fail operation includes supplying power, via an energy storage device, to the first section of the storage device, where the energy storage device is distinct from a power source used during normal operation of the storage device, and where supplying power via the energy storage device includes switching the output of the energy storage device from an output of a boost regulator to an input of the boost regulator. The power fail operation also includes performing data hardening on the first section of the storage device.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: September 13, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Gregg S. Lucas, Robert W. Ellis
  • Patent number: 9442842
    Abstract: A nonvolatile memory die is tested to determine certain parameters such as read time, which are then recorded in the nonvolatile memory die. After the die is incorporated into a memory system, and firmware is downloaded, the nonvolatile memory system uses the recorded parameters to determine how to configure the memory system for operation within specified limits, such as determining how much delay to apply to read operations.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: September 13, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Preeti Yadav, Barys Sarana, Abhijeet Bhalerao, Frederick Fernandez, Namita Joshi
  • Patent number: 9412466
    Abstract: The present technology relaxes the precision (or full data-correctness-guarantees) requirements in memory operations, such as writing or reading, of MLC memories so that an application may write and read a digital data value as an approximate value. Types of MLCs include Flash MLC and MLC Phase Change Memory (PCM) as well as other resistive technologies. Many software applications may not need the accuracy or precision typically used to store and read data values. For example, an application may render an image on a relatively low resolution display and may not need an accurate data value for each pixel. By relaxing the precision or correctness requirements is a memory operation, MLC memories may have increased performance, lifetime, density, and/or energy efficiency.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: August 9, 2016
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Karin Strauss, Douglas C. Burger, Luis Henrique Ceze, Adrian Sampson
  • Patent number: 9396774
    Abstract: A semiconductor memory apparatus includes a CAS latency setting circuit configured to change an initially-set CAS latency value in response to control signal pulses which are sequentially applied, during a test mode without changing settings of a mode register set during each test.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: July 19, 2016
    Assignee: SK hynix Inc.
    Inventor: Seong Jun Lee
  • Patent number: 9362005
    Abstract: A semiconductor device includes a plurality of memory chips and a plurality of signal selection units respectively corresponding to the plurality of memory chips, and suitable for commonly transferring test data signals from an external to a corresponding one of the plurality of memory chips during a common test mode, wherein one or more of the plurality of signal selection units may transfer the test data signals from the external to corresponding ones of the plurality of memory chips during an individual test mode, and wherein the semiconductor device may be set to the common test mode when a common test signal is enabled, and set to the individual test mode when both the common test signal and a test control signal are enabled.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: June 7, 2016
    Assignee: SK Hynix Inc.
    Inventors: Jae-Bum Ko, Sang-Jin Byeon
  • Patent number: 9361196
    Abstract: A memory device with a background built-in self-repair module (BBISRM) includes a main memory, an arbiter, and a redundant memory to repair a target memory under test (TMUT). The memory device also includes a background built-in self-test module (BBISTM) to identify portions of memory needing background built-in self-repair (BBISR). The BBISRM or the BBISTM can operate simultaneously while the memory device is operational for performing external accesses during field operation. The BBISR can detect and correct a single data bit error in the data stored in the TMUT. The arbiter configured to receive a read or write access memory request including a memory address, to determine if the memory address of the read or write access memory request matches the memory address mapped to the selected portion of the redundant memory, and to read or write data from the selected portion of the redundant memory, respectively.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: June 7, 2016
    Assignee: MoSys, Inc.
    Inventors: Bendik Kleveland, Dipak K Sikdar, Rajesh Chopra, Jay Patel