Abstract: Systems and methods are provided for estimating LLR values used for soft decoding of data stored in non-volatile storage devices. A method may include reading data stored in a non-volatile storage device using a group of soft read reference voltages, decoding the data read from the non-volatile storage device in a soft decoding process, obtaining a number of ones and a number of zeros for each zone of a plurality of zones delineated by the group of soft read reference voltages and obtaining a log-likelihood ratios (LLR) for each zone of the plurality of zones based on a ratio of the number of ones to the number of zeros in each zone.

Abstract: Rather than use one long folding operation to fold data from single-level cell (SLC) blocks into a multi-level cell (MLC) block, a storage system uses a multi-stage folding operation. By breaking up the folding process into stages, SLC blocks involved in an earlier stage can be released prior to a subsequent stage being performed. This can increase performance of the storage system by releasing SLC source blocks sooner and reducing an SLC block budget requirement.

Abstract: Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read.

Abstract: Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable read broadcast operations. A read broadcast may occur from the memory array to multiple locations of the signal development cache, for example via one or more multiplexers.

Abstract: A system includes a memory device having groups of managed units and a processing device coupled to the memory device. The processing device, during power on of the memory device, causes a read operation to be performed at a subset of a group of managed units and determines a bit error rate related to data read from the subset of the group of managed units. The bit error rate is a directional bit error rate resulting from an erroneously determined state compared to a programmed state that transitions between two opposing states. In response to the bit error rate satisfying a threshold criterion, the processing device causes a rewrite of the data stored at the group of managed units.

Abstract: The present disclosure relates to a memory test system and a memory test method. The memory test system comprises: a plurality of test devices, a host computer, and driving modules. Each of the test devices is provided with a test interface used for connecting a memory to be tested. The host computer is respectively connected to the plurality of test devices and configured to control the test devices to test the memory to be tested. The driving modules are connected to the test devices and configured to output, to the test devices, driving signals used for driving the test devices to perform data interaction with the host computer.

Abstract: A method for performing memory calibration and an associated System on Chip (SoC) Integrated Circuit (IC) are provided. The method may include: in a power-up and initialization phase, controlling a physical layer (PHY) circuit within the SoC IC to apply power to a memory through a pad set and perform initialization on the memory; in an impedance-calibration-related phase, triggering the memory to perform impedance calibration regarding a set of data pins; in at least one subsequent phase, during performing any calibration operation among a reading-related calibration operation and a writing-related calibration operation, performing a data access test corresponding to a set of test points on a predetermined mask, wherein the predetermined mask is movable with respect to a data eye; and according to whether the data access test is successful, selectively stopping the any calibration operation.

Abstract: A method for determining a resultant data word when accessing memory cells includes reading a set of memory cells, and determining first and second data words therefrom. Each memory cell is assigned a component of the first and second data words. The first and second data words for the respective memory cell assume a first value if a first comparison with a first reference value and a second comparison with a second reference value show that the two reference values are greater and assume a second value if the first comparison with the first reference value and the second comparison with the second reference value show that the two reference values are smaller. The first and second data words assume at least one third value if neither condition is satisfied. The resultant data word is determined based on the first or second data words. A corresponding device is also proposed.

Abstract: A test method includes: generating an error correction code according to a base data; dividing the base data into a plurality of base data sections; generating a plurality of candidate testing data according to the base data, wherein each of the candidate testing data has a plurality of testing data sections, and each of the testing data sections corresponds to each of the base data sections; and, performing a plurality of testing schemes. Each of the testing schemes includes: generating a plurality of write-in test data according to the plurality of candidate testing data, and writing the plurality of write-in test data with the error correction code into a tested device continuously; reading a plurality of mode register values of the tested device and a plurality of readout data from the tested device; and generating a test result according to the plurality of mode register value and the readout data.

Abstract: A memory test method includes: testing a first memory to acquire defect information of the first memory; acquiring repair information of the first memory according to the defect information of the first memory; and storing the repair information of the first memory in a second memory. In the technical solutions provided in the embodiments of the present disclosure, other memories may be used to store the repair information of the currently tested memory, so that the storage space can be increased and the test efficiency can be improved.

Abstract: In an embodiment, a method for managing self-tests in an integrated circuit (IC) includes: receiving built-in-self-test (BIST) configuration data; configuring a first clock to a first frequency based on the BIST configuration data; performing a first BIST test at the first frequency; configuring a second clock to a second frequency that is different from the first frequency; and performing a second BIST test at the second frequency.

Abstract: Disclosed herein is an apparatus that includes a data terminal, a memory cell array, a mode register storing a plurality of operation parameters, and an output circuit configured to output, in response to a read command, an incorrect data to the data terminal instead of a correct data read from the memory cell array when a predetermined one of the operation parameters indicates a test mode.

Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Abstract: A storage device for performing a reliability check by using error correction code (ECC) data is provided. The storage device includes a memory controller configured to detect the number of errors of second read data read out by a second read operation, based on ECC data of first read data read by a first read operation of a memory device. The memory controller includes a memory check circuit that includes a counter configured to count states of memory cells, a comparator configured to compare respective count numbers of the states with one another, and a register configured to store the number of errors based on a result of the comparison.

Abstract: Provided are standby circuit dispatch method, apparatus, device and medium. The method includes: a first test item is executed and first test data is acquired, the first test data including position data of a failure bit acquired during execution of the first test item; a first redundant circuit dispatch result is determined according to the first test data; a second test item is executed and second test data is acquired; when the failure bit acquired during execution of the second test item includes a failure bit outside the repair range of the dispatched regional redundant circuits and dispatched global redundant circuits, and the dispatchable redundant circuits have been dispatched out, a maximum target bit umber is acquired according to the first test data and the second test data; and a target dispatch mode is selected and a second redundant circuit dispatch result is determined according to the target dispatch mode.

Abstract: A method and device for Fail Bit (FB) repairing. The method includes: a bank to be repaired of a chip to be repaired is determined; first repair processing is performed on first FBs in each target repair bank using a redundant circuit; second FBs are determined, and second repair processing is performed on the second FBs through a state judgment repair operation; for each target repair bank, unrepaired FBs in the target repair bank is determined, and candidate repair combinations and candidate repair costs of the unrepaired FBs are determined using an optimal combined detection manner; and a target repair cost is determined according to the candidate repair costs, and a target repair solution corresponding to the target repair cost is determined to perform repair processing on the unrepaired FBs according to the target repair solution.

Abstract: Various embodiments relate to a detector circuit, including: a voltage source configured to produce a first voltage on a first output, a second voltage on a second output, and third voltage on a third output, wherein the first voltage is greater than the second voltage and the second voltage is greater than the third voltage; a first switch connected to the second output; a sampling capacitor connected to the switch, wherein the sampling capacitor is charged by the voltage source when the switch is closed; a first comparator with one input connected to the first output and a second input connected to the sampling capacitor; a second comparator with one input connected to the third output and a second input connected to the sampling capacitor; a multiplexer with a plurality of inputs configured to be connected to a plurality of terminals of an external circuit and an output connected to the sampling capacitor, the first input of the first comparator, and the first input of the second comparator; and a controll

Abstract: Losses of event datasets in computing networks can be detected and managed according to some examples. One example can include a system that can identify a slot among a group of slots of a ring buffer in which to store an event dataset. The system can determine a sequence number to associate with the event dataset. The system can then write the sequence number in a first predefined area of the slot of the ring buffer. Additionally, the system can initiate a write process for writing the event dataset in a second predefined area of the slot of the ring buffer, the second predefined area being separate from the first predefined area. The system can detect a completion of the write process and, in response to detecting the completion of the write process, include a write-completion indicator in the first predefined area.

Abstract: Where large transport blocks are rate-matched and transmitted on each PUSCH segment using different redundancy versions (RVs), RV cycling with a small number of PUSCH segments might not cover the whole codeword, and/or rate-matching a large TBS across many PUSCH segments into the resource of a single PUSCH segment may lead to an effective coding rate of the self-decodable redundancy versions that is too high. To avoid these issues, the starting position of one or more RVs may be shifted by setting the starting position of a current RV to be the same as an ending position of a previous position, or by scaling the starting position by a value. Alternatively, these issues may be avoided by setting a new starting position for an RV based on the gap from the end of a previous RV to the start of a current RV.

Abstract: A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

Abstract: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

Abstract: A system and method for optimizing seasoning trim values based on form factors in memory sub-system manufacturing. An example method includes selecting a baseline set of trim values based on a set of memory sub-system form factors; generating a first modified set of trim values for seasoning operations by modifying a first trim value of the baseline trim values; causing each memory sub-system of a plurality of memory sub-systems to perform seasoning operations using the first modified set of trim values; responsive to determining that a memory sub-system of the plurality of memory sub-system failed to satisfy a predetermined criterion, determining whether the memory sub-system is extrinsically defective; responsive to determining that the memory sub-system is extrinsically defective, removing the extrinsically defective memory sub-system from the set of memory sub-systems; and generating a second modified set of trim values for seasoning operations.

Abstract: Memory, used by a computer to store data, is generally prone to faults, including permanent faults (i.e. relating to a lifetime of the memory hardware), and also transient faults (i.e. relating to some external cause) which are otherwise known as soft errors. Since soft errors can change the state of the data in the memory and thus cause errors in applications reading and processing the data, there is a desire to characterize the degree of vulnerability of the memory to soft errors. In particular, once the vulnerability for a particular memory to soft errors has been characterized, cost/reliability trade-offs can be determined, or soft error detection mechanisms (e.g. parity) may be selectively employed for the memory. In some cases, memory faults can be diagnosed by redundant execution and a diagnostic coverage may be determined.

Abstract: Technology is disclosed herein for testing circuitry that controls memory operations in a memory structure having non-volatile memory cells. The testing of the circuitry can be performed without the memory structure. The memory structure may reside on one semiconductor die, with sense blocks and a control circuit on another semiconductor die. The control circuit is able to perform die level control of memory operations in the memory structure. The control circuit may control the sense blocks to simulate sensing of non-volatile memory cells in the memory structure even though the sense blocks are not connected to the memory structure. The control circuit verifies correct operation of the semiconductor die based on the simulated sensing. For example, the control circuit may verify correct operation of a state machine that controls sense operations at a die level. Thus, the operation of the semiconductor die may be tested without the memory structure.

Abstract: An amplification-based read disturb information determination system includes a storage device coupled to a global read temperature identification system. The storage device amplifies data errors in a first row in its storage subsystem by shifting a first value voltage reference level associated with the first row to provide a second value voltage reference level, reads data stored in bits provided in the first row and error correction information associated with the data, and uses the error correction information to identify a number of the bits that store portions of the data with errors. For the first row and based on the number of bits that store portions of the data with errors, the storage device determines read disturb information and uses it to generate a read temperature for a second row in its storage subsystem that it provides to the global read temperature identification system.

Abstract: An arithmetic device includes an auto-command/address generation circuit, a first data storage circuit, and a second data storage circuit. The auto-command/address generation circuit generates an auto-load selection signal that activates an auto-load operation based on a level of a power source voltage. In addition, the auto-command/address generation circuit generates an auto-load command for the auto-load operation. The first data storage circuit outputs look-up table data, to which an activation function is applied, based on the auto-load command. The second data storage circuit stores the look-up table data, output from the first data storage circuit, based on the auto-load command.

Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, determining that a value of a write counter associated with the memory device satisfies a first threshold criterion. The operations performed by the processing device further include, responsive to determining that the value of the write counter satisfies the first threshold criterion, identifying a first memory unit and a second memory unit of the memory device, the second memory unit comprising one or more memory cells adjacent to one or more memory cells of the first memory unit. The operations performed by the processing device further include performing a read operation on the second memory unit to determine a set of failed bit count statistics corresponding to a plurality of codewords of the second memory unit.

Abstract: In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster.

Abstract: A method for testing a circuit includes performing, by a test engine, a test of bit write to a memory. The test includes defining a bit group based on a set of bits from an address of a memory location. The test further includes generating a bit mask for the bit group. The test further includes performing a bit write operation to the address to store a sequence of bits, the sequence of bits selected using a predetermined bit pattern. The test further includes reading content of the address. The test also includes comparing, using the bit mask, only bits corresponding to the bit group from the sequence of bits and from the content of the address.

Abstract: A diagnosis circuit makes a diagnosis of a first multiplexer. The first multiplexer receives input data elements, selects one of the input data elements, and outputs the selected one as a selected data element. The diagnosis circuit includes a comparator unit and a second multiplexer. The comparator unit compares each of the input data elements to be supplied to the first multiplexer with the selected data element provided by the first multiplexer. The second multiplexer receives comparative data elements corresponding one to one to results of comparison made by the comparator unit with respect to the input data elements and outputs, out of the comparative data elements, a comparative data element, including a result of comparison between the one input data element selected by the first multiplexer and the selected data element, as a result data element.

Abstract: The method for monitoring a wireless link of a wireless node of a CPE device during operation of the CPE device, comprises the steps of taking samples of one or several of the following parameters in a defined time interval: Received Signal Strength (RSSI), modulation rate (Physical Layer Rate) and/or the number of spatial streams used for the wireless link, and calculating an average for that parameters by including a filtering of said parameters.

Abstract: An SRAM includes multiple memory cells, each memory cell includes a data storage unit; a data I/O control adapted to input data to, and output data from, a data line (BL); and multiple access controls respectively connected to at least two access control lines (WL's) and adapted to enable and disable the data input and output from the at least two WL's (WX and WY). The access controls are configured to permit data input only when both WL's are in their respective states that permit data input. A method of writing to a group of SRAM cells include sending a first write-enable signal to the cells via a first WL, sending a group of respective second write-enable signals to the respective cells, and, for each of the cells, preventing writing data to the cell if either of the first write-enable signal and respective second write enable signal is in a disable-state.

Abstract: An arithmetic device includes an auto-command/address generation circuit, a first data storage circuit, and a second data storage circuit. The auto-command/address generation circuit generates an auto-load selection signal that activates an auto-load operation based on a level of a power source voltage. In addition, the auto-command/address generation circuit generates an auto-load command for the auto-load operation. The first data storage circuit outputs look-up table data, to which an activation function is applied, based on the auto-load command. The second data storage circuit stores the look-up table data, output from the first data storage circuit, based on the auto-load command.

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

Abstract: A verifying method for an error checking and correcting (ECC) circuit of a static random-access memory (SRAM) is provided. The SRAM comprises a storage unit, an ECC circuit and a checking circuit. The ECC circuit receives an original data and an output first data. The checking circuit obtains a second data according to an error-injecting mask. The checking circuit performs a bit operation on the first data and the second data to obtain a third data. The checking circuit writes the third data into a test target area of the storage unit and the written data as a fourth data. The checking circuit reads the fourth data from the test target area. The ECC circuit obtains a fifth data and an error message according to the fourth data. The checking circuit obtains the bit error detection result according to the error message and the second data.

Abstract: The disclosure relates to an initialization circuit for initializing memory cells of a memory array including a common bit line. Individual memory cells are coupled to the common bit line of the memory array via at least one pass element of the individual memory cells. The initialization circuit is operable for receiving a set of partition addresses specifying the partitions, i.e. the memory cells to be initialized. The initialization circuit is operable for successively initializing one cell of the partitions to be initialized and iteratively initializing the remaining memory cells of the partitions to be initialized. A number of memory cells initialized simultaneously in one iteration increases from one iteration to another iteration. Initializing a certain memory cell comprises activating the pass element of the cell so that the memory cell is connected to the bit line. Further aspects relate to methods for initializing memory cells and semiconductor circuits.

Abstract: A method includes writing, to a first sub-set of memory blocks of a first plane associated with a memory device, first data corresponding to recovery of an uncorrectable error and writing, to a first sub-set of memory blocks of a second memory plane associated with the memory device, second data corresponding to recovery of the uncorrectable error. A relative physical location of the first sub-set of memory blocks of the first memory plane and a relative physical location of the first sub-set of memory blocks of the second memory plane are a same relative physical location with respect to the first memory plane and the second memory plane.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit and a control logic circuit to control the ECC circuit. The memory cell array includes memory cells and a normal cell region and a parity cell region The ECC circuit, in a normal mode, receives a main data, performs an ECC encoding on the main data to generate a parity data and stores the main data and the parity data in the normal cell region and the parity cell region. The ECC circuit, in a test mode, receives a test data including at least one error bit, stores the test data in one of the normal cell region and the parity cell region and performs an ECC decoding on the test data and one of the main data and the parity data to provide a decoding result data to an external device.

Abstract: A position-measuring device includes a graduation carrier having a measuring graduation, position measurement electronics, a data memory and a power supply. The data memory includes a first memory which is a volatile memory for storing additional data, a second memory which is a writable non-volatile memory, and a memory controller for controlling transfer and storage of additional data from the first into the second memory. The power supply includes an input stage, a first output stage for the position measurement electronics, a second output stage for the data memory, and a voltage monitor which will turn off the first output stage of the power supply in response to a drop below a minimum value and signal the drop to the memory controller by a backup signal. In response to the backup signal, the memory controller will transfer additional data from the first memory into the second memory.

Abstract: Methods, systems, and devices for recovery of logical-to-physical (L2P) table information for a memory device are described. A memory system may detect an error in one or more pointers of the L2P table using an error detecting code that is uncorrectable using the code. The memory system may determine a set of candidate codewords for the set of bits, where each of the candidate codewords includes one or more corresponding candidate pointers, and check whether a candidate codeword is correct based on whether a logical address corresponding to a candidate pointer of the candidate codeword matches a logical address stored as metadata for a set of data at a physical address pointed to by the candidate pointer. The memory system may limit the set of candidate codewords or order the candidate codewords for evaluate to reduce a latency associated with identifying a correct candidate codeword.

Abstract: A system and method for optimizing seasoning trim values based on form factors in memory sub-system manufacturing. An example method includes selecting a baseline set of trim values based on a set of memory sub-system form factors; generating a first modified set of trim values by modifying a first trim value of the baseline trim values; instructing each memory sub-system to perform seasoning operations using the first modified set of trim values; responsive to determining that each memory sub-system passed failure scanning operations, generating a second modified set of trim values; instructing each memory sub-system to perform seasoning operations using the second modified set; responsive to determining that a memory sub-system failed the failure scanning operations, determining whether the failed memory sub-system is defective; and responsive to determining that the failed memory sub-system does is not defective, storing the first modified trim values for the set of form factors.

Abstract: A write circuit for writing to a plurality of memory cells of a non-volatile data memory, including a buffer memory forming a single memory element which is configured to buffer a first data value before storing said value in the plurality of non-volatile memory cells of the non-volatile data memory. The write circuit also includes a first write line, by means of which the buffer memory is connected to a first memory cell of the plurality of memory cells, and a second write line, which is different from the first write line and by means of which the buffer memory is connected to a second memory cell of the plurality of memory cells.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a voltage distribution metric associated with a at least part of a block of the memory device; determining a threshold value for the voltage distribution metric associated with the block; and responsive to determining that the voltage distribution metric exceeds the threshold value, performing a media management operation with respect to the block.

Abstract: A memory device, and a method of operating the same, includes a plurality of pages, a peripheral circuit, and control logic. The peripheral circuit is configured to receive a command, an address, and data from an external controller to program a page selected from among the plurality of pages, and to generate internal input data depending on an input mode for the command, the address, and the data. The control logic is configured to determine whether internal input data is to be generated based on the data depending on the input mode and to control the peripheral circuit so that a program operation of programming the internal input data is performed.

Abstract: The present disclosure provides a method, a device and a terminal for testing a memory chip. The method may include setting an attack mode and random attack parameters, generating a random attack command according to the attack mode and random attack parameters, attacking the memory chip according to the random attack command, and testing the attacked memory chip and generating a test result. This method is able to simulate various types of attacks and can thus perform a suitable test on the memory chip for the types of the actual attack. In addition, since the attacks can be randomized to any memory cell of the memory chip, testing of the whole memory chip is made possible.

Abstract: Generally, a computing system includes processing circuitry, such as one or more processors or other suitable components, and memory devices, such as chips or integrated circuits. The memory devices may be associated with thermal limits. Saving data in such a way that causes a thermal limit of the memory device to be exceeded may cause loss of stored data and/or device over-heating. As discussed herein, a memory controller associated with the processing circuitry may determine whether a thermal limit is expected to be exceeded for a current memory writing operation. When the thermal limit is expected to be exceeded, the memory controller may respond by modifying the memory operation in such a manner that the thermal limit is not exceeded, thereby improving operation of at least the memory device and/or memory controller.

Abstract: A load of a data channel at the time of data writing is reduced. A memory controller includes a specific data pattern retaining unit, a comparator, and an issuance unit. The specific data pattern retaining unit retains a specific data pattern. The comparator compares write data regarding a write command from a host computer with the specific data pattern. The issuance unit issues a specific write request that requests writing of the specific data pattern without supplying the write data to a memory in a case where the write data matches the specific data pattern.

Abstract: A memory system includes a memory device including a memory device including a plurality of blocks, each block having a plurality of pages to store data; and a controller suitable for selecting specific memory blocks among the plurality memory blocks, acquiring error bit information of the plurality of pages in each of the specific memory blocks, generating a memory block group management list of each of the specific memory blocks to classify the specific memory blocks into different memory block groups or a same memory block group based on the error bit information, and performing a test read operation on the plurality of pages in each of the plurality of memory blocks based on whether the specific memory blocks are classified into different memory block groups or the same memory block group.

Abstract: An arithmetic device includes an auto-command/address generation circuit, a first data storage circuit, and a second data storage circuit. The auto-command/address generation circuit generates an auto-load selection signal that activates an auto-load operation based on a level of a power source voltage. In addition, the auto-command/address generation circuit generates an auto-load command for the auto-load operation. The first data storage circuit outputs look-up table data, to which an activation function is applied, to based on the auto-load command. The second data storage circuit stores the look-up table data, output from the first data storage circuit, based on the auto-load command.

Abstract: Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable read broadcast operations. A read broadcast may occur from the memory array to multiple locations of the signal development cache, for example via one or more multiplexers.