Abstract: A memory apparatus may include at least one memory, and a memory controller configured to receive an address signal and a command through shared pins and store data, provided from an external source, within the memory controller when a write command is inputted without the address signal.

Abstract: A test circuit testing a storage circuit and including a controller, a pattern-generator circuit, a comparing circuit, and a first register is provided. The storage circuit includes a storage block. The controller is configured to generate a plurality of internal test signals. The pattern-generator circuit generates and provides test data to the storage circuit according to the internal test signal. The storage circuit writes the test data into the storage block and reads the storage block to generate read data. The comparing circuit compares the test data and the read data to generate a test result. The first register stores the test result. The controller determines whether the storage circuit is working normally according to the test result stored in the first register.

Abstract: An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a memory configured to store a line of data and an error correcting code (ECC) syndrome associated with the line of data, where the ECC syndrome is calculated based on the line of data and the ECC syndrome is a first type ECC. The cache subsystem also includes a controller configured to, in response to a request from a master configured to implement a second type ECC, the request being directed to the line of data, transform the first type ECC syndrome for the line of data to a second type ECC syndrome send a response to the master. The response includes the line of data and the second type ECC syndrome associated with the line of data.

Abstract: Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second access line and configured to store a second element. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.

Abstract: A system includes a memory component, and a processing device coupled with the memory component. The processing device to identify a group of management units of the memory component, wherein the group of management units is included in a set of retired groups of management units, select a management unit from the group of management units, perform a media integrity check on the management unit to determine a failed bit count of the management unit, and in response to the failed bit count of the management unit failing to satisfy a threshold criterion, remove the group of management units from the set of retired groups of management units.

Abstract: An imaging device includes a first memory configured to perform writing to multiple addresses thereof by designating the multiple addresses on address-by-address basis, a second memory configured to perform writing simultaneously to multiple address thereof, and a control circuit that controls readout of signals from the first memory and the second memory. The control circuit is configured to perform a first operation mode to sequentially designate the multiple addresses of the first memory and sequentially perform readout of signals from the multiple addresses of the first memory, and a second operation mode to sequentially designate the multiple addresses of the second memory and sequentially perform readout of signals from the multiple addresses of the second memory so that an output value from the second memory becomes the same as a value expected as an output value from the first memory in the first operation mode.

Abstract: Examples include techniques to improve implement an error correction codeword (ECC) scheme to protect data stored to a memory from both hard and random bit errors using a hybrid ECC scheme that includes generation of first and second codewords to protect the data.

Abstract: According to one embodiment, in a memory system, a memory controller is configured to execute a first operation of observing an optimum value of a read voltage and updating a set value based on the observation result of the optimum value, at a predetermined time point of a plurality of time points for updating the set value of the read voltage for a plurality of memory cells, and execute a second operation of updating the set value based on the set value updated at one previous time point without executing the observation of the optimum value, at a time point after one time point of the predetermined time point.

Abstract: A method of verifying a hard post package repair (hPPR) includes steps as follows. A predetermined data background is written into a partial array of a volatile memory. First data are read out from a target row of the partial array of the volatile memory. The volatile memory is commanded to perform the hPPR on the target row. The predetermined data background is written into the partial array of the volatile memory anew after the hPPR has been performed. Second data are read out from a target row of the partial array of the volatile memory. The first data are compared with the second data to verify whether the hPPR fails.

Abstract: A memory apparatus may include at least one memory, and a memory controller configured to receive an address signal and a command through shared pins and store data, provided from an external source, within the memory controller when a write command is inputted without the address signal.

Abstract: A method of erasing data using a file-based protocol from a data storage apparatus for repurposing, reallocation to a new user or retirement of the data storage apparatus, the data storage apparatus comprising a memory using a file-based protocol, and the method comprises: receiving one or more signals representative of the available free space of at least one selected region of the memory; iteratively writing files to the at least one selected region of the memory using the file based protocol, wherein: at least one of the files is sized based on at least one of the received signals and the iterative writing of the files comprises writing the files in sequence such that for at least part of the sequence each file is smaller in size than the preceding file of the sequence; and wherein the files are written to collectively occupy all of the at least one selected region of the memory; and the method further comprises receiving an indication that said at least one selected region of memory is full following the

Abstract: Provided is a semiconductor integrated circuit which can continuously and stably generate an output value even after shipment and a vehicle-mounted control device using the semiconductor integrated circuit. The present invention includes a reference signal generation unit for outputting a reference signal, and detects the operation state of a semiconductor circuit on the basis of a difference between output values from the semiconductor circuit corresponding to the reference signals output at two different time points by the reference signal generation unit.

Abstract: A system for maintaining a repository replication system includes an interface and a processor. The interface is to receive a request to modify a repository, wherein the repository comprises repository copies. The processor is to determine whether modifying the repository resulted in an indication of an error, wherein the indication of the error is based at least in part on a plurality of checksums, wherein a checksum of the plurality of checksums is associated with a repository copy of the repository copies; and in the event that modifying the repository resulted in the indication of the error: queue a repair request to repair the error; and execute a repair process to repair the error associated with the repair request, wherein executing the repair process occurs asynchronously to queuing the error request.

Abstract: A non-volatile memory includes a plurality of physical pages each assigned to one of a plurality of page groups. A controller of the non-volatile memory performs a first calibration read of a sample physical page of a page group of the non-volatile memory. The controller determines if an error metric observed for the first calibration read of the sample physical page satisfies a calibration threshold. The controller calibrates read voltage thresholds of the page group utilizing a first calibration technique based on a determination that the error metric satisfies the calibration threshold and calibrates read voltage thresholds of the page group utilizing a different second calibration technique based on a determination that the error metric does not satisfy the calibration threshold.

Abstract: A mode register control circuit may include a masking signal generation circuit and a storage control pulse generation circuit. The masking signal generation circuit may be configured to generate a masking signal from data. The storage control pulse generation circuit may be configured to generate a storage control pulse for controlling a mode register write operation, from a mode register write pulse in response to the masking signal.

Abstract: Methods for verifying data path integrity are provided. One such method includes reading a partially programmed first set of data from an array of memory cells of the memory device into a page register of the memory device, loading the partially programmed first set of data into a cache register of the memory device, writing a partial set of test data to a portion of the cache register not containing the partially programmed first set of data during a read of a second set of data from the array of memory cells to the page register, reading the partial set of test data from the cache register during the read of the second set of data from the array of memory cells to the page register, and comparing the partial set of test data read from the cache register to the original partial set of test data.

Abstract: A driver of a multi-level signaling interface is provided. The driver may be configured reduce noise in a multi-level signal (e.g., a pulse amplitude modulation signal) generated by the driver using switching components of different polarities. The driver may include a pull-up circuit and/or a pull-down circuit. The pull-up circuit and the pull-down circuit may include at least one switching component of a first polarity (e.g., nmos transistor) and at least one switching component of a second polarity different from the first polarity (e.g., pmos transistor). Such a configuration of pull-up and pull down circuits may generate a more linear relationship between an output current and an output voltage of an output of the driver, thereby improving one or more characteristics of the multi-level signal.

Abstract: A semiconductor device is comprised of a memory cell array with multiple memory cells arranged in a matrix, multiple bit-line pairs provided for each memory cell column in the memory cell array, multiple input/output circuits provided respectively corresponding to the multiple bit-line pairs, and as interface control circuit that controls the data input/output to the multiple input/output circuits when performing the data write and data read for each memory cell row in a normal mode. The interface control circuit is comprised of a selection circuit. When the data write and data read are performed for each memory cell row in a test mode, the selection circuit selects the data input/output to one of first input/output circuit and a second input/output circuit, respectively corresponding to a first memory cell included in the memory cell row and a second memory cell adjoining the first memory cell, according to a test address.

Abstract: A soft information module is coupled between one or more flash memory devices and a decoder. The soft information module receives a putative value of one or more memory cells of the one or more flash memory devices based on a read of the one or more memory cells at an initial read level, and one or more respective indicators of whether the putative value was read at one or more respective different read levels offset from the initial read level, and receives a page indicator for the read. The soft information module determines a cell program region for the read based on the putative value, the one or more respective indicators, and the page indicator, identifies a predetermined confidence value for the region, and provides the confidence value to the decoder for association with the putative value, the confidence value being representative of a likelihood that the one or more memory cells was programmed to the putative value.

Abstract: A method of operation in an integrated circuit (IC) memory device. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

Abstract: Various aspects of the disclosed technology relate to streaming data for testing identical circuit blocks in a circuit. The system for streaming data comprises a first network for transporting equal-sized data packets consecutively and a second network for configuring interface devices of the first network. Each of the data packets comprises bits of test patterns and bits of good-machine test responses. Comparison bits (pass/fail status bits) of an identical circuit block instance may be unloaded directly or may merge with those from other identical circuit block instances to generate accumulated comparison bits which are unloaded. A sticky pass/fail bit may also be generated for each of the identical circuit block instances.

Abstract: A method of forming a read head. The method includes forming first and second read sensors. A first read measurement is performed on a storage medium using the first read sensor. A second read measurement is performed on the storage medium using the second read sensor. Based on a comparison of the first and second read measurements to a predetermined quantity, either the first read sensor or the second read sensor is selected to be operational in a data storage device.

Abstract: Apparatuses and methods are described for selective determination of data error repair. An example apparatus includes a memory array and a controller coupled to the memory array. The controller is configured to direct performance, responsive to a request, of a read operation at an address in the memory array, direct detection of an error in data corresponding to the read operation address, and direct storage of the read operation address in an address error register. The controller is further configured to direct a response be sent to the enable selective determination of data error repair, where the response does not include the read operation address.

Abstract: Embodiments include novel approaches for scan-based device testing using a march controller. A march data store can have sets of march element data stored thereon, each defining a respective march element of a march test sequence. A march select register can select each stored set of march element data according to the predefined march test sequence, and a march data loader can iteratively and sequentially output each set of march element data selected by the march select register. A memory built-in self-test controller can generate, in response to receiving each set of march element data output by the march controller, test stimulus data corresponding to the received set of march element data. The test stimulus data can input to a scan chain of the integrated circuit under test, and response data can be captured from the scan chain and assessed to determine whether the integrated circuit passed the test.

Abstract: A driver of a multi-level signaling interface is provided. The driver may be configured reduce noise in a multi-level signal (e.g., a pulse amplitude modulation signal) generated by the driver using switching components of different polarities. The driver may include a pull-up circuit and/or a pull-down circuit. The pull-up circuit and the pull-down circuit may include at least one switching component of a first polarity (e.g., nmos transistor) and at least one switching component of a second polarity different from the first polarity (e.g., pmos transistor). Such a configuration of pull-up and pull down circuits may generate a more linear relationship between an output current and an output voltage of an output of the driver, thereby improving one or more characteristics of the multi-level signal.

Abstract: A memory device, a memory system, and corresponding methods are provided. The memory device includes a non-volatile random access memory. The non-volatile memory includes a suspect bit register configured to store addresses of bits that are determined to have had errors. The non-volatile memory further includes a bad bit register configured to store addresses of bits that both (i) appeared in the suspect bit register due to a first error and (ii) are determined to have had a second error. Hence, the memory device overcomes the aforementioned intrinsic write-error-rate by identifying the bad bits so they can be fused out, thus avoiding errors during use of the non-volatile random access memory.

Abstract: An apparatus is described. The apparatus includes a memory controller having a programmable component. The programmable component is to implement a data checking function. The programmable component is to receive and process partial results of the data checking function from two or more DIMM cards that are coupled to the memory controller.

Abstract: The present invention provides a data-storage device. The data-storage device includes a flash memory and a controller. The flash memory has a plurality of blocks and each of the blocks has a plurality of pages. The blocks include a plurality of bad blocks that are labeled as damaged. The controller selects one of the bad blocks as a test block, and reads the pages in the test block to determine whether the pages in the test block are damaged. When all the pages in the test block are undamaged, the controller labels the test block as a spare block.

Abstract: Methods and apparatus are provided for read retry operations that estimate written data based on syndrome weights. One method comprises reading a codeword from a memory multiple times using multiple read reference voltages; obtaining a syndrome weight for each of the readings of the codeword; identifying a given reading of the codeword having a substantially minimum syndrome weight; and estimating a written value of the codeword based on the given reading. Two cell voltage probability distributions of cell voltages are optionally calculated for each possible cell state of the memory, based on the estimated written value and plurality of readings of the codeword. The cell voltage probability distributions are used to (i) dynamically select log likelihood ratio values for a failing page, (ii) determine a read reference voltage that gives a desired log likelihood ratio value, or (iii) dynamically select log likelihood ratio values for the page populations associated with the distributions.

Abstract: A semiconductor apparatus includes first and second chips sharing first and second data channels. The first chip compresses first test data of the first chip and outputs the compressed first test data through the first data channel in a first test mode, and the second chip compresses second test data of the second chip and outputs the compressed second test data through the second data channel in the first test mode.

Abstract: Embodiments of the present invention provide a method, computer program product, and computer system for masking indexes. The method may include masking the index if the index contention exceeds a defined threshold. The method may also include configuring the mask type for the index to insert the index without masking. In response to determining that the mask type for the index is configured to insert the index without masking, the index is masked according to a set of rules.

Abstract: A technical solution for improving test times and costs associated with IC production includes a central test engine (CTE) functional test block integrated onto an IC. The CTE functions as a hardware abstraction layer (HAL), and provides testing capabilities by transferring a large test data file to a device under test and performing a closed-loop monitoring of receipt of the expected test data results. The CTE also reduces the number of external interfaces and interface controllers used during testing. The reduction in external interfaces reduces the size of the IC, which enables smaller and more efficient IC manufacturing, and may be used to improve small form-factor high-volume manufacturing (HVM). This reduction in IO pins also enables significant reduction in IO resources (e.g., IO drivers) within the IC, and reduces or eliminates IO test hardware dependencies.

Abstract: A semiconductor system includes a controller and a semiconductor device. The controller outputs a burn-in test signal, a clock signal and command/address signals. The semiconductor device enters a first test mode if the burn-in test signal is inputted. The semiconductor device enters a second test mode according to a level combination of the command/address signals in synchronization with the clock signal after the semiconductor device enters the first test mode. The semiconductor device enters a third test mode according to an other level combination of the command/address signals in synchronization with the clock signal after the semiconductor device enters the second test mode.

Abstract: A system for maintaining a repository replication system includes an interface and a processor. The interface is to receive a request to modify a repository, wherein the repository comprises repository copies. The processor is to determine whether modifying the repository resulted in an indication of an error, wherein the indication of the error is based at least in part on a plurality of checksums, wherein a checksum of the plurality of checksums is associated with a repository copy of the repository copies; and in the event that modifying the repository resulted in the indication of the error: queue a repair request to repair the error; and execute a repair process to repair the error associated with the repair request, wherein executing the repair process occurs asynchronously to queuing the error request.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows; and a data control circuit configured to, sequentially read a first unit of data from N memory cell rows of the plurality of memory cell rows, generate merged test results by comparing bits read from the first units of the N memory cell rows, and output the merged test results, during the test mode of the semiconductor memory device. Therefore, test time for testing the semiconductor memory device may be greatly reduced because a test device may determine pass/fail of the data of the unit of repair unit on one read operation.

Abstract: A semiconductor test device and a semiconductor test method are disclosed. A semiconductor test device may include a DQ signal receiver, a test mode register set signal processor, and a test mode command generator. The DQ signal receiver may receive a first DQ signal through a first DQ pin. The test mode register set signal processor may receive a test mode register set signal in response to the first DQ signal, and may output a test mode register set pulse signal. The test mode command generator may generate a test mode command corresponding to an input address in response to the test mode register set pulse signal.

Abstract: An input/output (I/O) line test device and a method for controlling the same are disclosed, which may relate to a technology for testing a base die having no cell using various patterns. The I/O line test device may include an interface controller configured to perform signal transmission/reception between a pad and an input/output line (IOL), and a signal transceiver configured to perform signal transmission/reception between the IOL and a through silicon via (TSV). The I/O line test device may include a latch unit configured to latch output data of the signal transceiver, and a test controller configured to output a control signal for controlling whether the signal transceiver performs a reception operation in response to a write enable signal and a test signal.

Abstract: A memory built-in self test (“BIST”) system comprises: a controller; a single port memory engine coupled to one or more single port memories; and a non-single port memory engine coupled to one or more non-single port memories. The controller receives operation codes (“op-codes”) for testing a plurality of memory types. An output of the controller is coupled to inputs of the single port memory engine and the non-single port memory engine. The controller generates test instructions based on the received op-codes. The single port memory engine and the non-single port memory engine interpret the test instructions to test the one or more single port memories and the one or more non-single port memories.

Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.

Abstract: A data processing apparatus includes a circuit selector and a data processor. The circuit selector makes a selection, in data processing in which multiple unit processes are each selected and repeated, from a generalized circuit that executes the multiple unit processes and one of dedicated circuits that are each dedicated to a corresponding one of the unit processes, the selection being made repeatedly on a basis of a judgment made using continuous repeat counts each of which indicates how many times a corresponding one of the unit processes is continuously repeated. The data processor selectively configures one of the generalized circuit and the dedicated circuit that corresponds to one of results serially obtained from the selection repeatedly made by the circuit selector, the data processor performing the data processing.

Abstract: Embodiments of the present invention provide a method, computer program product, and computer system for masking indexes. The method may include masking the index if the index contention exceeds a defined threshold. The method may also include configuring the mask type for the index to insert the index without masking. In response to determining that the mask type for the index is configured to insert the index without masking, the index is masked according to a set of rules.

Abstract: Embodiments of the present invention provide a method, computer program product, and computer system for masking indexes. The method may include masking the index if the index contention exceeds a defined threshold. The method may also include configuring the mask type for the index to insert the index without masking. In response to determining that the mask type for the index is configured to insert the index without masking, the index is masked according to a set of rules.

Abstract: The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to sensing circuitry and is configured to cause storing of an indication of whether a logical operation is to be selectively performed between an operand stored in the sensing circuitry and an operand stored in the sense amplifier.

Abstract: A method of isolating hidden data in a solid state memory system is disclosed including obtaining a logical block address (LBA) image from the memory system, obtaining a physical block address (PBA) image, determining whether an error exists in the PBA image and correcting the error, calculating an ETCRC on each sector of the LBA image and building a search tree indexed on the ETCRC value. For each sector in the PBA image, the method also includes computing an error tolerant cyclic redundancy check (ETCRC) value and searching for the ETCRC value in the LBA search tree. If the ETCRC value is found, also included is comparing the cyclic redundancy check (CRC) of the LBA and PBA sectors, and outputting to an output file the PBA sector as hidden data if either the ETCRC value is not found in the LBA search tree or the CRC comparison fails.

Abstract: Provided are methods and systems for managing memory using a hardware-based page filter designed to distinguish between active and inactive pages (“hot” and “cold” pages, respectively) so that inactive pages can be compressed prior to the occurrence of a page fault. The methods and systems are designed to achieve, among other things, lower cost, longer battery life, and faster user response. Whereas existing approaches for memory management are based on pixel or frame buffer compression, the methods and systems provided focus on the CPU's program (e.g., generic data structure). Focusing on hardware-accelerated memory compression to offload CPU translates higher power efficiency (e.g., ASIC is approximately 100× lower power than CPU) and higher performance (e.g., ASIC is approximately 10× faster than CPU), and also allows for hardware-assisted memory management to offload OS/kernel, which significantly increases response time.

Abstract: A multistate register, comprising: a flip-flop that comprises a first latch, a second latch and an intermediate gate coupled between the first and second latches; multiple memristive devices; and an interface coupled between the multiple memristive devices and the flip-flop; wherein the multistate register is arranged to operate in a memristive device write mode, in a memristive device read mode and in a flip-flop mode; wherein when operating in the memristive device read mode, the interface is arranged to write to a first selected memristive device of the multiple memristive devices a first logic value stored in the first latch; wherein when operating in the memristive device write mode, the interface is arranged to write to the second latch a second logic value stored in a second selected memristive device of the multiple memristive devices; and wherein when operating on a flip-flop mode logic the interface is prevented from transferring values between the flip flop and the memristive devices.

Abstract: A computer memory access method includes: receiving external data with a prefetching length, the external data having an unmasked first data portion and a masked second data portion; writing the unmasked first data portion to a corresponding data storage unit of a computer memory by a writing unit and reading a third data portion corresponding to the masked second data portion from the data storage unit by a reading unit; producing modified external data by merging the unmasked first data portion and the third data portion in place of the masked second data portion; generating parity bits from the modified external data by an error correction code encoding circuit according to a given rule; and then writing the parity bits to a parity bit storage unit of the computer memory by the writing unit, in substitution of previous information in the parity bit storage unit.

Abstract: Transitioning to all addresses of a memory array during BIST includes arranging the addresses as a matrix with rows of the matrix corresponding one to one to the plurality of addresses of the memory array and columns of the matrix corresponding one to one to the plurality addresses of the memory array. A column of a selected current location can correspond to a destination address of a memory transition. The destination addresses can identify a candidate row of the matrix which corresponds to the destination address. The candidate row can be different from a row of the current location. A next location can be determined that has not been recorded in the candidate row that has a minimum column distance from the column of the first location as compared to other locations that have not been recorded in the candidate row.

Abstract: A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.

Abstract: Techniques for reducing error in time-of-flight measurement due to transceiver latency are disclosed. A method includes determining a first indicator of a first latency of a first transceiver of a first system using a first loopback configuration of the first transceiver. The method includes receiving a second indicator of a second latency of a second transceiver determined by a second system using a second loopback configuration of the second transceiver. The method includes determining a third indicator of a roundtrip latency of a communication from the first transceiver to the second transceiver and back to the first transceiver. The method includes determining a time-of-flight between the first system and the second system based on the first indicator, the second indicator, and the third indicator.