Abstract: To decrease the burden of digital processing, provided is an AD conversion apparatus comprising a pattern generating section that, for each target bit specified one bit at a time moving downward in the output data, generates a pattern signal having a pulse width or number of pulses corresponding to a weighting of the target bit; an integrating section that integrates the pattern signals according to a judgment value for judging a value of the target bit each time a pattern signal is generated, and outputs a reference signal obtained by accumulating the integrated value of each pattern signal; a comparing section that, each time generation of a pattern signal is finished, compares the input signal to the reference signal; and an output section that outputs the output data to have values corresponding to the comparison results obtained after each generation of a pattern signal corresponding to a bit is finished.

Abstract: A semiconductor device includes a plurality of memory cell array units and a test circuit unit. The test circuit unit includes a test data generating unit configured to generate a test data piece per test cycle including a writing period and a retrieving period; an expected value register configured to output the test data piece as an expected value data piece; a memory cell driving unit configured to supply a writing driving signal during the writing period, and a retrieving driving signal during the retrieving period; a data relay switching unit configured to supply the test data piece during the writing period, and to output retrieved data piece during the retrieving period; and a determining unit configured to determine whether the retrieved data piece output from the data relay switching unit matches the expected value data piece, and to generate a test result signal indicating a determination result.

Abstract: A method for testing a memory includes performing an error correction code check (ECC check) on user data stored in the memory, inverting the user data stored in the memory, performing a further ECC check on the inverted user data stored in the memory, and inverting the inverted user data stored in the memory for restoring the user data in the memory.

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to read or write performance of a phase change memory.

Abstract: Data is processed by selecting one or more bits in a codeword to replace with an erasure. The selected bits in the codeword are replaced with the erasure and error correction decoding is performed on the codeword with the erasure in place for the selected bits.

Abstract: Some of the embodiments of the present disclosure provide a system, device and a method performing N read cycles on a plurality of memory cells of a memory sector, wherein N is an integer greater than one; constructing (N+1) bin histograms based at least in part on performing the N read cycles; identifying a shortest bin histogram of the (N+1) bin histograms; and based on a height of the shortest histogram, assigning a log-likelihood ratio (LLR) to the shortest bin histogram. Other embodiments are also described and claimed.

Abstract: A storage apparatus for controlling a storage unit includes a cache memory for temporarily storing data to be stored in the storage unit, and a processor for executing a process including receiving unit data which is divided from data to be migrated, calculating first checksum data from the received unit data, storing the unit data and the first checksum data to the cache memory, reading out the stored unit data and the first checksum data from the cache memory, calculating second checksum data from the read out unit data, storing the unit data to the storage unit, and determining whether data migration has been performed properly by comparing the first checksum data to the second checksum data.

Abstract: A data storage system includes a memory circuit and a control circuit. The control circuit is operable to receive data bits provided for storage in memory cells of the memory circuit. The control circuit is operable to compare each of the data bits provided for storage in a corresponding one of the memory cells having a stuck-at fault to a value of the stuck-at fault, and to invert each of the data bits having a different value than the value of the stuck-at fault of the corresponding one of the memory cells to generate encoded data bits. The control circuit is operable to generate redundant bits that indicate the encoded data bits to invert to regenerate the data bits.

Abstract: A method and apparatus for detecting N-symbol codewords.

Abstract: A method with a circuit that includes a memory (130) coupled to an analog line coverage circuit (104). The analog line coverage circuit includes a plurality of buffers (151-154) in which each buffer is coupled to one memory location of the memory, a plurality of bin cells (161-164) in which each bin cell is coupled to a buffer, a multiplexer (170), each input terminal of which is coupled to a bin cell, and an analog-to-digital converter (180) coupled to the multiplexer and to an output terminal of the analog line coverage circuit. The analog line coverage circuit stores an analog voltage that is representative of a number of occasions that a memory location is accessed, and outputs a signal indicative thereof. A processor (102), coupled to the memory and to the analog line coverage circuit, enables the analog line coverage circuit when the processor is in a debug mode.

Abstract: Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one memory cell whose resultant conductance is measured on the same bit line. The combined sensing result is use for measuring certain statistics of the cell voltage distribution (CVD) of multiple word lines and comparing it to the expected value. In case the measured statistics are different than expected, this may indicate that one or more of the sensed word lines may exhibit a failure and more thorough examination of the group of word lines can be performed.

Abstract: Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested.

Abstract: A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode.

Abstract: A method includes directing an access of a memory location of a memory device to an error correction code (ECC) decoder in response to receiving a test activation request indicating the memory location. The method also includes writing a test pattern to the memory location and reading a value from the memory location. The method further includes determining whether a fault is detected at the memory location based on a comparison of the test pattern and the value.

Abstract: A data storage system configured to perform prioritized memory scanning for memory errors is disclosed. In one embodiment, the data storage system prioritizes scanning for memory errors based on a quality attribute of pages or zones of a non-volatile memory array. Pages or zones having quality attributes that reflect a lower level of reliability or endurance than other pages or zones are scanned more frequently for memory errors. When memory errors are discovered, the quality attribute of pages or zones can be adjusted to reflect a lower level of reliability or endurance. In addition, stored data can be recovered before it may become permanently lost and before a host system reads the stored data. Improved performance of the data storage system is thereby attained.

Abstract: A method and system for monitoring an output of an electronic processing component which detects an out-of-range value in the output of the electronic processing component during one time period during which one channel of input channels of a time multiplexer provides an input signal to the electronic processing component. Corrective actions are performed based on the detected out-of-range value. The corrective actions including excluding further multiplexing of signals from the one channel of the input channels.

Abstract: The present application provides a circuit and method for testing a memory device. The memory device has multiple blocks addressable via a plurality of address lines and capable of inputting and/or outputting data via a plurality of data lines.

Abstract: A memory system with integrated memory built-in self-test (BIST) circuitry has one or more pipeline registers interposed between combinational logic elements. These combinational logic elements can include write data decoding logic, memory control signal decoding logic, address counter logic, address comparison logic, data comparison logic, and next state decoding logic. Features can be included that compensate for the delay inherent in the pipeline registers.

Abstract: An integrated circuit includes memory units and at least one memory test module, each module includes one associated memory unit, a set of test registers therefor, and a test engine configured to perform a test operation on that associated memory unit. A transaction interface of the memory test module receives a transaction specifying a register access operation and providing a first address portion having encodings allowing individual memory units as well as groups of memory units to be identified, and a second address portion identifying one of the test registers within the set to be an accessed register. Decode circuitry, within each memory test module and responsive to the transaction, is configured to selectively perform the register access operation if it is determined that the memory test module includes a set of test registers associated with a memory unit.

Abstract: Aspects of the invention provide for reducing BIST test time for a memory of an IC chip. In one embodiment, a BIST architecture for reducing BIST test time of a memory for an integrated circuit (IC) chip, the architecture comprising: a pair of latches for receiving bursts of data from a memory; a first compression stage for receiving a burst of data and compressing the burst of data into a plurality of latches; a second compression stage for comparing the compressed bursts of data with expected data; and a logic gate for determining whether there is a fail in the burst of data.

Abstract: Apparatus and methods are provided for concurrently selecting multiple arrays of memory cells when accessing a memory element. A memory element includes a first array of one or more memory cells coupled to a first bit line node, a second array of one or more memory cells coupled to a second bit line node, access circuitry for accessing a first memory cell in the first array, a first transistor coupled between the first bit line node and the access circuitry, and a second transistor coupled between the second bit line node and the access circuitry. A controller is coupled to the first transistor and the second transistor, and the controller is configured to concurrently activate the first transistor and the second transistor to access the first memory cell in the first array.

Abstract: Techniques associated with a read and write window budget for a two level memory (2LM) system may include establishing a read and write window budget for the 2LM system that includes a first level memory and a second level memory. The established read and write window budget may include a combination of a first set of memory addresses and a second set of memory addresses of the second level of memory. The first set of memory addresses may be associated with non-volatile memory cells having wider cell threshold voltage distributions compared to cell threshold voltage distributions for non-volatile memory cells associated with the second set of memory addresses. According to some examples, the established read and write window budget may be part of a strategy to meet both a completion time threshold for a given amount of memory and an acceptable error rate threshold for the given amount of memory when fulfilling read or write requests to the second level memory.

Abstract: A parallel test circuit of a semiconductor memory apparatus includes a memory bank which includes first and second sub banks having test global lines, respectively, and sharing a global line connected to each of the first and second sub banks. When a read command is applied during a test mode, the parallel test circuit compares data loaded in the global line to data loaded in the test global line of the second sub bank to attain a comparison result, compresses the comparison result to attain a compression signal, and outputs the compression signal as a test output signal to a pad.

Abstract: Exemplary method, system, and computer program embodiments for performing deterministic data verification by a storage controller are provided. Each of a plurality of concurrent write tasks is configured to be placed in a plurality of overlapping data storage ranges by performing at least one of: implementing a data generation function for generating pseudo-random data using a data seed, and generating a range map, the range map utilized as a lookup data structure to verify a chronological order for performing the plurality of concurrent write tasks, wherein a data address space is first designated in the range map as undetermined. Each of a plurality of read tasks is analyzed by comparing data read from a sub range in the plurality of overlapping data storage ranges against the data seed associated with the sub range.

Abstract: A transmitting device includes a parallel data generation unit and a transmitting unit. The parallel data generation unit generates first serial data and second serial data from a data packet, converts the first serial data and second serial data respectively into first parallel data and second parallel data, transmits the first parallel data and second parallel data respectively through first and second parallel transmission paths, and performs the transmission of the first parallel data and the transmission of the second parallel data in parallel. The transmitting unit receives the first parallel data and second parallel data respectively through the first and second parallel transmission paths, re-converts the first parallel data and second parallel data respectively into the first serial data and second serial data, and transmits the first serial data and second serial data to a receiving device respectively through first and second serial transmission paths.

Abstract: A plurality of stacked memory device die and a logic circuit are connected to each other through a plurality of conductors. The stacked memory device die are arranged in a plurality of vaults. The logic circuit die serves as a memory interface device to a memory access device, such as a processor. The logic circuit die includes a plurality of link interfaces and downstream targets for transmitting received data to the vaults. The logic circuit die includes a packet builder and broadcaster configured to receive command, address and data signals over separate interfaces from a conventional tester, format the signals into a packet and broadcast the signals to a plurality of vaults.

Abstract: Techniques and mechanisms are provided for an improved built in self-test (BIST) mechanism for 3D assembly defect detection. According to an embodiment of the present disclosure, the described mechanisms and techniques can function to detect defects in interconnects which vertically connect different layers of a 3D device, as well as to detect defects on a 2D layer of a 3D integrated circuit. Additionally, according to an embodiment of the present disclosure, techniques and mechanisms are provided for determining not only the presence of a defect in a given set of interfaces of an integrated circuit, but the particular interface at which a defect may exist.

Abstract: A method for operating a memory includes storing data in a plurality of analog memory cells that are fabricated on a first semiconductor die by writing input storage values to a group of the analog memory cells. After storing the data, multiple output storage values are read from each of the analog memory cells in the group using respective, different threshold sets of read thresholds, thus providing multiple output sets of the output storage values corresponding respectively to the threshold sets. The multiple output sets of the output storage values are preprocessed by circuitry that is fabricated on the first semiconductor die, to produce preprocessed data. The preprocessed data is provided to a memory controller, which is fabricated on a second semiconductor die that is different from the first semiconductor die. so as to enable the memory controller to reconstruct the data responsively to the preprocessed data.

Abstract: Methods and circuits for disrupting integrated circuit function. The circuits include finite state machines connected to memory arrays. The finite state machines are sensitive to a predetermined sequence of addresses sent to the memory array or the time between a series of memory array errors detected by an error detection circuit. Upon detection of the pre-set addresses or errors the finite state machines either (i) enable or disable specific circuit functions or (ii) disrupt the operation of the integrated circuit.

Abstract: A loopback card includes a connector configured to connect to an IO interface and emulate a storage device interface. The connector includes a port configured to receive a set of signals from the IO interface and transmit them to a redriver. The connector is configured to receive the set of signals from the redriver and transmit them from the redriver to the IO interface. The connector includes control signal inputs configured to receive control signals from the IO interface. The connector further includes one or more logic gates configured to receive the control signals. The one or more logic gates apply a logic operation on the control signals to generate an output and route the output to the IO interface through the connector. The redriver is operably connected to the port and configured to receive the set of signals from the port and transmit them back to the port.

Abstract: A method includes directing an access of a memory location of a memory device to an error correction code (ECC) decoder in response to receiving a test activation request indicating the memory location. The method also includes writing a test pattern to the memory location and reading a value from the memory location. The method further includes determining whether a fault is detected at the memory location based on a comparison of the test pattern and the value.

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Abstract: A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which performs BIST memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.

Abstract: A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information.

Abstract: A system includes a first device, a first storage element, a comparator and a second device. The first device is configured to test memory cells in an array of memory cells to detect defective memory cells. The defective memory cells include a first memory cell and a second memory cell. The first storage element is configured to store a first address of the first memory cell. The comparator is configured to compare a second address of the second memory cell to the first address.

Abstract: Disclosed are a flash memory device and flash memory programming method that equalizes a wear-level. The flash memory device includes a memory cell array, an inversion determining unit to generate a programming page through inverting or not inverting a data page based on a number of ‘1’s and ‘0’s in the data page, a programming unit to store the generated programming page in the memory cell array; and a data verifying unit to read the programming page stored in the memory cell array, to restore the data page from the programming page according to whether an error exists in the read programming page, and to output the restored data page, and thereby can equalize a wear-level of a memory cell.

Abstract: Provided is a test module that tests a device under test, comprising a pattern generating section that generates a test pattern supplied to the device under test and an expected value pattern corresponding to the test pattern, based on a pattern program; an output pattern acquiring section that acquires an output pattern output by the device under test in response to the test pattern; a comparing section that compares the output pattern output and the expected value pattern; a fail counter that counts the number of times the comparing section indicates a mismatch between the output pattern and the expected value pattern; and a control section that controls operation of the fail counter according to control instructions in the pattern program.

Abstract: Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one memory cell whose resultant conductance is measured on the same bit line. The combined sensing result is use for measuring certain statistics of the cell voltage distribution (CVD) of multiple word lines and comparing it to the expected value. In case the measured statistics are different than expected, this may indicate that one or more of the sensed word lines may exhibit a failure and more thorough examination of the group of word lines can be performed.

Abstract: Apparatuses and methods for memory testing with data compression is described. An example apparatus includes a plurality of latch test circuits, wherein each of the plurality of latch test circuits is coupled to a corresponding global data line of a memory. Each of the latch test circuits is configured to receive test data and is configured to latch data from the corresponding global data line or a corresponding mask bit. Each of the plurality of latch test circuits is further configured to output data based at least in part on the corresponding mask bit. A comparison circuit is coupled to an output of each of the latch test circuits and is configured to compare output data provided by each of the latch test circuits and provide a comparator output having a logical value indicative of whether all the output data matches.

Abstract: In a method of executing a BIST operation on IC memory arrays having a common BIST control unit, a first BIST sequence is initiated. Each address for the arrays is incremented. The BIST control unit receives a signal indicating a maximum valid address in the array is reached, receiving a plurality of maximum valid addresses, which are recorded. A single relatively highest maximum valid address is determined. A first mode, which prevents BIST testing, is engaged in each array having reached the maximum valid address. A second BIST sequence is initiated based on having received the signal indicating a maximum valid address is reached from all the arrays connected to the common BIST control unit. An address count is decremented from the single relatively highest maximum valid address. The first mode is disengaged for each array as the address count reaches each of the maximum valid addresses during the decrementing.

Abstract: A memory error detecting apparatus for detecting an error of a subject memory, the memory error detecting apparatus includes a memory bus connected to the subject memory, a mirror memory connected to the memory bus so as to receive the same data as data to be written into and read from the subject memory, the received data being written into the mirror memory, an address acquiring portion configured to acquire an address related to the data written into the subject memory, a mirror memory controller configured to control data writing or reading to or from the mirror memory on the basis of the acquired address, a comparator configured to compare data read from the subject memory and data read from the mirror memory, and an error detector configured to detect a data error on the basis of a result of the comparison.

Abstract: Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied.

Abstract: A graphics memory device includes a memory array configured to store data for a display device comprising b*y rows by a*x columns of pixels, where b>a. The memory array is arranged in a*y rows by b*x columns of memory locations. Each memory location is adapted to store n-bit image data for one of the pixels of the display device. A memory location remapping circuit is adapted to map image data stored in the b*x columns of memory locations in the memory device to the a*x columns of the display device.

Abstract: In one embodiment, a method of performing data training in a system including a memory controller and at least a first memory device including a group of memory banks is disclosed. The method includes providing a plurality of enabling states for the group of memory banks, wherein each enabling state is different and for each enabling state a set of the memory banks of the group is enabled and any remaining of the memory banks of the group are not enabled. The method further includes performing a first data training procedure that includes a series of first data training operations for the first memory device, each data training operation being performed for a different one of the plurality of enabling states, generating a noise profile based on the series of first data training operations, statistically analyzing the noise profile to select a reference enabling state of the group of memory banks, and performing a second data training procedure for the first memory device using the reference enabling state.

Abstract: This disclosure is related to measurement of latency in data paths. A latency measurement may be accomplished by calculating a roundtrip write-to-read latency based on generating a write signal and receiving a read signal approximately simultaneously. The read signal may be based on a coupling between a write element and read element. A device setting may then be adjusted based on the calculated roundtrip write-to-read latency. Further, a read/write mechanism that is used to write user data to and read user data from a data storage medium may be used to determine the roundtrip write-to-read latency. Even further, the roundtrip write-to-read latency may be determined in real-time as the data storage device is in operation.

Abstract: A memory test system and a memory test method are provided. The memory test system includes a control unit, a data reading channel, a data writing channel and a test channel. The control unit generates and outputs a first read and a first write command. The data reading channel and the data writing channel coupled to the memory unit, and the control unit respectively reads data from the memory unit at a first time and writes the data back to the memory unit at a second time according to the first read command and the first write command. The test channel receives the data from the data reading channel through an input end and outputs the data back to the data writing channel through an output end after a time delay. The time delay is substantially equal to a time interval between the first time and the second time.

Abstract: A memory module for operating with a system memory controller comprises a plurality of data ports, a plurality of memory devices organized in ranks, and a plurality of data handlers. Each respective data handler is coupled to a respective set of data ports of the plurality of data ports and to a respective set of memory devices of the plurality of memory devices. Each set of memory devices include at least one memory device from each rank. In a normal mode, each respective data handler is configured to provide write data received from the system memory controller via the respective data ports to the respective set of memory devices. In a test mode, each respective data handler is configured to provide test data generated in the respective data handler to the respective set of memory devices.

Abstract: A test apparatus including a first buffer section and a second buffer section that each buffers fail data and address data; an address fail memory section that writes the fail data buffered in the first buffer section to an address of an internal memory indicated by the address data corresponding to the fail data, using an RMW process; and a control section that, in a state in which the fail data and address data output from the testing section are supplied to the first buffer section, when unused capacity of the first buffer section becomes less than or equal to a predetermined first threshold value, supplies the fail data and address data output from the testing section to the second buffer section instead of to the first buffer section.

Abstract: According to one embodiment, a semiconductor integrated circuit includes at least one memory and at least one built-in self test (BIST) circuit. In the memory, data can be stored. The BIST circuit tests the memory and includes an address generator. The address generator operates in one of a first operating mode and a second operating mode. In the first operating mode, address signals corresponding to all addresses of the memory are generated. In the second operating mode, the address signals are generated such that each bit of an address input of the memory can be one signal state of both 0 and 1 and such that different bits constitute a set of pieces of data in which the bits choose different signal states at least once.

Abstract: A system for calibrating timing for write operations between a memory controller and a memory device. During operation, the system identifies a time gap required to transition from writing data from the memory controller to the memory device to reading data from the memory device to the memory controller. The system then transmits a test data pattern to the memory device within the time gap. The system subsequently uses the received test data pattern to calibrate a phase relationship between a received timing signal and data transmitted from the memory controller to the memory device during write operations.