Abstract: A device receives test methods that include input arguments that match parameters. The test methods are used to test one or more portions of dynamically-type programming code, and the parameters define conditions for the test methods. The device receives one or more values for each of the parameters, and applies the parameters and the one or more values to different ones of the test methods. The device executes the different ones of the test methods, with the applied parameters and the applied one or more values, to generate results, and outputs or stores the results.

Abstract: An operating method of an ECC decoder includes receiving first chunk data and second chunk data from a nonvolatile memory device, the second chunk data subsequent to the first chunk data, performing error correction on the first chunk data, determining if the first chunk data includes an uncorrectable error bit and determining not to perform error correction on the second chunk data in response to the first chunk data including the uncorrectable error bit.

Abstract: A system on chip is provided which performs a built-in self-test operation using an error access pattern. The system on chip includes a master device and a slave device. A bus is configured to transfer an instruction from the master device to the slave device. A built-in instruction capture circuit is configured to receive and store the instruction. The built-in instruction capture circuit stores the instruction as the error access pattern when an error occurs in the slave device due to the instruction.

Abstract: A server stores multiple configuration data which respectively provide different functions to a test system. A tester hardware is configured to be capable of changing at least a part of its functions according to the configuration data stored in nonvolatile memory included in the tester hardware. A control program is installed on an information processing apparatus. The control program provides the information processing apparatus with (i) a function of displaying multiple configuration data candidates on a display when the test system is set up, and (ii) a function of writing the configuration data selected by the user to the nonvolatile memory of the tester hardware.

Abstract: According to one embodiment, a semiconductor integrated circuit includes memories, comparison circuits, first registers and a BIST. The comparison circuits compare output values of the memories with expected values, respectively. The first registers store comparison result data in the comparison circuits, respectively. The BIST controls tests of the memories and generates the expected values. A relief data generator generates relief data indicating the presence of a defect of each of the memories and a failure position on the basis of the comparison result data stored in a second register in the BIST. A third registers store the relief data and are smaller in number than the memories. A judgment circuit outputs a relief impossible signal when the total number of the relief data is greater the number of the third registers.

Abstract: A semiconductor memory device includes, in part, a first data I/O block and a second data I/O block. During a write operation, the first data I/O block transmits input data supplied through a first pad to a first global I/O line, and further generates a write internal signal. The second data I/O block transmits the write internal signal to a second pad in response to a monitor enable signal. During a read operation, the first data I/O block supplies data from the first global I/O line to a first pad, and further generates a read internal signal. The second data I/O block transmits the read internal signal to the second pad in response to a monitor enable signal.

Abstract: A nonvolatile memory die is tested to determine certain parameters such as read time, which are then recorded in the nonvolatile memory die. After the die is incorporated into a memory system, and firmware is downloaded, the nonvolatile memory system uses the recorded parameters to determine how to configure the memory system for operation within specified limits, such as determining how much delay to apply to read operations.

Abstract: The various embodiments described herein include circuits, methods and/or devices used to protect data in a storage device. In one aspect, a method includes performing a power fail operation on a first section of the storage device. The power fail operation includes supplying power, via an energy storage device, to the first section of the storage device, where the energy storage device is distinct from a power source used during normal operation of the storage device, and where supplying power via the energy storage device includes switching the output of the energy storage device from an output of a boost regulator to an input of the boost regulator. The power fail operation also includes performing data hardening on the first section of the storage device.

Abstract: The present technology relaxes the precision (or full data-correctness-guarantees) requirements in memory operations, such as writing or reading, of MLC memories so that an application may write and read a digital data value as an approximate value. Types of MLCs include Flash MLC and MLC Phase Change Memory (PCM) as well as other resistive technologies. Many software applications may not need the accuracy or precision typically used to store and read data values. For example, an application may render an image on a relatively low resolution display and may not need an accurate data value for each pixel. By relaxing the precision or correctness requirements is a memory operation, MLC memories may have increased performance, lifetime, density, and/or energy efficiency.

Abstract: A semiconductor memory apparatus includes a CAS latency setting circuit configured to change an initially-set CAS latency value in response to control signal pulses which are sequentially applied, during a test mode without changing settings of a mode register set during each test.

Abstract: A semiconductor device includes a plurality of memory chips and a plurality of signal selection units respectively corresponding to the plurality of memory chips, and suitable for commonly transferring test data signals from an external to a corresponding one of the plurality of memory chips during a common test mode, wherein one or more of the plurality of signal selection units may transfer the test data signals from the external to corresponding ones of the plurality of memory chips during an individual test mode, and wherein the semiconductor device may be set to the common test mode when a common test signal is enabled, and set to the individual test mode when both the common test signal and a test control signal are enabled.

Abstract: A memory device with a background built-in self-repair module (BBISRM) includes a main memory, an arbiter, and a redundant memory to repair a target memory under test (TMUT). The memory device also includes a background built-in self-test module (BBISTM) to identify portions of memory needing background built-in self-repair (BBISR). The BBISRM or the BBISTM can operate simultaneously while the memory device is operational for performing external accesses during field operation. The BBISR can detect and correct a single data bit error in the data stored in the TMUT. The arbiter configured to receive a read or write access memory request including a memory address, to determine if the memory address of the read or write access memory request matches the memory address mapped to the selected portion of the redundant memory, and to read or write data from the selected portion of the redundant memory, respectively.

Abstract: According to one embodiment, there is provided a semiconductor integrated circuit including a memory, a capture register, a writing unit, and a control unit. The memory includes a plurality of memory bit cells. The capture register stores data read out from a memory bit cell selected out of the plurality of memory bit cells. The writing unit writes relevant data according to the data stored in the capture register to the memory bit cell. The control unit reads the relevant data from the written memory bit cell, compares the relevant data according to the data stored in the capture register and the read-out relevant data, controls the capture register such that a comparison result is stored by overwriting a result as a self-test result about the written memory bit cell, and controls the writing unit such that the original data according to the read-out relevant data is rewritten to the selected memory bit cell.

Abstract: Provided is a semiconductor device including a test mode circuit capable of changing the semiconductor device into a test mode with fewer malfunctions and without providing a test terminal. The semiconductor device includes a test circuit configured to compare data of a data input terminal and a data output terminal in synchronization with clock, and control whether or not to change the semiconductor device into a test mode in accordance with a result of the comparison.

Abstract: A method of reading data from a memory device is disclosed. The method comprises accessing preexisting data from a location in the memory device in response to a read command and identifying an error in the preexisting data. The identified error is corrected for transmission as corrected data. Error information representing the identified error is stored while the preexisting data is retained in the location of the memory device in uncorrected form.

Abstract: A first bit position of a cell in solid state storage is read where a sorting bit is obtained using the read of the first bit position. A second bit position of the cell is read for a first time, including by setting a first read threshold associated with the second bit position to a first value and setting a second read threshold associated with the second bit position to a second value. The second bit position of the cell is read for a second time, including by setting the first read threshold to a third value and setting the second read threshold to a fourth value. A new value for the first read threshold and for the second read threshold is generated using the sorting bit, the first read, and the second read.

Abstract: A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable power sequencing and data hardening in a storage device. In one aspect, a method includes, in response to a first signal received by the storage device, performing a soft power fail operation on a first section of the storage device. The soft power fail operation including: (1) signaling a power fail condition to a first plurality of controllers on the storage device, where the first plurality of controllers correspond to the first section of the storage device, (2) transferring data held in volatile memory of the storage device to non-volatile memory of the storage device, and (3) removing power from the first plurality of controllers.

Abstract: An information processing apparatus includes an external tool unit configured to provide a man-machine interface to a debugging user; and a microcontroller. The microcontroller includes: a CPU section configured to execute a program as a debugging target in a response to a first clock signal, wherein a clock rate of the first clock signal is changed in response to an instruction from the CPU section; a first transmitting section configured to transmit debugging data to the external tool unit in response to the first clock signal; a second transmitting section configured to transmit the debugging data to the external tool unit in response to a second clock signal which is different from the first clock signal; and a receiving section configured to receive data transmitted from the external tool unit.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location.

Abstract: A semiconductor memory includes a read port array disposed on a first layer of a three-dimensional integrated circuit and a bit cell array disposed on a second layer of the three-dimensional integrated circuit. The second layer being vertically positioned above or below the first layer. At least one bit cell of the bit cell array is coupled to at least one read port cell of the read port array by a via extending from the first layer to the second layer.

Abstract: A memory controller includes a first error detection code generator for generating a first error detection code for data received from a host, a controller to write the data and the first error detection code to nonvolatile memory and to read the data and the first error detection code from the nonvolatile memory, an error detector to perform an error detection based on the data and the first error detection code that are read from the nonvolatile memory, a second error detection code generator to generate a second detection error code based on the data read from the nonvolatile memory, and a mismatch code generator to generate a mismatch code signaling the presence of an error in the data, wherein either the second error detection code or the mismatch code is selected based on the error detection and sent to the host.

Abstract: According to one embodiment, a memory system includes a NAND-type flash memory and a memory controller. A comparison module of the memory controller compares a first threshold voltage distribution of a first memory area with a second threshold voltage distribution of the first memory area acquired earlier than the first threshold voltage distribution, if an error is detected in data read from the first memory area. An error factor determination module of the memory controller determines a cause of the error based on the comparison result, and inhibits a data move operation of moving data of the first memory area to the second memory area based on the determination result.

Abstract: The present invention, system and method for optimized board test and configuration, comprises a method for splitting test data into dynamic and static parts, a system for optimized test access using variable-length shift register (VLSR) that uses the latter method, a system for optimized test application using VLSR with accumulating buffer (VLSRB) and a method for switching between BS-based test and VLSR/VLSRB-based test.

Abstract: A device is described for forming a signature from an input signal (input). According to the present invention, a plurality of transformation elements is provided, each having a finite-state machine, to which, on the input end, in each case the input signal (input) and/or a signal (input?), that is a function of the input signal, is able to be fed, all the finite-state machines are similar and are configured in such a way, particularly able to be initialized, that each finite-state machine always respectively has a different state than do all the other finite-state machines, and the signature is formable as a function of state data of at least one finite-state machine.

Abstract: The present disclosure includes apparatuses and methods for continuous adjusting of sensing voltages. A number of embodiments include continuously monitoring an error rate associated with sense operations performed on a group of memory cells, and continuously adjusting a sensing voltage used to determine a state of the memory cells of the group based, at least partially, on the error rate.

Abstract: Devices, circuits, and methods for data mask and data bit inversion encoding and decoding for a memory circuit. According to these methods and circuits, the number of data lines/pins required to encode data mask information and data bit inversion information can be reduced. In an embodiment the data mask and data inversion functions for a portion of data, such as a data word, can be merged onto a common pin/data line. In other embodiments, a data mask instruction can be conveyed through a transmitted data word itself without using any extra pins. According to these embodiments, the pin overhead can be reduced from two pins per byte to one pin per byte.

Abstract: An apparatus includes a plurality of magnetic read/write heads, a system controller and a switching network. Each of the magnetic read/write heads includes a read sensor element configured to perform a read operation and a write element configured to perform a write operation. The switching network is coupled between the plurality of magnetic read/write heads and the controller. Further, the switching network is configured to substantially simultaneously select elements from at least two of the plurality of magnetic read/write heads in response to a command from the controller such that the operations of the selected elements are performed substantially simultaneously to establish a manufacturing parameter of a disk drive.

Abstract: A semiconductor device includes non-volatile registers, each including a holding circuit to hold data in a volatile manner and a non-volatile element. An address is allocated to each of the non-volatile registers. A non-volatile register control circuit performs control such that, in response to a write instruction, data held in the holding circuit is written to the non-volatile element in the non-volatile register having the address specified by the instruction and in response to a load instruction, data held in the non-volatile element is held in the holding circuit in the non-volatile register having the address specified by the instruction.

Abstract: Integrated circuits with memory error detection and correction (EDC) circuitry are provided. The EDC circuitry may include first and second data registers and a comparator. The first data register may store data read from a selected frame. The second data register may be loaded with a predetermined bit stream. If a soft error is detected, correct bits generated using a logic function associated with the predetermined bit stream may be written back to the selected frame. In another suitable arrangement, the EDC circuitry may include first and second registers, a mask register, and a comparator. The first data register may store data read from a selected frame. The second data register may be loaded with desired data. The mask register may be loaded with mask bits. If a soft error is detected, the correct bits may be written back to the selected frame if the corresponding mask bits are high.

Abstract: An interface comprising a single data connection, arranged to transfer data between the user equipment and an identity module. The data transferred over the interface may be arranged to be synchronized by at least one clock signal. The data transferred over the interface may comprise universal serial bus protocol data.

Abstract: A method is provided for accessing a memory device. The method includes programming data in a plurality of cells of the memory device in a first programming operation. The first programming operation uses a first memory instruction including at least one first parameter representative of at least one first threshold voltage value for said programming. The method further includes re-programming at least a portion of the data in the plurality of cells in a second programming operation. The second programming operation uses a second memory instruction including at least one second parameter representative of at least one second threshold voltage value for said re-programming, wherein said re-programming provides bit manipulation of the portion of the data.

Abstract: An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns.

Abstract: A method of operating a semiconductor memory device according to an aspect of the present disclosure includes performing a program loop, including a program operation and a program verification operation, in order to store input data in selected memory cells, performing a first error bit check operation for comparing the number of error bits of data not identical with the input data, with the number of correctable error bits, if the number of error bits is equal to or smaller than the number of correctable error bits, performing a second error bit check operation for comparing the number of error bits with the reference number of bits for replacement determination, and if the number of error bits is greater than the reference number of bits for replacement determination, updating failed column address information by adding the column address of a memory cell, having the error bits, to the failed column address information.

Abstract: A transmitting device includes a parallel data generation unit and a transmitting unit. The parallel data generation unit generates first serial data and second serial data from a data packet, converts the first serial data and second serial data respectively into first parallel data and second parallel data, transmits the first parallel data and second parallel data respectively through first and second parallel transmission paths, and performs the transmission of the first parallel data and the transmission of the second parallel data in parallel. The transmitting unit receives the first parallel data and second parallel data respectively through the first and second parallel transmission paths, re-converts the first parallel data and second parallel data respectively into the first serial data and second serial data, and transmits the first serial data and second serial data to a receiving device respectively through first and second serial transmission paths.

Abstract: According to one embodiment, a test method for testing a nonvolatile semiconductor memory including first and second areas includes performing first to sixth processes every block included in the first area. The first process performs block erase. The second process writes data to a first block. The third process reads data from first pages except a second page in the first block. The fourth process reads data from the second page. The fifth process records an event of a first read error in the second area when a read error happens in the third process. The sixth process records an event of a second read error in the second area when a read error happens in the fourth process.

Abstract: Embodiments herein provide data recovery techniques and configurations for solid state memory devices. For example, a method includes identifying a hard error associated with a cell of a solid state memory device, providing a location of the cell having the identified hard error to a decoder to recover data originally programmed to the cell, and recovering the data originally programmed to the cell using the decoder. Other embodiments may be described and/or claimed.

Abstract: A method for identifying non stuck-at faults in a read-only memory (ROM) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell, generating a test reading of the victim cell in response to the provided fault-specific pattern, and determining whether the ROM has at least one non stuck-at fault. The determination is based on a comparison of the golden value and the test reading of the victim cell.

Abstract: A memory test device for testing a memory device is provided. The memory test device includes a sequencer configured to output first and second sequencer outputs that are different from each other in response to a sequencer input. A first pattern generator is configured to output a first test pattern according to the first sequencer output. A second pattern generator is configured to output a second test pattern according to the second sequencer output. A selector is coupled to the first and second pattern generators and configured to output write data according to the first test pattern and the second test pattern.

Abstract: A data storage system includes a memory circuit and a control circuit. The control circuit is operable to receive data bits provided for storage in memory cells of the memory circuit. The control circuit is operable to compare each of the data bits provided for storage in a corresponding one of the memory cells having a stuck-at fault value to the stuck-at fault value. The control circuit is operable to generate encoded data bits by inverting each of the data bits having a different value than the stuck-at fault value of the corresponding one of the memory cells and by maintaining a digital value of each of the data bits having the stuck-at fault value of the corresponding one of the memory cells. The control circuit is operable to prevent any of the data bits from being stored in the memory cells determined to have unstable values. The control circuit is operable to generate redundant bits that indicate at least one operation to perform on the encoded data bits to regenerate the data bits.

Abstract: A method of correcting stored data includes reading data stored in a portion of a nonvolatile memory. The method includes, for each particular bit position of the read data, updating a count of data error instances associated with the particular bit position in response to detecting that the read data differs from a corresponding reference value of the particular bit position. The reading of the first portion and the updating of the counts of data error instances are performed for a particular number of repetitions. The method includes identifying each bit position having an associated count of data error instances equal to the particular number of repetitions as a recurring error bit position.

Abstract: Memory devices storing particular data, systems containing such memory devices and methods of testing such memory devices. The memory devices include an array of memory cells containing particular data, and control circuitry configured to control operations of the array of memory cells.

Abstract: A method of testing the operational margin of an information storage device having marked random variations, and an information storage device having the function of self-diagnosing the operational margin, are provided. The test method includes testing an information storage device including a plurality of memory bits as the test condition is set so as to be outside a range of conditions that may be presupposed in real use of the information storage device and of counting the number of memory bits that fail in operation. The test method also includes verifying the size of the operational margin of the information storage device based on the count value. The test condition is made severe and the reference value is set to a fairly large value to enable the operational margin against the noise to be tested highly accurately.

Abstract: A method of detecting uninitialized memory reads is shown where either all or a subset of a random access memory system is initialized to a know value. One or more watch points are implemented where after a memory read is detected the value read is compared to the value written during initialization. If the values match debug information is captured and appropriate corrective action is taken.

Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for n-channel transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, static noise margin and writeability (Vtrip) screens are provided. Each of the n-channel transistors in the CMOS SRAM cells are formed within p-wells that are isolated from p-type semiconductor material in peripheral circuitry of the memory and other functions in the integrated circuit. Forward and reverse body node bias voltages are applied to the isolated p-wells of the SRAM cells under test to determine whether such operations as read disturb, or write cycles, disrupt the cells under such bias. Cells that are vulnerable to threshold voltage shift over time can thus be identified.

Abstract: A method of testing a semiconductor memory includes generating a logical value of a test pattern through an algorithm pattern generator included in a field programmable gate array. The generated logical value is programmed in a DUT under the control of a DQ signal responding to a DQ enable signal that is generated from automatic test equipment and is then transferred to the field programmable gate array. The programmed logical value is captured from the DUT under the control the DQ signal. The generated logical value is compared with the captured logical value. Whether the DUT is defective is determined according to a result of the comparison. The DQ enable signal is applied to a time point different from a time point when a SYNC clock for synchronizing the automatic test equipment with the field programmable gate array is applied.

Abstract: In accordance with an exemplary embodiment of the present invention, a method for measuring a quality parameter of an optical storage system comprising a non-diffraction-limited optical storage medium and a readout device, the method comprising the process of deriving an impulse response of the optical storage system, and the process of analyzing the impulse response to determine at least one of a width of the impulse response and a skewness of the impulse response as the quality parameter.

Abstract: A method for controlling access operations of a flash memory includes: receiving first source data from a host; generating a plurality of first scrambled signals according to a plurality of pseudo random sequences and the first source data; obtaining a plurality of transmission powers of the first scrambled signals; and selecting a target scrambled signal from the first scrambled signals according to the transmission powers for storing to the flash memory. An associated flash memory device and an associated flash memory controller are also provided.

Abstract: In some embodiments, a non-volatile memory device comprises an error correction component to re-program at least a portion of a non-volatile memory array at least in part in response to detection of one or more heat events and detection of one or more errors in contents of the at least a portion of the non-volatile memory array.

Abstract: A circuit arrangement for detecting memory errors is provided. The circuit arrangement comprises a memory (11) and an error detection circuit (12). The circuit arrangement is designed to store a code word of an error detection code (C) or a code word that is inverted in a subset (M) of bits in the memory (11) at a memory location and to read out a data word from the memory (11) from the memory location. The error detection circuit (12) is designed, for the case where a control signal present assumes a first value, to indicate a memory error if the data word is not a code word of the error detection code (C).