Abstract: In an embodiment, a method provides an input and an expected test output for a unit test. The unit test is executed using a module under test and the input, thereby generating an actual test output. The actual and expected test outputs are serialized into XML, so that comparison and extraction of differences between actual and expected test outputs can be performed using methods for comparisons and extraction of differences between XML documents, such as XML change detection or calculation of checksums.

Abstract: A method for determining that failures in semiconductor test are due to a defect potentially causing a hold time violation in a scan cell in a scan chain, counting the number of potential defects, and, if possible, localizing, and ameliorating hold time defects in a scan chain.

Abstract: A computer program product, apparatus and method for processing a variable length device command word (DCW) at a control unit configured for communication with an input/output (I/O) subsystem in an I/O processing system. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a DCW at the control unit from the I/O subsystem. The DCW specifies one or more I/O operations and includes a command, a control data count, and control data having a varying length specified by the control data count. The control data is extracted in response to the control data count. The command is then executed in response to the extracted control data to perform the specified one or more I/O operations.

Abstract: A solution for generating functional coverage bins for testing a device is disclosed. A method includes: receiving information of a failing test generated from a random simulation performed on the device; tracing a first sequence of signal events that happened in the failing test; correlating the signal events to coverage bins to generate a sequence of coverage bins; creating cross coverage event sequence bins based on the sequence of coverage bins; and outputting the created coverage event sequence bins for testing the device.

Abstract: A method for testing a random-access memory (RAM) includes six tests. The first test is performed by performing a write and read test to storage locations of the RAM. The second test is performed by testing walking 1's across each data bus of the RAM. The third test is performed by testing walking 0's across the data bus of the RAM. The fourth test is performed by testing walking 1's across each address bus of the RAM. The fifth test is performed by testing walking 0's across the address bus bit of the RAM. The sixth test is performed by performing a write and read test to random blocks in the storage locations of the RAM.

Abstract: A semiconductor integrated circuit is configured to test a high-speed memory at the actual operation speed of the memory, even when the operation speed of the built-in self-test circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the integrated circuit is provided with a first test pattern generation section, operating on a second clock, for generating test data, and a second test pattern generation section, operating on a third clock, the inverted clock of the second clock, for generating test data. Furthermore, the integrated circuit is provided with a test data selection section for selectively outputting either the test data output from the first test pattern generation section or the test data output from the second test pattern generation section depending on the signal value of the second clock, thereby inputting the test data to the memory as test data.

Abstract: A semiconductor memory device, having a test mode and a normal mode, includes a frequency multiplier and a test command sequence generator. The frequency multiplier receives a test clock signal in the test mode and generates multiple internal test clock signals, each of which has a frequency equal to a frequency of an operation clock signal in the normal mode. The test clock signal has a frequency lower than the frequency of the operation clock signal. The test command sequence generator generates at least one command signal in response to the internal test clock signals in the test mode. The at least one command signal corresponds to at least one operation timing parameter of the semiconductor memory device that is to be measured. The frequency multiplier may include a Phase Locked Loop (PLL) or a Delay Locked Loop (DLL).

Abstract: A method of verifying whether a recording and/or reproducing apparatus that records and/or reproduces a disc having temporary defect management area (TDMA) information properly produces the TDMA information, the method including producing TDMA information produced by performing a recording test according to a series of recording operations based on a scenario using a blank test disc as test information; and providing a result of the recording test by confirming the test information using reference test information for the recording test.

Abstract: A method and apparatus is provided for detecting random access memory (RAM) failure for data with a plurality of addresses. The method comprises generating a plurality of RAM test patterns in a predetermined order, implementing a RAM test pattern on each data address in an initial testing pass, based on the predetermined order of the RAM test patterns, rotating the RAM test patterns sequentially to prepare for a new testing pass, and implementing the RAM test patterns on different data addresses in the new testing pass. The apparatus comprises means for generating a plurality of RAM test patterns in a predetermined order, means for implementing a RAM test pattern on each data address in an initial testing pass, based on the predetermined order of the RAM test patterns, means for rotating the RAM test patterns sequentially to prepare for a new testing pass, and means for implementing the RAM test patterns on different data addresses in the new testing pass.

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Abstract: A semiconductor integrated circuit includes a memory, a BIST main circuit and a BIST sub circuit. The BIST sub circuit is to generate a row address pattern or a column address pattern of the memory and includes a boundary address generation circuit for alternately generating a top address and a bottom address of the memory for at least one of the row address pattern and the column address pattern. The BIST main circuit is provided in common with a plurality of memories and the BIST sub circuit is individually provided corresponding to the memories. The boundary address generation circuit includes a top address memory unit for storing the top address and a top/bottom address generation unit for reading out the top address and alternately outputting the top address and the bottom address.

Abstract: A modification of a predetermined, memory-size-dependant number of nonvolatile memory cells turns them into ROM cells with a fixed content pattern. Since these additional ROM cells do not require much effort during manufacturing and use only small additional space on the memory chip or the integrated circuit, but provide significant advantage for testing. When using pairs of essentially symmetrical non-volatile memory cells, each pair having a common bit line, the removal or interruption of this bitline contact may serve to impress a fixed value, e.g. a ‘0’, into this pair and vice versa. During test, a simple and therefore only minimal time requiring pattern, preferably a checkerboard pattern, is written into and read from the non-volatile memory, allowing a quick determination of the decoders' correct function.

Abstract: The sequential access memory array is able to store p words each of n bits. Such p test words each made up of n test bits are written in the memory array, the p test words are extracted sequentially and, for each current word extracted, the n test bits that compose it are compared sequentially with n respective expected data bits before extracting the next test word.

Abstract: A method of identifying race conditions in a computer program can include identifying a call to a selected function specifying a memory range. The selected function can cause data to be written to the memory range asynchronously. The method further can include spraying the memory range with a predetermined bit pattern and determining whether a detected write operation at least partially overwrites the predetermined bit pattern in the memory range. A race condition can be selectively indicated according to the determining step.

Abstract: A memory test circuit includes a counter circuit that outputs a set signal that is set to the first set value or the second set value alternately in a cycle of the clock signal, an OR circuit that calculates a logical sum of the set signal and the input signal each time when the set signal is output from the counter circuit and outputs a control signal indicating the logical sum of the set signal and the input signal, and a test pattern generation circuit that generates the test pattern for causing the memory to operate in each first cycle if a set value of the control signal is the first set value, or generates the test pattern for causing the memory to operate in each second cycle if the set value of the control signal is the second set value.

Abstract: A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined input/outputs (I/Os,) data inputs may be inverted to create a desired test pattern (such as data stripes) which are “worst case” for I/O circuitry or column stripes which are “worst case” for memory arrays. A circuit in accordance with the technique of the present invention then matches the pattern for the data out path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester.

Abstract: A method and apparatus for determining the characteristics of a communications channel within a high speed memory system includes generating a first signal having a known and repeating pattern and generating a second signal having a pseudo-random pattern. The first and second signals are combined to produce a combined signal. The combined signal is transmitted over a communications channel of a memory system and received by the memory devices of the memory system. Each memory device removes the second signal from the received combined signal to produce a received first signal. Parameters associated with transmitting and receiving may be adjusted by examining the pattern of the received first signal to determine if it has the known pattern of the first signal. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A semiconductor memory device performs a parallel bit test on a plurality of memory blocks by writing test pattern data into the plurality of memory blocks, outputting two bits from each memory block in parallel and comparing the two bits output from each memory block with each other in a first test mode, and outputting two bits from respectively different memory blocks and comparing the two bits output from the respectively different memory blocks with each other in a second test mode.

Abstract: Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication channel. A plurality of test vector patterns is generated having characteristics such that when a given test vector pattern is transmitted electrically at a transmission rate via the communication channel, the test vector pattern has a frequency content that is less than the frequency content of a high frequency test vector pattern if the high frequency test vector pattern were to be transmitted electrically at the transmission rate via the communication channel, and such that the frequency content of each test vector pattern when transmitted electrically at the transmission rate via the communication channel falls within the passband associated with the communication channel.

Abstract: A method for verifying whether a recording/reproducing apparatus properly produces disc management information and records the disc management information on a disc includes preparing a test disc; issuing reading commands to a recording/reproducing apparatus to be tested on which the test disc is loaded and verifying the disc in order to verify the reading operation; and issuing recording commands to the recording/reproducing apparatus to be tested on which the test disc is loaded and checking whether a temporary disc management area (TDMA) structure is properly updated on the disc in order to verify the modification operation.

Abstract: A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory locations in succession in the same order in which the two memory locations were written; capturing output data from the memory interface; and analyzing captured output data to determine whether said captured output data corresponds to expected data.

Abstract: Implementations of the present principles are directed to test output compaction arrangements and a methods of generating control patterns for unknown blocking. The specified bits in the control patterns, which when using linear feedback shift register (LFSR) reseeding determines control data volume and LFSR size, are preferably organized in a manner so as to balance the number of specified bits in the control patterns across test patterns.

Abstract: To copy protect an optical disc, such as a DVD, program chains additional to the main program chain are provided. These program chains may lead to the genuine data but in an incomplete or incorrect order or to false data. Sufficient additional program chains are provided to make it difficult to identify the main program chain amongst all of the program chains provided on the disc. The structure of the further program chains ape that of the main program, again to hide the main program chain. The navigation path which leads to the main program chain, and hence to the content on the DVD, is dynamically generated and at least some of the information required to generate the navigational path arises by setting parameters associated with a player or with a user. Thus a search of all of the navigation information on the disc will fail to reveal the navigation path to the content.

Abstract: A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for storing therein the data which have passed through the data input section; and a data compressor for determining whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other.

Abstract: A configurable memory architecture includes a built-in testing mechanism integrated in said memory to support very efficient built-in self-test in Random Access Memories (RAMs) with greatly reduced overhead, in terms of area and speed. Memories can fail at high speed due to glitches (unwanted pulses which can at times behave as invalid clocks and destroy the functionality of synchronous systems) produced in decoding, the slow precharge of bitlines or the slow sensing of the sense amplifiers. The memory architecture incorporates structured DFT techniques to separately detect these failures.

Abstract: A method of verifying the integrity of an arithmetic logic unit (ALU) of a control module includes inputting a first test value into one of a plurality of registers of the ALU and inputting a second test value into remaining registers of the plurality of registers. A first set of operations is performed between the one of the plurality of registers and each of the remaining registers to produce a first set of results. A fault is indicated when one of the first set of results varies from a first predetermined result.

Abstract: An input circuit of a semiconductor memory device includes a data input circuit and a data pattern setting circuit. The data input circuit receives first data, and generates second data by buffering the first data, sampling buffered first data responsive to a write data strobe (WDQS) signal, and parallelizing sampled data. The data pattern setting circuit sets a pattern of the second data responsive to a test mode signal and a data pattern select signal to generate third data. Accordingly, the semiconductor memory device including the input circuit may generate data of various patterns in a test mode, and may perform a high-speed test using a low-speed tester.

Abstract: The present invention provides a semiconductor memory device comprising a memory cell array including a plurality of memory regions, an address decoding portion for decoding an address applied from an external portion for simultaneously selecting all of the plurality of memory regions during a test read operation, a data IO control portion for receiving test pattern data and writing the test pattern data to each of the plurality of memory regions during a test write operation, and reading the test pattern data from one of the plurality of memory regions and outputting the test pattern data during the test read operation, a data IO portion for receiving the test pattern data from the external portion and applying the test pattern data to the data IO control portion during the test write operation, and receiving the test pattern data output from the data IO control portion and conditionally outputting the test pattern data as test status data to the external portion in response to an output control signal durin

Abstract: Integrated circuits, load boards and methods are disclosed, such as those associated with a memory testing system that includes an algorithmic pattern generator generating a pattern of command, address or write data digits according to an algorithm. In one such embodiment, the pattern of digits are applied to a frame generator that arranges the pattern of digits into a packet. The packet is then applied to a plurality of parallel-to-serial converters that convert the packet into a plurality of serial digits of a command/address packet or a write data packet, which are output through a plurality of bit lanes. The system might also include a plurality of serial-to-parallel converters receiving respective sets of digits of a read data packet through respective bit lanes. The read data packet is applied to a frame decomposer that extracts a pattern of read data digits from the packet. An error detecting circuit then determines if any of the received read data digits are erroneous.

Abstract: A digital test instrument and a test method provide adjustable results latency. A digital test instrument includes a pattern controller configured to generate a sequence of test patterns, responsive, at least in part, to a pass/fail result, a pattern memory configured to supply the generated sequence of test patterns to a unit under test, a pattern results collection unit configured to receive at least one result value from the unit under test and to determine a pass/fail result for at least one supplied test pattern, and a synchronization unit configured to provide a no-result indication to the pattern controller during a preset number of pattern cycles following the start of a test, the preset number of pattern cycles based on a results latency of the test instrument, and to provide pass/fail results to the pattern controller after the preset number of pattern cycles.

Abstract: We describe, in exemplary embodiments, an on-chip Functional Built-In Self Test (“FBIST”) mechanism for testing integrated circuits with internal memory state and complex transaction based interfaces. Such interfaces include system-on-chip applications, memory chip applications, and input/output (“IO”) protocol adapter chips.

Abstract: Embodiments of a scannable IO circuit featuring reduced latch count for pipelined memory architectures and test methodology are described. For a pipelined memory system performing at speed tests, the timing sequence for processing a test command comprises a precharge-read-precharge-write sequence for each clock cycle starting with the rising clock edge. The memory circuit utilizing this test command timing sequence comprises a sense amplifier and a single latch. The sense amplifier itself is used as a latch to implements scan functionality for the memory circuit. The memory device is incorporated into an integrated test wrapper circuit that executes back-to-back commands through serial compare operations using integrated scan flip-flop circuits. The test wrapper includes a fanout block and padded address scheme for testing multiple and disparate size memory devices in parallel.

Abstract: A memory device includes an ECC and test circuit. In a normal mode, the circuit performs ECC conventional functions. In a test mode, the least significant bit of received data is used to generate test data. If the received bit is “0,” the test data bits are all “0,” and if the received bit is “1,” the test data bits are all “1.” The test data bits are applied to the ECC encoder that is used in normal operation. The ECC encoder is designed so that it generates ECC bits that have the same logic level as the test data bits. The test data bits and ECC bits are then written to a memory array and subsequently read. During the test mode, a logic circuit determines if the read data and check bits are all either “0” or “1” and outputs a corresponding test result bit from the memory device.

Abstract: An ECC circuit and method for an integrated circuit memory allows a user to enter a test mode and select a specific location to force a known failure on any memory chip, whether it is fully functional or partially functional. Additional circuitry is placed in the data path where existing buffers and drivers are already located, minimizing any additional speed loss or area penalty required to implement the forced data failure. In a first general method, a logic zero is forced onto a selected data line at a given time. In a second general method, a logic one is forced onto a selected data line at a given time.

Abstract: A system and method for predicting lwarx (Load Word And Reserve Index form) and stwcx (Store Word Conditional) instruction outcome is presented. A lwarx instruction establishes a reservation on an address/granule, and a stwcx instruction targeted to the same address/granule “succeeds” only if the reservation for the granule still exists (conditional store). Since the reservation may be lost due to situations such as, for example, a processor (or another processor) executing a different lwarx or ldarx instruction (or other mechanism), which clears the first reservation and establishes a new reservation, the invention described herein builds test patterns in a manner that ensures, stwcx success and failure predictability. As a result, stwcx instructions are testable during test pattern execution.

Abstract: Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays. The memory arrays can be tested using configurable built in self test circuitry. The built in self test circuitry may have test control register circuitry and configurable state machine logic. The state machine logic may perform at-speed tests on a memory array and may provide test results to external equipment for analysis. A tester may be used to provide test control settings to the test control register circuitry. The test control settings may include march element settings for a march sequence. During testing, the configurable state machine logic may use the march element settings to generate march sequences. March sequences that have been generated in this way may be used in testing the memory array.

Abstract: A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test results or the status of the test modes are output from the chip. The method includes providing a chip having at least one first register set having a plurality of registers and at least one second register set having a plurality of registers, at least one register of the first register set and at least one register of the second register set being 1:1 logically combined with one another. A first serial bit string is stored, the bit sequence of which can be assigned to at least one test mode, in the first register set. A bit sequence is transmitted for application of the logical combination between the first register set and the second register set to the first bit string stored in the first register set. The test results are read out by means of a serial second bit string.

Abstract: Provided is a semiconductor memory device testable with a single data rate (SDR) or a dual data rate (DDR) pattern in a merged data input/output pin (DQ) test mode. The device includes a first path circuit, a second path circuit, and a merged output generator configured to generate a merged data bit having a SDR and/or DDR pattern.

Abstract: A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m register groups each having n registers, each register group respectively having only one individual register from a register set, the m register groups being uniquely identifiable using m headers; programming the m different register groups by filling them with m first bit strings, each bit string being respectively assignable to a state of n test modes; transmitting at least one header to select a register group and the state of the n test modes and executing the state of n test modes stored in the selected register group; and using a serial second bit string to read out test results or the status of the test modes.

Abstract: There is provided a test apparatus for testing a memory-under-test for storing data strings to which an error correcting code has been added, having a logical comparator for comparing each data contained in the data string read out of the memory-under-test with an expected value generated in advance, a data error counting section for counting a number of data inconsistent with the expected value, a plurality of registers, provided corresponding to each of a plurality of classes, for storing an upper limit value of a number of errors contained in the data -under-test to be classified into the class, comparing sections for comparing each of the plurality of upper limit values stored in the plurality of registers with the counted value of the data error counting section and a classifying section for classifying the memory-under-test into the class corresponding to the register storing the upper limit value which is greater than the counted value.

Abstract: A semiconductor integrated circuit has a scan path that includes, between the output of the first logic section and the input of the functional block, a parallel path and a serial shift path for serially transferring data, and that includes first selectors for connecting the output of the first logic section or the serial shift path to the input of the functional block, and flip-flops for storing the data. The semiconductor integrated circuit further includes second selectors connected into the serial shift path of the scan path, for connecting the output of the functional block or the serial shift path to the input of the second logic section. Test data is provided from the serial shift path of the scan path to the functional block via the second selectors, and data output from the functional block is output via the second selectors after switching the second selectors.

Abstract: A semiconductor memory device to which information of different data bits can be written, and a method of electrically testing the semiconductor memory device are provided. In a mode for testing a memory cell array of the semiconductor memory device, the semiconductor memory comprises a control signal generation pad capable of writing non-identical data to data input/output pads of each group when data is written to the memory cell array.

Abstract: In relation to the built-in self-test circuit (BIST circuit) for testing CAM macros, the present invention is intended to provide a means to enable reduction in amount of materials as required for wiring channel region for signal distribution, buffer, FF, etc., and in number of LSI pins, and further, to facilitate mounting on chips. The data generators for CAM testing, inserted between the APG for RAMs and CAM macros, create data to write to the CAM macros by obtaining the address signals directly or by decoding the same signals. The APG is common to all the memory macros, and testing proper to each CAM can be carried out by changing over the operation of the inserted data generators by means of the control signal. The data generators are arranged in the proximity of the CAM macros, the circuits to be tested.

Abstract: Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing.

Abstract: The invention relates to a semi-conductor component test procedure, and a semiconductor component test device (10b), which comprise: a device (43) for generating pseudo-random address values to be applied to corresponding address inputs of a semi-conductor component (2b), in particular a memory component, to be tested.

Abstract: A magnetic recording device comprising a magnetic recording medium, a read-write channel for modulating write data, writing it on the magnetic recording medium, reading data from the magnetic recording medium, and demodulating the read data, and a processor for supplying the write data to the read-write channel and being supplied with the read data from the read-write channel. The processor supplies to the read-write channel a microdefect detection pattern having a first pattern for generating a consecutive magnetization inversion during writing and a second pattern for generating, during reading, a signal having a S/N ratio higher than the signal produced by the first pattern, the read-write channel modulates the microdefect detection pattern, writes it to the magnetic recording medium, reads the microdefect detection pattern, which was written, from the magnetic recording medium, and conducts abnormality detection of the microdefect detection pattern, which was read out.

Abstract: The invention relates to a semi-conductor component test procedure, as well as to a semi-conductor component test device with a shift register, which comprises several memory devices from which pseudo-random values (BLA, COL, ROW) to be used for testing a semi-conductor component are able to be tapped and emitted at corresponding outputs of the semi-conductor component test device, whereby the shift register comprises at least one further memory device, from which a further pseudo-random value (VAR) is able to be tapped and whereby a device is provided, with which the further pseudo-random value (VAR) can selectively, if needed, be emitted at at least one corresponding further output of the semi-conductor component test device.

Abstract: Method and system for repairing memory failure in a computer system in one aspect determines one or more test patterns and time duration for testing the new memory unit that replaced a failed memory unit. The test pattern is written to the new memory unit and read from the new memory unit. The read pattern is compared to the test pattern that was used to write. If the read test pattern and the written test pattern doe not match, a further repair action is taken. If they match, writing and reading of the test pattern repeats until the time duration for testing expires. The new memory unit may be configured as available for use when the write and read test completes successfully for the testing time duration.

Abstract: A method according to one embodiment may include receiving a write request to write data in a local storage device. The method of this embodiment may also include detecting a write error in the local storage device. The method of this embodiment may also include reserving a reserved area in the local storage device and remapping the data corresponding to the write error to the reserved area of the local storage device. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A memory test circuit receives test pattern data from a processing unit having a first data width, expands the test pattern to a second data width greater than the first data width, and writes the expanded test pattern data into a memory having the second data width, thereby avoiding the need for extra write cycles when a processing unit tests a memory having a greater data width. The test pattern data may be expanded by, for example, copying a specific bit to multiple bit positions, inverting a specific bit and copying the inverted bit to multiple bit positions, or performing arithmetic operations that generate a test pattern similar to the test pattern received from the processing unit.