Abstract: A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for storing therein the data which have passed through the data input section; and a data compressor for determining whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other.

Abstract: A memory system with transparent error correction circuitry provides full stuck-at fault coverage for both test data patterns and the corresponding error correction code (ECC) values. The memory system includes a semiconductor memory having a memory array, a memory interface and an error detection/correction unit. The memory array is configured to store test data patterns and corresponding error correction code (ECC) values. The memory interface is configured such that the ECC values are not directly accessible. The error detection/correction unit is configured to correct single-bit errors in the test data patterns and corresponding ECC values. A set of test data patterns associated with the semiconductor memory is selected such that any multiple-bit error in a test data pattern and the corresponding ECC value causes the error detection/correction unit to provide an output data pattern having an error, thereby rendering multiple-bit faults 100% detectable.

Abstract: A semiconductor integrated circuit includes a memory, a BIST main circuit and a BIST sub circuit. The BIST sub circuit is to generate a row address pattern or a column address pattern of the memory and includes a boundary address generation circuit for alternately generating a top address and a bottom address of the memory for at least one of the row address pattern and the column address pattern. The BIST main circuit is provided in common with a plurality of memories and the BIST sub circuit is individually provided corresponding to the memories. The boundary address generation circuit includes a top address memory unit for storing the top address and a top/bottom address generation unit for reading out the top address and alternately outputting the top address and the bottom address.

Abstract: A method and apparatus for determining the characteristics of a communications channel within a high speed memory system includes generating a first signal having a known and repeating pattern and generating a second signal having a pseudo-random pattern. The first and second signals are combined to produce a combined signal. The combined signal is transmitted over a communications channel of a memory system and is received by the memory devices of the memory system. Each memory device removes the second signal from the received combined signal to produce a received first signal. Parameters associated with transmitting and receiving may be adjusted by examining the pattern of the received first signal to determine if it has the known pattern of the first signal. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: Memory testing at system startup, such as boot POST, of an information handling system is accelerated by adjusting memory testing routines to use instructions that take advantage of optimizations made to information handling system and CPU architectures. For instance, memory test iterations in one Mbyte portions using 128-bit SIMD registers, 64-bit MMX registers, ADD and SUB instructions, the MOVNTDQ instruction, and relying on an initial setting of the gate A20 and protected mode result in a substantially accelerated memory test.

Abstract: A method (200) for determining various bit failure modes in a static random access memory device. A hard/soft bit failure test sequence is performed on each cell of the memory device to determine whether the cell exhibits a hard bit failure or a soft bit failure, then a data retention test is performed on the cell having soft bit failure to determine whether the cell exhibits a data retention failure. A write or disturb test sequence is then performed on the cell not having data retention failure, and a read or disturb test sequence is performed on the cell having write or disturb failure. Finally, a disturb test sequence is performed on the cell having read or disturb failure, and then an analysis is performed on the data from the tests to determine whether the cell exhibits one of a write, read, or disturb failure.

Abstract: This invention uniquely partitions the pBIST ROM for storing program and data information. The pBIST unit selectively loads both the algorithm and data, the algorithm only or the data only for each test set stored in the pBIST ROM into read/write registers. These registers are memory mapped readable/writable. A configuration register has an algorithm bit and a data bit which determines whether the corresponding algorithm or data is loaded from the pBIST ROM. The pBIST unit includes another configuration register having one bit corresponding to each possible test set stored in the pBIST ROM. The pBIST unit runs a test set if the corresponding bit in the configuration register has a first digital state.

Abstract: According to one exemplary embodiment, a method for isolating a failure site in a leaky wordline in a memory array includes dividing said leaky wordline into an initial leaky wordline portion and an initial non-leaky wordline portion, where the initial leaky wordline portion has wordline-to-substrate leakage. The initial leaky wordline portion can be determined by using a passive voltage contrast procedure to illuminate the initial leaky wordline portion. The method further includes performing a number of division and identification cycles on the initial leaky wordline portion to determine a final leaky wordline portion. According to this exemplary embodiment, the final leaky wordline portion comprises a predetermined number of memory cells. The method further includes performing a cutting and imaging procedure on the final leaky wordline portion to isolate the failure site.

Abstract: A semiconductor memory device performs a parallel bit test on a plurality of memory blocks by writing test pattern data into the plurality of memory blocks, outputting two bits from each memory block in parallel and comparing the two bits output from each memory block with each other in a first test mode, and outputting two bits from respectively different memory blocks and comparing the two bits output from the respectively different memory blocks with each other in a second test mode.

Abstract: A timing generation circuit can increase a maximum delay amount without changing the configuration of a timing memory. The timing generation circuit includes: a timing memory (TMM) 10 containing predetermined timing data; a plurality of down counters 20 for loading the timing data from the TMM and outputting a pulse signal at the timing indicated by the timing data; an address selection circuit 40 for specifying one or two TMM addresses by switching and outputting corresponding one or plural timing data; a load data switching circuit 50 for loading the plural timing data to the plural down counters cascaded and outputting one timing pulse signal; and a timing data selection circuit 60 for selecting one of the pulse signals. The plural timing data are generated by dividing the timing memory into a plurality of memory regions either in a column or row direction.

Abstract: A method and apparatus for burn-in of semiconductor devices is disclosed. A semiconductor device that includes built-in self test circuitry is coupled to a socket on a burn-in board. The burn in board and the semiconductor device are heated. Burn-in instructions can be transmitted to the semiconductor device through a JTAG terminal of the semiconductor device. Upon receiving a burn-in instruction through a JTAG terminal, the built-in self test circuitry is operable to perform one or more burn-in function. This allows for burn-in of a semiconductor device without any transfer of data through the data input terminals of the semiconductor device.

Abstract: A self-test controller 10 is responsive to scanned in self-test instructions to carry out test operations including generating a sequence of memory addresses that is specified by the self-test instruction. Combining multiple such self-test instructions allows a custom test methodology to be built up by a user using a generic self-test controller 10.

Abstract: A semiconductor memory device includes a mode setting register for generating a parallel bit test signal and a code according to an externally applied mode setting register code in response to a mode setting command; a data input circuit for receiving and outputting at least one bit of externally applied data in response to a write command; and a test pattern data generating circuit for receiving the parallel bit test signal and a predetermined bit from the code to generate a test pattern data in response to the at least one bit of externally applied data received from the data input circuit.

Abstract: Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data compression test mode, reading one word of an output page provides an indication of the data values of the remaining words of the output page. The time necessary to read and verify a repeating test pattern can be reduced as only one word of each output page need be read to determine the ability of the memory device to accurately write and store data values. The memory devices include data compression circuits to compare data values for each bit location of each word of the output page. Output is selectively disabled if a bit location for one word of the output page has a data value differing from any remaining word of the output page.

Abstract: A procedure is provided for identifying an operating mode of a device, such as an EEPROM memory that communicates according to a communication protocol, such as “I2C” (Inter Integrated Circuit). The signal is an “ACK” or “ACKNOWLEDGE” signal. At least one operating mode of a device is identified by a time lag from the time the signal (ACK) is transmitted relative to the time foreseen by the protocol for the signal. This approach can be used to verify that the test mode commands (read or write) have been taken into account correctly.

Abstract: A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a data table for generating a random pattern is provided in the testing circuit so that a test using a test pattern having no regularity is performed using the data table in addition to a test using a test pattern having regularity generated by the ALPG.

Abstract: There are provided an apparatus and method for testing semiconductor memory devices, in which the frequencies of test pattern signals can be selectively changed. The test apparatus includes a main tester, an input frequency converter, and an output frequency converter. The main tester generates first input test signals with a first frequency, a first program control signal, and a second program control signal, receives first output test pattern signals with the first frequency, and determines an operating performance of a semiconductor memory device. The input frequency converter converts the first input test pattern signals into second input test pattern signals with a second frequency in response to the first program control signal, and applies the second input test pattern signals to the semiconductor memory device.

Abstract: A method for testing an CMOS ternary content addressable memory (TCAM) device includes a match line test to identify stuck match lines, a pull down test to identify weak pull downs (from the match line to ground), and a row-by-row match test. During the row-by-row match test a failed cell can be repaired or the row associated with the failed cell can be disabled. A failed cell or its associated row can also be repaired or disabled, respectively, after the test. Additionally, individual CAM cells which are identified as being defective can be further tested to identify which component of the CAM cell failed.

Abstract: The present invention relates to a memory interlace-checking method and, in particular, to a test method that can effectively detect the weakening of memory. This test method is different from the conventional continuous address testing style. It is an interlacing address test method that comprises a main step and a data checking step. The main step provides main data to perform command actions on local addresses in memory. This will weaken other portions in the memory that are not trigged by commands because of the electromagnetic interference (EMI) induced by memory operations. Afterwards, in the data checking step, the yet to be triggered portion will be checked in a complementary way in order to accurately detect weakened memory.

Abstract: Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data compression test mode, reading one word of an output page provides an indication of the data values of the remaining words of the output page. The time necessary to read and verify a repeating test pattern can be reduced as only one word of each output page need be read to determine the ability of the memory device to accurately write and store data values. The memory devices include data compression circuits to compare data values for each bit location of each word of the output page. Output is selectively disabled if a bit location for one word of the output page has a data value differing from any remaining word of the output page.

Abstract: A method of testing an embedded memory at speed within an integrated circuit which includes providing a memory built in self test sequencer module, providing a satellite engine module coupled to the memory built in self test sequencer module and applying a march test to the embedded memory via the satellite engine module based upon information stored within the instruction buffer. The satellite engine module includes an instruction buffer and a sequence generation engine.

Abstract: A method of testing write enable lines of random access memory having at least one word having one or more write enable inputs for controlling write operations in the word, comprises, for a selected memory address, shifting a series of test bits through an addressed word via a first data input to the word, and for each test bit, performing a write operation to the word using a write enable test input derived from data outputs of the word or from a test write enable signal applied concurrently to each write enable input; and, after each write operation, comparing a last bit of the word against an expected value to determine whether there exists a defect in a write enable line.

Abstract: In a method of testing a multi-port memory in accordance with a test pattern, test clock signals having the same test clock frequency but with different delay periods introduced therein are generated for controlling memory access through the different access ports of the memory. Consecutive memory operations of a test element of the test pattern are then conducted in a folded sequence upon a memory cell through the different access ports in accordance with the test clock signals such that the memory operations are completed within the same test clock cycle of the test element.

Abstract: A method and system of testing data retention of memory is provided. An embodiment of the method of testing data retention of memory comprises: writing first data to a first memory sub-group during a first time period; writing second data to a second memory sub-group during a second time period subsequent to said first time period; pausing for a predetermined time interval during a third time period subsequent to said second time period; reading a first one of said first and second data during a fourth time period subsequent to said third time period; reading a second one of said first and second data during a fifth time period subsequent to said fourth time period; and comparing said first and second ones of read data to expected results to determine data retention capabilities of said first and second memory sub-groups.

Abstract: Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data compression test mode, reading one word of an output page provides an indication of the data values of the remaining words of the output page. The time necessary to read and verify a repeating test pattern can be reduced as only one word of each output page need be read to determine the ability of the memory device to accurately write and store data values. The memory devices include data compression circuits to compare data values for each bit location of each word of the output page. Output is selectively disabled if a bit location for one word of the output page has a data value differing from any remaining word of the output page.

Abstract: A method of safeguarding program parts which are critical to safety against inadvertent execution is described. In this method, at least one program part is executed in a predetermined chronological sequence. At a certain time in the execution, a pattern is generated. At least at one later time, a check is then performed to determine whether the pattern is present. If the pattern is not present, the execution of the respective program part is terminated. A memory device for executing such a method is also described.

Abstract: Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated from the captured first group. A second group of applied data signals is then captured and determined to have been properly captured when the second group corresponds to the group of expect data signals. In this way, when a captured series of data signals is shifted in time from an expected capture point, subsequent captured data signals are compared to their correct expected data signals in order to determine whether that group, although shifted in time, was nonetheless correctly captured. A pattern generator generates expect data signals in this manner, and may be utilized in a variety of integrated circuits, such as an SLDRAMs.

Abstract: A method, computer program product and system for testing stuck-at-faults. A first register may be loaded with a first value where the first value may be written into each entry in a memory array. A second register may be loaded with a second value. A third register may be loaded with either the second value or a third value. The second and third values are pre-selected to test selector circuits for stuck-at-faults with a pattern where the pattern includes a set of bits to be inputted to selector circuits and a set of bits to be stored in the memory cells. A value stored in the n-most significant bits in both the second and third registers may be predecoded to produce a predecode value. The predecode value may be compared with the value stored in the n-most significant bits in an entry in the memory array to determine a stuck-at-fault.

Abstract: The present invention discloses a diagonal testing method for flash memories. The testing method regards the flash memory as several squares, and executes in the direction from top to bottom and from left to right. Each square is provided with a first diagonal in ?45 degrees from the upper left to the lower right, and a second diagonal in +45 degrees from the lower left to the upper right. The present invention is to program the cells in the first diagonal or the second diagonal, and then read the cells except the first diagonal or the second diagonal; or, program the cells except the first diagonal or the second diagonal, and then read the cells in the first diagonal or the second diagonal so as to detect the disturb fault in the flash memories and normal memory fault models.

Abstract: When a program is activated, data recorded in a predetermined sector is reproduced by an error correction. When no reproduction error occurs, the data in the predetermined sector is reproduced without conducting the error correction. When reproduced data are not a predetermined pattern, it is determined that write software illegally writes dummy data to the predetermined sector, instead of the predetermined pattern, and an optical disc where the program is activated is a copied optical disc. Accordingly, a process conducted by the program is terminated. Therefore, a process realizing original functions based on the program cannot be executed.

Abstract: A semiconductor test data analysis system (1) automatically recording, during an analysis operation, operation information of the analysis operation, including analysis conditions or an analysis procedure for input test data, or analysis information obtained by the analysis operation. The analysis system includes a processing means (101), an analysis target data storage means (109), which stores the test data as analysis target data, a historical data storage means (107), which stores as historical data either operation information of the analysis operation or analysis information obtained by the analysis operation, and a display data storage means (112), which stores analysis information obtained by the analysis operation, which stores analysis display data generated by the processing means for the purpose of displaying the analysis information obtained by the analysis operation.

Abstract: The present invention provides a method and apparatus configured to allow testing of interconnections between components in a system. The present invention utilizes a source of a known pattern, for example a pattern buffer, in a first component of the system and a capture buffer located in a second component of the system.

Abstract: A semiconductor device manufacturing process which includes a test process that minimizes the test time for a single wafer, reduces the test cost and improves the throughput. The test system is made up of a wafer which includes plural chips formed with flash memories, a wafer level whole-surface contact device for contact with the whole surface of the wafer, a tester for testing electric characteristics of the wafer, and a BOST board interposed between the tester and the wafer level whole-surface contact device and with chip-by-chip control circuits mounted thereon. Where the test time differs depending on each chip in the wafer, the BOST board controls each test item for each chip so that in a parallel manner for the chips, upon completion of a preceding test, a shift is made to the next test.

Abstract: A method and arrangement is provided for testing memory external to a network switch and a memory interface bus connecting the external memory to the network switch. The method includes writing, via the memory interface bus and on a per-bit basis, a first prescribed logic pattern to a prescribed region of the memory to check for one of a bus short to ground and a short between adjacent pins of the memory. The first prescribed logic pattern is read to verify operation of the prescribed region of the memory. The method includes writing, via the memory interface bus and on a per-bit basis, a second prescribed logic pattern, complementary to the first prescribed logic pattern, to a prescribed region of the memory to check for one of a bus short to power and a short between adjacent pins of the memory. The second prescribed logic pattern is read to verify operation of the prescribed region of the memory.

Abstract: The present invention provides an improved method, an system, and a set of computer implemented instructions for handling a cache containing multiple single-bit hard errors on multiple addresses within a data processing system. Such handles will prevent any down time by logging in the parts to be replaced by an operator when certain level of bit errors is reached. When a hard error exists on a cache address for the first time, serviceable first hard error, that cache line is deleted. Thus the damaged memory device is no longer used by the system. As a result, the system is running with “N?x” lines wherein “N” constitutes the total number of existing lines and “x” is less than “N”. An alternative method is to exchange the damaged memory device to a spare memory device. In order to provide such services, the system must first differentiate whether an error is a soft or hard error.

Abstract: 32 pseudo-random numbers respectively indicated by 5 bits are successively generated in a test address generating unit, a serial output signal denoting one pair of pseudo-random numbers of 10 bits are input to 10 flip-flops serially arranged in an address shift register for each clock cycle, a read address expressed by a string of bits output from the flip-flops of odd-numbered stages is input to a read port of a RAM to perform a read test for one memory cell of the read address, and a write address expressed by a string of bits output from the flip-flops of even-numbered stages is input to a write port of the RAM to perform a write test for one memory cell of the write address. The read test and the write test for 32 memory cells are alternately performed in 64 clock cycles.

Abstract: In an ECC circuit of an ECC circuit-containing semiconductor memory device, an error correcting code/syndrome generating circuit and a data correcting circuit are disposed. In portions of the ECC circuit connected to buses, a data bus input control circuit for controlling input of a data from a data bus; an error correcting code bus input control circuit for controlling input of an error correcting code from an error correcting code bus; and an error correcting code bus output control circuit for controlling output of an error correcting code to the error correcting code bus are disposed. A portion corresponding to an error correcting code generator of a conventional technique is included in the ECC circuit, so that the ECC circuit can function both as an error correcting code generator and a decoder. As a result, the entire device can be made compact.

Abstract: A pattern generator for semiconductor test system for testing a semiconductor memory device by generating and applying test patterns. The pattern generator is capable of freely generating inversion request signals for inverting the read/write data for specified memory cells for a memory device under test having different total numbers of memory cells between X (row) and Y (column) directions. The locations of specified memory cells are on a diagonal line on an array of memory cells in the memory device under test or on a reverse diagonal line which is perpendicular to the diagonal line.

Abstract: Provided are a device, method and storage medium, which, when a memory LSI defect analysis apparatus is used as a monitoring device to estimate reductions in yield, automatically interprets results, and calculates the period of distribution patterns and the mix rate of regular patterned defects. The total defect number of bits is found, and the factor f, is selected. The value of expected value functions, T(f), for the selected f is found, and if it is decided that regularly patterned defects are included, then regular pattern defect mix rate function MR(f) is calculated from number of bits, factor f, and the value of estimated value function T(f). If it is decided that it does not contain regularly patterned defects the regular patterned defect mix rate function MR(f) is assumed to be zero; and it is confirmed whether or not MR(f) has been found for every f.

Abstract: A system for analyzing bitmap test data includes a fault shape analyzer which continuously and automatically receives bitmap test data. In use, the user creates at least one failure pattern analysis order to be performed by the fault shape analyzer, the order specifying a particular failure pattern to be identified. Based on the order, the fault shape analyzer creates a bitmap display of a user-specified sector using selected bitmap test data. The fault shape analyzer identifies the user-specified failure pattern in the bitmap display by multiplying, at various locations, the bitmap display in the frequency domain and the failure pattern in the frequency domain. A comparison between the product of the multiplication process and the failure pattern is performed to locate failure patterns in the bitmap display. Failure patterns identified from the comparison process are saved as defect files which, in turn, are stored in a failure pattern classification database.

Abstract: A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a data table for generating a random pattern is provided in the testing circuit so that a test using a test pattern having no regularity is performed using the data table in addition to a test using a test pattern having regularity generated by the ALPG.

Abstract: A clock signal driven device has a clock pin for receiving an externally generated clock signal during normal operation. Internal circuitry coupled to the clock pin is responsive to the externally generated clock signal during normal operation. The device also has a clock source, such as a PLL, that provides an internal clock signal, and an internal clock generator that during a test mode of operation generates from the internal clock signal and asserts on the clock pin a test clock signal. The test clock signal has substantially similar signal characteristics to predefined signal characteristics of the externally generated clock signal. The device's internal circuitry is responsive to the test clock signal during the test mode of operation.

Abstract: Synchronous dynamic random access memory (SDRAM) method and apparatus are provided for implementing address error detection. Addressing errors are detected on the memory interface independent of data ECC, with reduced memory read access latency and improved processor performance. Addressing errors are detected while allowing differentiation between memory addressing failures that are required to stop the system and memory cell failures that allow continued operation. A predefined pattern is generated for a write burst to the SDRAM. The predefined pattern is dependent on a write address. A bit of the predefined pattern is sequentially stored into the SDRAM on each burst transfer of the write burst to the SDRAM. An expected pattern is generated from a read address for a read burst. The stored predefined pattern is retrieved during a read burst. The retrieved predefined pattern is compared to the generated expected pattern for identifying a type of an addressing error.

Abstract: A method of judging whether an electronic component is good or defective in accordance with a response output signal by inputting a test signal to the IC to be tested, wherein a common test signal is input to respective electronic devices A1 and A2 of a group of electronic devices composed of a plurality of electronic devices, and in accordance with a response signal thereof, the group of electronic devices as a whole subjected to the test is judged to be good or defective. In the second test, each of the DUTs A1 and A2 of the group of electronic devices judged to be defective is input a mutually independent test signal, and in accordance with the response signal thereof, it is judged whether each of the electronic devices A1 and A2 subjected to the test is good or defective.

Abstract: One embodiment of the present invention provides a system that facilitates generating a bus testing data pattern for simultaneously testing multiple bus widths. The system first receives a list of bus widths to be tested. Next, the system receives a root test pattern with a width equal to the width of the smallest bus in the list. The system then inverts each bit of the root test pattern and concatenates this inverted pattern with the original pattern. Next, the system creates an additional pattern by repeating the second pattern sufficient times so that the width of this additional test pattern equals the width of the next larger bus. The system then creates a test pattern for the next larger bus by inverting each bit of the additional test pattern and concatenating this inverted test pattern with the additional test pattern.

Abstract: There are disclosed methods and apparatus for testing memory components for faults, defects or the like, by generating a testing sequence that produces various bit combinations as well as current changes, that when coupled, stresses or fatigues the memory component, and allows for the evaluation of single bits. The testing sequence is provided in cycles, formed of complement word pairs of N bit words. The first, or initial, cycle typically includes a first word of all binary zeros. Successive or subsequent cycles include a shifted bit in each subsequent first word. The testing pattern is written into the memory component(s) under test and corresponding words are read from the memory component(s). The written and read words are then compared, with this comparison analyzed for detection of faults, defects or the like in the memory component(s).

Abstract: Testing a memory device having M data pads with a tester having N<M data pads, comprising writing data to the memory device in a test configuration; then in a normal configuration reading the data and writing the data back to the memory device. Subsequently the memory device is configured to a test configuration and the data is read to the tester to check for error.

Abstract: The present invention provides a method for fibre channel control units to execute commands locally when a channel sends a repeat execute indicator in conjunction with certain other field settings, wherein the control unit will repeat and chain control words until certain predefined conditions occur.

Abstract: A method for interlacing digital data to reduce transmission errors includes dividing a stream of digital data into consecutive blocks of bits, and interlacing each block of bits by writing to an interlacing table. The interlacing table is arranged in the form of rows and columns of memory addresses, with a number of the rows and columns corresponding to predetermined interlacing parameters. The access sequences to the memory addresses for interlacing the blocks of bits are different from each other. The method further includes reading a block of bits in the interlacing table according to a memory addresses access sequence, and also writing bits to a consecutive block of bits according to the memory addresses access sequence during the reading.

Abstract: A semiconductor memory device includes a first data scramble circuit, which is configured between a data input buffer and a memory cell block, for outputting data by inverting or maintaining a polarity of an input data in response to a data scramble control signal and a second data scramble circuit, which is configured between the memory cell block and a data output buffer, for outputting data by inverting or maintaining a polarity of an output data in response to a data scramble control signal.