Abstract: A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block.

Abstract: A method for self-contained testing within a DRAM comprises the DRAM receiving an instruction from an external processor to test a memory core on the DRAM, and the DRAM self-testing the memory core with one or more BIST pattern stored in a multipurpose register on the DRAM. Optionally, the step of self-testing may include writing the BIST pattern into all locations of the memory core, reading each location of the memory core, and comparing the content read from each location of the memory core with the BIST pattern, wherein a negative comparison indicates a failure has occurred. In a further option, the method may further comprise, after testing the DRAM, initializing the DRAM with an INIT pattern stored in the multipurpose register on the DRAM.

Abstract: A memory module including a plurality of memory banks, a memory control unit, and a built-in self-test (BIST) control unit is provided. The memory banks store data. The memory control unit accesses the data in accordance with a system command. The BIST control unit generates a BIST command to the memory control unit when a BIST function is enabled in the memory module. While the system command accessing the data in a specific memory bank exists, the memory command control unit has the priority to execute the system command instead of the BIST command testing the specific memory bank. Memory reliability of a system including the memory module is enhanced without reducing the system effectiveness.

Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.

Abstract: A smart card includes a non-volatile memory, a CPU, and a plurality of pads. The non-volatile memory stores a test program. The CPU is released from a reset state in response to a test enable signal. The CPU executes the test program stored in the non-volatile memory based on predetermined flag information and stores a result of the test program in the non-volatile memory.

Abstract: A method and circuit for implementing enhanced memory reliability using memory scrub operations to determine a frequency of intermittent correctable errors, and a design structure on which the subject circuit resides are provided. A memory scrub for intermittent performs at least two reads before moving to a next memory scrub address. A number of intermittent errors is tracked where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads.

Abstract: A flash memory device includes a flash memory array, a set of non-volatile redundancy registers, a serial interface, and testing logic coupled to the serial interface, the testing logic configured to accept a set of serial commands from an external tester; erase the array; program the array with a test pattern; read the array and compare the results with expected results to identify errors; determine whether the errors can be repaired by substituting a redundant row or column of the array, and if so, generate redundancy information; and program the redundancy information into the non-volatile redundancy registers.

Abstract: Upon receiving a request for one or a set of data blocks associated with a given data segment, a disk cache controller may retrieve into cache the some part of the entire data segment from a disk. Each data segment on a disk may include a fixed number of data blocks, and all data segments may include the same number of data blocks. Data segments may be dynamically defined and their locations and sizes may vary from segment to segment. Data segments may be defined when data is written to the disk, or may be defined at a later point. A table associated with a cache controller may store information as to the physical location or address on a disk of the starting point and/or size of each data segment.

Abstract: A method for designing a video processor with a variable and programmable bitwidth parameter. The method comprises selecting logical operations having propagation delay that scales linearly with the bitwidth; determining a desired tradeoff curve; and grouping instances of a logic operation having same properties; for a single instance of each logic operation, matching an actual curve of the logic operation to the desired tradeoff curve, wherein the actual curve is determined by the propagation delay and bitwidth of the logic operation.

Abstract: According to one embodiment, an information processing apparatus includes an information processing apparatus main body, and a nonvolatile semiconductor memory drive. The semiconductor memory drive includes a control module configured to control execution of data read and write on a nonvolatile semiconductor memory in units of a predetermined number of sectors. In a case where a data size of write data from the information processing apparatus main body is less than a data size of the predetermined number of sectors, the control module reads, from the nonvolatile semiconductor memory, data in a predetermined number of sectors including a sector in which the write data is to be written, and in a case where an error is detected in the read data, the control module stores, in a management table, defective sector information which is indicative of a sector storing the data in which the error is detected.

Abstract: A failure mask memory is added to a semiconductor tester. In conjunction with a new failure filter, failures may be ignored or used to update the contents of failure mask memory. Only the first instance of a failure is reported reducing the size of test data logs.

Abstract: An apparatus according to the present invention is designed to perform formatting processing on an information storage medium. The storage medium has a data storage area including a user data area and a spare area. The user data area is provided to write user data on, while the spare area includes a replacement block to be used as a replacement for a block that has been detected as a defective block. The replacement block stores instruction information that instructs to read data from the defective block when data is read from the replacement block. The apparatus includes a control section for controlling the formatting processing. In performing the formatting processing, the control section updates information stored in the replacement block such that when data is read from the replacement block, the data is not read from the defective block.

Abstract: Herein described is at least a method and system for processing a read or write operation when one or more defects are mapped using one or more fractional sectors. The method comprises using one or more fractional sectors to map defects and to store data symbols. Furthermore, a first algorithm is used for translating a logical block address into a physical starting location such that one or more fractional sectors may be processed during a read or write operation. A second algorithm is used for temporally processing one or more portions of a track of a disk drive, wherein the one or more portions may comprise one or more defective fractional sectors, non-defective fractional sectors, frame remainders, and servo sectors. The system comprises a memory, a processor, and software resident in said memory. The process executes the software that implements the first and second algorithms.

Abstract: A method for manufacturing a multiple-chip memory device includes making a volatile memory element on a semiconductor substrate, examining the volatile memory element for one or more initial errors, correcting the one or more initial errors on the semiconductor substrate, incorporating the volatile memory element into the multiple-chip memory device, and incorporating a non-volatile memory element into the multiple-chip memory device. The volatile memory element is examined for one or more secondary errors, after incorporating the volatile memory element and the non-volatile memory element into the multiple-chip memory device. Repair information is stored in a non-volatile memory element, the repair information identifying the one or more secondary errors.

Abstract: A semiconductor device capable of reducing a memory area of a test circuit required for storing fail-information is provided. In the test circuit, for determining right/wrong of information obtained by memory access, specific fail-information among pieces of fail-information sequentially obtained in response to wrong-determination result is held in a first memory section; and differences in serial two pieces of fail-information sequentially continuing from the specific fail-information are held in a second memory section. The test circuit, when it obtains differences based on pieces of fail-information sequentially obtained with a wrong-determination result at the time of holding the specific fail-information as a base point, sequentially adds subsequent differences to the specific fail-information to decompress subsequent pieces of fail-information.

Abstract: Interleaving improves noise rejection in digital communication and storage systems. According a known scheme, the interleaving/deinterleaving is achieved by storing symbols in a temporary memory table of R rows×C columns in a row by row order, and reading them in a column by column order, or vice versa, so obtaining a rearranged order. Methods and devices for interleaving and deinterleaving are proposed which accomplish the same interleaving/deinterleaving operation with a reduced size of the temporary memory table. The rearrangement of the symbols according to the rearranged order is accomplished by using a table with a reduced memory size, in combination with the order with which the symbols are fetched from or stored in a further memory. The invention further relates to ICs and apparatuses for interleaving and/or deinterleaving.

Abstract: Circuits, architectures, systems, methods, algorithms, software and firmware for indicating positions of defective data storage cells using reserved (e.g., “pilot”) cells. The circuit generally includes a memory having multiple subunits, each subunit containing multiple data storage cells and at least one reserved cell. The reserved cells store information identifying whether one or more data storage cells in a subunit are defective. The method of identifying defective memory positions generally includes determining the status of data storage cells in a multi-subunit memory; storing such status information in a reserved cell; and reading the reserved cell. In various embodiments, the reserved cells differentiate between fewer voltage levels and/or store a lower density of information than the data storage cells. The present invention improves error correction capabilities using cells that are typically already available in many conventional nonvolatile memories.

Abstract: A solution for generating functional coverage bins for testing a device is disclosed. A method includes: receiving information of a failing test generated from a random simulation performed on the device; tracing a first sequence of signal events that happened in the failing test; correlating the signal events to coverage bins to generate a sequence of coverage bins; creating cross coverage event sequence bins based on the sequence of coverage bins; and outputting the created coverage event sequence bins for testing the device.

Abstract: A reconfigurable high performance computer includes a stack of semiconductor substrate assemblies (SSAs). Some SSAs involve FPGA dice that are surface mounted, as bare dice, to a semiconductor substrate. Other SSAs involve memory dice that are surface mounted to a semiconductor substrate. Elastomeric connectors are sandwiched between, and interconnect, adjacent semiconductor substrates proceeding down the stack. Each SSA includes a local defect memory and a self-test mechanism. The self-test mechanism periodically tests the SSA and its interconnects, and stores resulting defect information into its local defect memory. The computer is configured to realize a user design and then is run. A defect is then detected. If the defect is determined to be in a part of the computer used in the realization of user design, then the computer is reconfigured not to use the defective part and running of the computer is resumed, otherwise the computer resumes running without reconfiguration.

Abstract: A memory system includes a first parameter estimation module that receives pilot signals that are generated based on pilot data stored in a memory. The first parameter estimate module generates a first estimate of a signal quality value associated with a block of the memory based on reference pilot information. A second parameter estimation module generates a second estimate of the signal quality value based on the first estimate and user data signals that are generated based on user data stored in the memory. A processing module generates recovered user data based on the second estimate.

Abstract: The recording method of the present invention includes the steps of: receiving a write instruction which specifies at least a logical sector in which data is to be written; determining whether the logical sector corresponds to a recorded physical sector or an unrecorded physical sector; when it is determined that the logical sector corresponds to an unrecorded physical sector, writing the data into the unrecorded physical sector, determining whether a verification of the data which has been written into a physical sector is successful, if the verification of the data that has been written is not successful, writing the data into an unrecorded physical sector, generating a remapping table including remapping information which remaps an original address of the physical sector corresponding to the logical sector to a remapping address of the selected physical sector, and writing the remapping table on the write-once disc.

Abstract: A recording method of the present invention includes the steps of: receiving a write instruction which specifies at least a logical sector in which data is to be written; determining whether the logical sector specified by the write instruction corresponds to a recorded physical sector or an unrecorded physical sector (S1111); when it is determined that the logical sector specified by the write instruction corresponds to an unrecorded physical sector, writing the data into the unrecorded physical sector (S1112); and when it is determined that the logical sector specified by the write instruction corresponds to a recorded physical sector, writing the data into an unrecorded physical sector other than the recorded physical sector (S1113), generating a remapping table including remapping information which remaps an original address of the recorded physical sector to a remapping address of the selected physical sector, and writing the remapping table on the write-once disc (S1114).

Abstract: A memory circuit comprises a first memory that stores data in a plurality of memory locations that are associated with memory addresses. A memory interface communicates with said first memory. A second memory communicates with said memory interface and stores memory addresses of defective memory locations that are identified in said first memory.

Abstract: A memory module comprises first memory that stores data in memory blocks; second memory that temporarily stores data from at least one of the memory blocks and third memory for storing a relationship between addresses of the at least one of the memory blocks in the first memory and corresponding addresses of the data from the at least one of the memory blocks in the second memory. Storage capacities of the second and third memories are less than a storage capacity of the first memory. A control module selectively transfers data in the at least one of the memory blocks in the first memory to the second memory and stores and retrieves data from the second memory for the at least one of the memory blocks based on the relationship during the testing.

Abstract: An apparatus according to the present invention is designed to perform formatting processing on an information storage medium. The storage medium has a data storage area including a user data area and a spare area. The user data area is provided to write user data on, while the spare area includes a replacement block to be used as a replacement for a block that has been detected as a defective block. The replacement block stores instruction information that instructs to read data from the defective block when data is read from the replacement block. The apparatus includes a control section for controlling the formatting processing. In performing the formatting processing, the control section updates information stored in the replacement block such that when data is read from the replacement block, the data is not read from the defective block.

Abstract: A system and method for logging events processed by an operating system is provided. The events logged can include interrupt and non-interrupt events, and can include user-defined events. Information concerning the interrupt events is initially written, during event handling time, into a first buffer while information concerning non-interrupt events is initially written, during event handling time, into a second buffer. Information from the two buffers is then written to a third buffer not during event handling time. Separating the interrupt event buffer from the non-interrupt event buffer rather than having one buffer, and writing relatively small amounts of data during event handling time to memory, rather than transporting data to slower non-memory mapped devices allows the event logger to be less intrusive and facilitates greater accuracy in event logging.

Abstract: A memory module comprises first memory that includes memory blocks, second memory, and non-volatile memory. A control module, during testing of at least one of the memory blocks having a first address, stores data from the at least one of the memory blocks in the second memory at a second address and stores the first and second addresses in the non-volatile memory. Content addressable memory (CAM) stores addresses of defective memory locations in the first memory and stores and retrieves data for the defective memory locations.

Abstract: A method and apparatus is disclosed herein for logging and/or synchronizing data exchanges. In one embodiment, the method comprises receiving a request from a requester to post data to a first log, identifying the log based on a context identifier in the request indicative of a location of the first log and digital data associated with a document corresponding to the first log, creating a first entry based on data in the request, appending the first log with the first entry, calculating a first identifier based on log entries in the first log, and sending the first identifier to the requester.

Abstract: A memory circuit includes a memory interface. A first memory receives a first read address from the memory interface. A second memory stores addresses of defective memory locations found in the first memory, receives the first read address from the memory interface, compares the first read address to the addresses stored in the second memory, and, if a matching address is found, reads first data from the second memory. The first memory reads second data from a memory location in the first memory corresponding to the first read address. A multiplexer receives the second data and the first data from the first memory and the second memory, respectively, when the matching address is found, and selectively outputs one of the second data and the first data to the memory interface.

Abstract: A system and method are herein disclosed for managing memory defects in an information handling system. More particularly, a system and method are described for generating a usable memory map which excludes memory locations containing defect memory elements. In an information handling system, a memory defect map, which contains information about the location of defective memory elements, is coupled to the memory device. As a map of memory usable by the system is created, usable memory regions containing defective memory elements are excluded from the memory map. The memory map is passed to the operating system, which uses only those regions of memory designated as usable and non-defective.

Abstract: For recording or replaying in real-time digital high bandwidth video signals, e.g. HDTV, HD progressive or HD film capture signals, very fast memories are required. For storage of streaming HD video data NAND FLASH memory based systems could be used. Flash memory devices are physically accessed in a page oriented mode. According to the invention, the input data are written in a multiplexed fashion into a matrix of multiple flash devices. A list processing is performed that is as simple and fast as possible, and defect pages of flash blocks of single flash devices are addressed within the matrix architecture. When writing in a sequential manner, the data content for the current flash device page of all flash devices of the matrix is copied to a corresponding storage area in an additional memory buffer. After the current series of pages has been written without error into the flash devices, the corresponding storage area in an additional memory buffer is enabled for overwriting with following page data.

Abstract: A method for testing an integrated circuit implemented in an electronic system. The method includes placing an integrated circuit (or portion thereof) that is implemented in an operational system (e.g., in a computer system) in an offline status. An electrical parameter of the integrated system (e.g., a voltage, clock frequency, etc.) is set, and a built-in self-test (BIST) is conducted. Any failures that occur during the BIST are recorded. Testing is then repeated for each of a plurality of predetermined values of the electrical parameter, recording any failures that occur. Once testing is complete a failure rate/range is determined for each of the predetermined values.

Abstract: A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data relating to over-programmed bits in the primary array. When the over-programmed bits in the primary array are erased, the error documentation memory array is erased as well, deleting the documentation data relating to the over-programmed bits.

Abstract: Technologies disclosed herein can be used to diagnose defects on die having both scan chain and system logic defects, including in situations where the presence of one or more faults in the system logic potentially obscures the detectability of one or more faults in the scan chains (or channels) and vice versa. At least some embodiments employ an iterative approach where at least some scan chain faults are identified, these chain faults are used to identify system logic faults, and then additional chain faults are identified using the system logic faults and vice versa. Failing bits can be partitioned into at least two groups: failing bits determined as being caused by system logic failures, and failing bits determined as being possibly caused by chain defects, system logic defects, or the compound effects of both types of defects.

Abstract: Herein described is at least a method and system for processing a read or write operation when one or more defects are mapped using one or more fractional sectors. The method comprises using one or more fractional sectors to map defects and to store data symbols. Furthermore, a first algorithm is used for translating a logical block address into a physical starting location such that one or more fractional sectors may be processed during a read or write operation. A second algorithm is used for temporally processing one or more portions of a track of a disk drive, wherein the one or more portions may comprise one or more defective fractional sectors, non-defective fractional sectors, frame remainders, and servo sectors. The system comprises a memory, a processor, and software resident in said memory. The process executes the software that implements the first and second algorithms.

Abstract: The present invention discloses a method for performing a defective-area management adaptive to a slipping replacement algorithm in an optical media with segmented sector/blocks, by either keeping buffering a read user data of the sector/block to a buffer memory, regardless of the read sector/block is defective, or keeping buffering the read user data to two different memories based on whether the sector/block is defective, thereby simplifying the complicated steps due to absence of interruption of data buffering, and therefore raising an operating performance.

Abstract: A data complementation method including a defective-data confirmation step of confirming if there is address information of defective data, a complementation-data confirmation step of confirming if complementation data is recorded, a complementation-data transmission request step of requesting a recovery server to transmit the complementation data, a complementation-data acquisition step of acquiring the complementation data through a communication network, and a complementation-data record step of recording the complementation data.

Abstract: A memory redundancy reconfiguration for N base blocks associated with k redundant blocks. The data will be written into both base blocks and defect-free redundant blocks if the base blocks are defective; k multiplexers MUXRi each having N input signals (d0 to dN?1) capable of being connected to k input signals of the redundant blocks; N multiplexers MUXi each having k+1 input signals from k redundant blocks (R0 to Rk?1) and one base block (Ni), capable of being connected to N output signals (qi); and logic means associated with each multiplexer, to convert the input signals of the multiplexer to its output signal.

Abstract: A semiconductor test system with self-inspection of memory repair analysis is disclosed, comprising a memory repair analysis device, an analysis fail memory and a self-inspection controller. The self-inspection controller controls storing a set of simulated fail bit addresses and a set of simulated repair line addresses, provided from outside, into the analysis fail memory in advance, controls the memory repair analysis device to execute a particular repair analysis operation with respect to the set of simulated fail bit addresses to produce repair line address information, and compares the repair line address information, obtained after calculation, directly with the set of simulated repair line addresses in the analysis fail memory. Thus, before physically proceeding with the operation of testing, the invention is capable of self-inspecting if there is an abnormal condition of the memory repair analysis device and the analysis fail memory contained therein.

Abstract: A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.

Abstract: According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storage locations for the cache, a detector to measure a thermal environment of the processor, and circuitry to raise an operating voltage of the processor if the actual number of unreliable storage locations exceeds the acceptable number of unreliable storage locations, and if the thermal environment is acceptable.

Abstract: A method and apparatus are disclosed in which defect behavior in an integrated circuit is discovered and modeled rather than assuming defect behavior in the form of a fault. A plurality of tests are performed on an integrated circuit to produce passing and failing responses. The failing responses are examined in conjunction with circuit description data to identify fault locations. For at least certain of the fault locations, the logic-level conditions at neighboring locations which describe the behavior of a failing response are identified. Those logic level conditions are combined into a macrofault for that location. The macrofault is then validated and can be then used to identify more tests for further refining the diagnosis. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: In accordance with certain embodiments of the present disclosure, an information handling system is provided. The information handling system may include a plurality of processors, each processor comprising multiple cores, a memory system coupled to the plurality of processors, and a controller coupled to the plurality of processors. The controller may be configured to: receive a local system management interrupt (SMI) signal regarding an error associated with at least one of the multiple cores, determine that the received local SMI signal triggers a global SMI based on a global SMI trigger rule, cause the plurality of processors to enter a global system management mode (SMM), and log the error in a shared resource shared by the plurality of processors during the global SMM.

Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Abstract: A method for testing a burner includes the steps of: providing a rewriter (RW) disk (4) in good burning condition, and inserting the RW disk into a test burner (3) connected to a computer (1); selecting a burner type for the burner; designating a source file to be burned, and setting a counter J=0, a loop time N and a maximum time of fail test M; erasing all data on the RW disk; burning the source file onto the RW disk; determining whether the source file is successfully burned to the RW disk; executing J=J+1 if the source file is successfully burned to the RW disk; repeating the erasing step, the burning step and the determining step, and counting a time of successfully burned process by the counter J, until J=N?M+1 which denotes that the burner is in good burning condition. A related method for testing a RW disk is also provided.

Abstract: A system for repairing embedded memories on an integrated circuit includes an external Built-In Self-repair Register (BISR) associated with every reparable memory. Each BISR is serially configured in a daisy chain with a fuse box controller. The controller determines the daisy chain length upon power up. The controller may perform a corresponding number of shift operations to move repair data between BISRs and a fuse box. Memories can have a parallel or serial repair interface. The BISRs may have a repair analysis facility into which fuse data may be dumped and uploaded to the fuse box or downloaded to repair the memory. Pre-designed circuit blocks provide daisy chain inputs and access ports to effect the system or to bypass the circuit block.

Abstract: A test apparatus for testing a memory under test is provided, including a pattern generator generating a read address from which data is read from the memory under test and an expected value of the data read from the read address, a logical comparator comparing the read data read from the read address of the memory under test to the expected value and outputting fail data indicating pass/fail of every bit of the read data, a first fail memory storing a grouping of the read address and the fail data in a case where the read data and the expected value are not the same, a second fail memory storing fail data concerning addresses corresponding to each address of the memory under test, and an updating section updating fail data stored in the second fail memory and corresponding to the read address based on the grouping of the address and the fail data read from the first fail memory.

Abstract: When a primary spare area is allocated for slipping replacement and linear replacement upon initialization, and a remaining portion of the primary spare area after slipping replacement and allocated for linear replacement after initialization are insufficient, a supplementary spare area is allocated. The sizes of the primary and supplementary spare areas are determined by the number of defects generated upon initialization. The information on the sizes of the spare areas, and the remainder state information representing the degree of use of the spare areas, are recorded, so that the spare areas can be efficiently managed. Also, in the defect management method, when an area that has already been linearly replaced is allocated as a supplementary spare area, defective blocks within the allocated supplementary spare area are not used for linear replacement, and the entries of a secondary defect list (SDL) with respect to the defective blocks are not changed.

Abstract: One embodiment of the invention relates to a circuit board for testing upsets caused by charged particles delivered under testing conditions. The circuit board comprises a device under test including an internal memory, a memory control unit to generate test patterns for comparison with data read from stored areas within the internal memory of the device under test, and a memory that is configured to only store error data. Other embodiments are described and claimed.

Abstract: A method of testing a SIP that has a CPU, a nonvolatile memory and a volatile memory. First, the CPU is used to test the memories. Then the CPU is tested separately. Preferably, the programs for testing the memories are pre-stored in and loaded from the nonvolatile memory into the volatile memory and are executed by the CPU in the volatile memory. Preferably, the test results are stored in the nonvolatile memory.