Abstract: A state machine; a BIST circuit including a test pattern generator and an expected value comparison circuit; a state monitoring circuit configured to monitor whether or not a state of the state machine is a specific state; and a transition request detection circuit configured to detect a transition request signal from the specific state to a next state, are held. When the state monitoring circuit decides that the state of the state machine is the specific state, the state machine outputs a signal indicating the specific state as a state output of the state machine, and the BIST circuit performs a test of the state machine. When the transition request detection circuit detects the transition request signal while the test is performed, the BIST circuit stops the test of the state machine.

Abstract: Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected.

Abstract: By constructing a universal test circuit on a tester chip, and stacking the tester chip in an IC package together with operational circuit chips to be tested, the problems inherent with external IC testing are reduced. The tester chip can be standardized across a number of different chip combinations and, if desired, pre-programmed during manufacturing for a particular package. The tester chip interfaces to other chips in the stack advantageously are standardized.

Abstract: Provided are a self-diagnosis system and a test circuit determination method that are capable of determining normality of a test circuit which diagnoses a test target circuit. A self-diagnosis system according to an aspect of the present invention includes a test circuit including first and second diagnosis controllers which determine normality of a test target circuit by using an execution result of a test pattern in the test target circuit; and a test circuit determination unit which determines normality of the test circuit by comparing a normality determination result of the test target circuit output from the first diagnosis controller with a normal determination result of the test target circuit output from the second diagnosis controller.

Abstract: A system for testing an integrated circuit, in which the system includes a deserializer, a frame sync module, and a diagnostic module. The deserializer is external to the integrated circuit and is configured to receive messages in a serial data format, wherein the messages include test results associated with the integrated circuit, and deserialize the messages into data frames. The frame sync module is configured to provide control code based on the data frames, wherein the control code includes, in a digital format, status information associated with the messages deserialized into the data frames. The diagnostic module is configured to generate, based on the control code, diagnostic data associated with states of the integrated circuit.

Abstract: The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

Abstract: A circuitry testing module for testing an external circuit of a Light-Emitting Diode (LED) includes at least one logic unit and a latch circuit. Two input terminals of the at least one logic unit are connected to a first end and a second of the LED correspondingly. The output terminal of the at least one logic unit is connected to the latch circuit. If the external circuit works normally, the logic unit outputs a first logic operating signal to the latch unit, and the latch circuit outputs a first latch signal. If the external circuit does not work normally, the logic unit outputs a second logic operating signal to the latch unit, and the latch circuit outputs a second latch signal.

Abstract: A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface.

Abstract: A circuit test interface and a test method are disclosed. The circuit test interface may include a test voltage input pad, a test voltage output pad, and a plurality of input buffers. Each of the plurality of input buffers may have a first input terminal, a second input terminal, and an output terminal. The first input terminal of each respective input buffer may be coupled to one of a plurality of through-silicon vias (TSVs). The circuit test interface may further include a plurality of switch units. Each of the plurality of switch units may have a first terminal and a second terminal. The circuit test interface may further include a scan chain, coupled to both the output terminal of each of the plurality of input buffers and to the test voltage output pad.

Abstract: A micro controller includes an input and output unit having a reset terminal, a plurality of input terminals, and a test enable terminal, a test mode setting unit which allocates a first input terminal of the plurality of input terminals to a test clock terminal and allocates the remaining N input terminals to L test terminals, in response to a signal output from the input and output unit, and a processor which controls the input and output unit and the test mode setting unit. The test mode setting unit includes M flip-flops which receives a test clock signal from the first input terminal, a test signal from the N input terminals, and a test enable signal from the test enable terminal, and a decoder which decodes a signal output from the M flip-flops and determines whether or not to allocate the N input terminals to the L test terminals.

Abstract: A method for operating a data processing system to generate a test for a device under test (DUT) is disclosed. The method utilizes a model of the DUT that includes a plurality of blocks connected by wires and a set of control inputs. Each block includes a plurality of ports, each port being either active or inactive. Each block is also characterized by a set of constraints that limit which ports are active. The active ports of at least one of the blocks are constrained by one of the control inputs. A test vector having one component for each port of each block and one component for each control input is determined such that each set of constraints for each block is satisfied. The test vector defines a test for the DUT.

Abstract: A method, computer program storage device and apparatus are provided for flexible observability during a scan. In one aspect of the present invention, a method is provided. The method includes providing a selector load input to at least a portion of a scan chain, selecting an observe-only scan mode for the at least a portion of the scan chain based at least upon the selector load input, and providing a data input to a storage element in the scan chain based at least upon the observe-only scan mode. The apparatus includes a first scan chain multiplexor comprising a selector input, a first input terminal, a second input terminal and an output terminal. The apparatus also includes a first scan chain storage element comprising an input terminal and an output terminal, where the input terminal of the first scan chain storage element is communicatively coupled to the output terminal of the first scan chain multiplexor.

Abstract: A 1149.1 TAP performs at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. In a second embodiment the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal. In a third embodiment the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states. In a fourth embodiment the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and inputting these states to a Dual Port Router to control the at-speed operations of a circuit. The improvements are achieved without requiring any additional IC pins beyond the 4 required TAP pins. Devices including the TAP improvements can be operated compliantly in a daisy-chain arrangement with devices that don't include the TAP improvements.

Abstract: Embedded logic is implemented in a partially reconfigurable programmable logic device (PLD), thus allowing debugging of implemented instantiations of logic after partial reconfiguration. Several instantiations of logic are received at the PLD. One instantiation of logic is implemented in a reconfigurable region of logic within the PLD. The instantiation of logic includes a port that provides a constant interface between the reconfigurable region of logic and a fixed region of logic within the PLD. The port may receive signals from probe points implemented within the reconfigurable region of logic. The port may provide the signals to a signal interface implemented within a fixed region of logic. Furthermore, an embedded logic analyzer may be implemented in either the reconfigurable region of logic or the fixed region of logic. The embedded logic analyzer receives signals from the probe points and provides signal visibility to an external computing system.

Abstract: A Joint Test Action Group (JTAG) apparatus and a method for implementing JTAG data transmission are disclosed. The JTAG apparatus includes an isolation circuit connected with a processor and pins of a JTAG programmable logic device, wherein the isolation circuit has a register/registers corresponding to the pins of the JTAG programmable logic device. Based on a high or low level signal written into the register/registers of the isolation circuit by the processor, the isolation circuit drives the pins of the JTAG programmable logic device, and transmits the JTAG data corresponding to the high or low level signal from the processor to the JTAG programmable logic device. The isolation circuit is used to implement protection of a JTAG interface or a serial port of a personal computer connected with the JTAG apparatus.

Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: A semiconductor device, comprising: a user circuit having a plurality of flip-flops; and a connection path which, while in test mode, connects the plurality of flip-flops and forms a scan chain, wherein the connection path has a logic operation circuit which performs a logic operation on a non-inverted output value of any flip-flop among the plurality of flip-flops and outputs the result, or, an inverted value connection path which outputs to a following-stage flip-flop an inverted output value of any flip-flop among the plurality of flip-flops.

Abstract: A scannable pulse dynamic logic gate may include an evaluation network that evaluates dynamic inputs in response to assertion of an evaluate pulse. The evaluate pulse may be generated from a clock signal such that it is shorter in duration than the clock signal. During a normal mode of operation, when the evaluate pulse is asserted, the evaluation network may discharge a dynamic node depending on the state of the dynamic inputs. The resultant state of the dynamic node may be stored within an output storage element. When the evaluate pulse is deasserted, the dynamic node may be precharged. During a scan mode of operation, the dynamic node may remain precharged. Scan data may be transferred to the output storage element under the control of scan-related control signals.

Abstract: A semiconductor integrated circuit is configured so that a transition scan test can be performed thereon. The semiconductor integrated circuit includes a plurality of logic circuit blocks having different operation frequencies; a clock supply unit for supplying a plurality of clock signals having frequencies corresponding to the operation frequencies of the logic circuit blocks from a clock supply source; a compression scan circuit including a plurality of scan chains formed of a plurality of flip-flop circuits, a pattern deployment circuit connected to the scan chains on an input side thereof, and a pattern compression circuit; and a clock control unit for controlling the clock supply unit to stop supplying the clock signals to specific ones of the flip-flop circuits of the scan chains when a capture operation is performed during a transition scan test.

Abstract: A network-fabric used for testing with an external or internal tester is shown for a Structured ASIC. In one embodiment, the Structured ASIC uses a microprocessor, network-aware IO routing fabric comprising network agents in a scalable novel configuration, with the network-aware IO having a plurality of blocks connected in series in a plurality of paths in the fabric leading to and from the microprocessor and memory and/or logic, the blocks acting as intelligent network agents under processor control to determine what state they can assume, whether to pass a data signal or not along these paths, comprising open loops and closed loops running to and from the microprocessor and memory and/or logic, primarily for testing and determining the state of the memory and logic. In another embodiment a JTAG controller may receive JTAG test commands from an external testing apparatus and set up to communicate along the fabric.

Abstract: According to one embodiment, a semiconductor integrated circuit includes at least one memory and at least one built-in self test (BIST) circuit. In the memory, data can be stored. The BIST circuit tests the memory and includes an address generator. The address generator operates in one of a first operating mode and a second operating mode. In the first operating mode, address signals corresponding to all addresses of the memory are generated. In the second operating mode, the address signals are generated such that each bit of an address input of the memory can be one signal state of both 0 and 1 and such that different bits constitute a set of pieces of data in which the bits choose different signal states at least once.

Abstract: A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface.

Abstract: A semiconductor chip having a functional block that performs a communication function includes an input circuit that supplies an oscillating test signal to the functional block, and a test circuit that detects the strength of an oscillating signal which the functional block outputs in response. A strength signal indicating the detected strength is output from the test circuit through an external terminal of the semiconductor chip to a test device. The test device evaluates the strength signal to decide whether an operating characteristic of the functional block is within a specified range. The strength information indicated by the strength signal is not affected by impedance on the signal transmission line between the semiconductor chip and the test device, so the test is not affected by impedance loss.

Abstract: An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic.

Abstract: An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic.

Abstract: Expedited memory drive self test, including: determining, by a drive self test module, a base block size for testing a memory drive; determining, by a drive self test module, a block group size for testing a memory drive; determining, by the drive self test module, a percentage of the memory drive to test; and for each block group size of memory in the memory drive: testing for media defects, by the drive self test module, a number of blocks in a block group that corresponds to the percentage of the memory drive to test.

Abstract: An integrated circuit integrated on a semiconductor material die and adapted to be at least partly tested wirelessly, wherein circuitry for setting a selected radio communication frequencies to be used for the wireless test of the integrated circuit are integrated on the semiconductor material die.

Abstract: Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage.

Abstract: A method and system for compiling a representation of a source circuit including one or more source subchannels associated with portions of source logic driven by a plurality of clock domains are described. Each source subchannel may generate packets carrying signal data from one of the portions of the source logic. A representation of a destination circuit may be compiled to include one or more destination subchannels associated with portions of destination logic replicating the source logic. Each destination subchannel may forward the signal data via the packets to one of the portions of the destination logic. A switching logic may be configured to map the source subchannels to the destination subchannels as virtual channels to forward the packets from the source subchannels to the destination subchannels. A single queue may be configured to couple with the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels.

Abstract: An integrated circuit includes an input unit, a core processor and M output buffers, where M is a natural number greater than 1. The input unit has an output control pin, and receives an output control signal. The core processor is coupled to the input unit, and receives the output control signal to provide M output control signals. The M output buffers are coupled to the core processor, and are time-division multiplexing and enabled in response to the M output control signals, respectively, to output M output signals in M operation periods, respectively.

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Abstract: A flip-flop circuit includes a master latch, a master/slave gate, a slave latch, a slave gate, a feedback latch, and a master gate. The master latch has an input and an output. The master/slave gate has an input coupled to the output of the master latch and an output. The slave latch has input coupled to the output of the master/slave gate and an output. The slave gate has input coupled to the output of the slave latch and an output. The has an input coupled to the output of the slave gate and an output. The master gate has an input coupled to the output of the feedback latch and an output coupled to the input of the master latch.

Abstract: An on-chip functional debugger includes one or more functional blocks each providing one or more functional outputs. A hierarchical selection tree is formed by one or more selectors having the output of one of the selectors as a final output and individual selector inputs coupled either to a functional output from the functional blocks or to an output of another selector. A selection signal coupled to the select input of each of the selectors to enable a selected one of its output. An output node coupled to the final output. A method of providing on-chip functional debugging is also provided. A desired functional output from one or more available functional outputs is selected and then the selected functional output is coupled to an output node.

Abstract: A method and circuits for implementing aperture function calibration for Logic Built In Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. The aperture function calibration uses aperture calibration data, and an LBIST calibration channel having a predefined number of scan inversions between the aperture calibration data and a multiple input signature register (MISR). LBIST is run selecting the LBIST calibration channel and masking other LBIST channels to the MISR. A change in the MISR value, for example, from zero to a non-zero value, is identified and an aperture adjustment is calculated and used to identify any needed adjustment of aperture edges.

Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

Abstract: A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device.

Abstract: Methods and apparatus are provided for determining whether a built-in-test fault code (BITFC) data sequence generated by a built-in-test (BIT) of a particular module of a complex system is indicative of an actual fault condition. A regression function is generated for the particular module based on stored BITFC data sequences generated by the BIT and stored repair data for that module from a fault history database. Later, during operation of the particular module, the BIT generates a new BITFC data sequence. A processor can then load the new BITFC data sequence and execute the regression function with respect to the new BITFC data sequence to determine whether the new BITFC data sequence is indicative of an actual fault condition at the particular module or is indicative of a false fault condition at the particular module.

Abstract: An integrated circuit comprises random logic communicatively coupled to a non-scannable memory array. The integrated circuit also comprises a built-in self-test (BIST) controller adapted to apply test data to the random logic and propagate the test data through the random logic to test the memory array.

Abstract: Some of the embodiments of the present disclosure provide a system, device and a method performing N read cycles on a plurality of memory cells of a memory sector, wherein N is an integer greater than one; constructing (N+1) bin histograms based at least in part on performing the N read cycles; identifying a shortest bin histogram of the (N+1) bin histograms; and based on a height of the shortest histogram, assigning a log-likelihood ratio (LLR) to the shortest bin histogram. Other embodiments are also described and claimed.

Abstract: A virtual In-Circuit Emulation (ICE) capability is provided herein for supporting testing of Joint Test Action Group (JTAG) hardware. A Virtual ICE Driver is configured for enabling any debug software to interface with target hardware in a flexible and scalable manner. The Virtual ICE Driver is configured such that the test instruction set used with the Virtual ICE Driver is not required to compute vectors, as the JTAG operations are expressed as local native instructions on scan segments, thereby enabling ICE resources to be accessed directly. The Virtual ICE Driver is configured such that ICE may be combined with instrument-based JTAG approaches (e.g., the IEEE P1687 standard and other suitable approaches).

Abstract: Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1, as the scan test stimulus data for another circuit, such as circuit 2. After reset, a scan path captures the output response data from the reset stimulus from all circuits. A tester then shifts the captured data only the length of the first circuit's scan path while loading the first circuit's scan path with new test stimulus data. The new response data from all the circuits then is captured in the scan path. This shift and capture cycle is repeated until the first circuit is tested. The first circuit is then disabled and any remaining stimulus data is applied to the second circuit. This process is repeated until all the circuits are tested. A data retaining boundary scan cell used in the scan testing connects the output of an additional multiplexer as the input to a boundary cell.

Abstract: An apparatus for protecting against external attacks for a processor based on an ARM core and a method using the same are provided. A method for protecting against external attacks for a processor based on an ARM core in accordance with an embodiment of the present invention includes: setting up a register using a reset handler, which is executed first within a boot image; generating a control signal for protecting against external attacks using any one of an external debug request signal and an output signal of the register; and blocking a JTAG interface used for JTAG communication with the processor based on the ARM core according to the control signal for protecting against external attacks.

Abstract: A process for improving design-limited yield by collecting test fail data, converting to electrical faults, and localizing to physical area on semiconductor die. The steps of identifying an area on a wafer containing a fault to enable the analysis of specific defects, accumulating data suitable for yield monitoring analysis based on pattern test failures logged on scan cells in scan chains on automatic test equipment, and translating scan cell and scan chain failure reports to geometric locations of electrical structures on wafers.

Abstract: Disclosed are integrated circuits that incorporate an asynchronous circuit with a built-in self-test (BIST) architecture using a handshaking protocol for at-speed testing to detect stuck-at faults. Specifically, a test pattern generator applies test patterns to an asynchronous circuit and an analyzer analyzes the output test data. The handshaking protocol is achieved through the use of a single pulse generator, which applies a single pulse to the test pattern generator to force switching of the test pattern request signal and, thereby to control application of the test patterns to the asynchronous circuit and subsequent switching of the test pattern acknowledge signal. Generation of this single pulse can in turn be forced by the switching of the test pattern acknowledge signal.

Abstract: A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes “n” number of groups of the failing memory output data during “n” cycles using analysis logic and calculating a repair solution. Normal operations can be resumed.

Abstract: A built-in self test (BIST) method and system for testing a memory included on an integrated circuit includes activating a component of the integrated circuit, partitioning the memory into a first part for use by non-BIST components and second part for BIST, and executing BIST on the second part of the memory while the component is operating. While the BIST is executing, the non-BIST components can access the first part of the memory and perform normal functional operations. The BIST method and system finds memory faults that are related to an I-R voltage drop due to the physical placement of the memory relative to power supply sources.

Abstract: A semiconductor device includes a first internal terminal, a first transistor, a second transistor, an oscillator including an output terminal to output a clock signal, and a comparator coupled to a first internal terminal, and that compares a potential of the first internal terminal when the first internal terminal is coupled to the first reference potential with a potential of the first internal terminal when the first internal terminal is coupled to a second reference potential, an external terminal being connectable to the first internal terminal, and a second internal terminal being coupled to the external terminal, and that receives an input signal through the external terminal. Each of the first control terminal and the second control terminal is coupled to the output terminal to commonly receive the clock signal. The first transistor and the second transistor exclusively operate according to the clock signal.

Abstract: Various embodiments of the present invention provide systems and methods for evaluating and debugging a data decoder. For example, a data decoder circuit is discussed that includes an input memory, a data decoder operable to decode data from the input memory in one or more iterations, an output memory operable to store decoded data from the data decoder, and a test port operable to provide access to the input memory, the data decoder and the output memory.

Abstract: A current measurement unit measuring power supply currents each consumed in a plurality of circuit blocks of which at least one of the circuit blocks includes a processor, and outputting the measurement result as the power supply current values. A selection unit selecting at least one of the power supply current values according to selection information. A trace buffer sequentially holding the power supply current values being selected by the selection unit together with execution information of the processor, and sequentially outputting the held information. By selecting the power supply current values of the circuit blocks required for debugging according to the selection information, the number of external terminals of a semiconductor integrated circuit required for the debugging which includes tracing the power supply current values may be reduced. As a result, a chip size of the semiconductor integrated circuit with a debug function may be reduced.