Error Correcting Code With Additional Error Detection Code (e.g., Cyclic Redundancy Character, Parity) Patents (Class 714/758)
  • Patent number: 11327184
    Abstract: The invention relates to providing atmospheric correction data in a GNSS network-RTK system for correcting GNSS data, wherein a base triangulation that encloses at least part of the reference stations of the GNSS network-RTK system is subdivided into child triangles by means of a recursive division of parent triangles into four child triangles, synthetic data are determined for each of the child triangles based on a triangulation algorithm applied to basic data of the reference stations such that the synthetic data represent a gridded representation of the basic data, and access to correction data is provided, wherein the correction data comprise at least part of the synthetic data arranged in a quad-tree hierarchy.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: May 10, 2022
    Assignee: LEICA GEOSYSTEMS AG
    Inventors: Frank Takac, Paul Spencer
  • Patent number: 11329670
    Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode outer-encoded bits to generate an LDPC codeword including LDPC information bits and parity bits; a puncturer configured to puncture some of the parity bits included in the LDPC codeword; and a mapper configured to map the LDPC codeword except the punctured parity bits to symbols for transmission to a receiver, wherein the puncturer calculates a number of parity bits to be punctured among the parity bits included in the LDPC codeword based on a number of the outer-encoded bits, a number of the LDPC information bits, and a minimum number of parity bits to be punctured among the parity bits included in the LDPC codeword.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: May 10, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Kyung-Joong Kim, Hong-sil Jeong
  • Patent number: 11323134
    Abstract: Provided is an encoding method and device and a decoding method and device for structured LDPC. The encoding method includes: determining a base matrix used for encoding and performing an LDPC encoding operation on a source information bit sequence according to the base matrix and an expansion factor Z corresponding to the base matrix to obtain a codeword sequence, where Z is a positive integer. The base matrix includes multiple submatrices and the submatrices include an upper-left submatrix Hb1 and an upper-left submatrix Hb2, and the upper-left submatrix Hb1 is an upper-left submatrix of the upper-left submatrix Hb2.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: May 3, 2022
    Assignee: XI'AN ZHONGXING NEW SOFTWARE CO., LTD.
    Inventor: Jun Xu
  • Patent number: 11314586
    Abstract: Mapping information management for data storage. A mapping information format without any uncorrectable flag bits (UNC bits) is shown. A controller provides a cyclic redundancy check (CRC) engine. In response to an uncorrectable marking command issued by a host, the controller operates the cyclic redundancy check engine to encode a data pattern with a biased encoding seed to generate biased cyclic redundancy check code. The controller programs the data pattern and the biased cyclic redundancy check code to the non-volatile memory. The data pattern, therefore, will not pass CRC. The uncorrectable marking command works.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: April 26, 2022
    Assignee: SILICON MOTION, INC.
    Inventors: Ting-Han Lin, Che-Wei Hsu
  • Patent number: 11316532
    Abstract: Devices, systems and methods for improving decoding operations of a decoder are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising N columns, wherein each of at least B columns of the parity matrix has a column weight that exceeds a predetermined column weight, processing the N columns based on a message passing algorithm, and determining, based on the processing, a candidate version of the transmitted codeword, wherein the processing for each of the N columns comprises performing a read operation, a variable node update (VNU) operation, and a check node update (CNU) operation on the first set and the second set, the read operation and the CNU operation on each of the at least B columns spanning two or more time-steps.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: April 26, 2022
    Assignee: SK hynix Inc.
    Inventors: Michael Hsu, Hongwei Duan, Aman Bhatia
  • Patent number: 11316540
    Abstract: A method of decoding polar codes based on belief propagation includes conventional belief propagation to decode the polar codes first; when a number of iterations exceeds a predefined upper limit and a cyclic redundancy check fails, the method selects log-likelihood ratio vectors of a plurality of R or L messages from a plurality of log-likelihood ratio vectors generated in each of the iterations and generates another set of log-likelihood ratio vectors (referred to as candidate vector group) to be used as initial values of the R or L messages for a subsequent belief propagation to perform belief propagation decoding iterations and cyclic redundancy check again. Whenever a decoding result passes the cyclic redundancy check, the method exits; otherwise, the method iterates the above procedure until a maximum number of candidate vector groups has been reached.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: April 26, 2022
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Tzi-Dar Chiueh, Bei-Sheng Su
  • Patent number: 11309050
    Abstract: There are provided a memory controller and a memory system having the same. A memory controller includes: an internal memory for storing error injection information for an error test operation and error test information that is a result of the error test operation; and a central processing unit for receiving first sector data from a host, and performing an error test operation on a memory device according to the error injection information, when the error injection information is included in the first sector data.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: April 19, 2022
    Assignee: SK hynix Inc.
    Inventor: Dae Gon Cho
  • Patent number: 11309914
    Abstract: A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: April 19, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Belkacem Mouhouche, Daniel Ansorregui Lobete, Kyung-joong Kim, Hong-sil Jeong
  • Patent number: 11309997
    Abstract: Polar codes may be generated with a variable block length utilizing puncturing. Some puncturing schemes consider punctured bits as unknown bits, and set the log likelihood ratio (LLR) for those bits to zero; while other puncturing schemes consider punctured bits as known bits, and set the LLR for those bits to infinity. Each of these puncturing schemes has been observed to provide benefits over the other under different circumstances, especially corresponding to different coding rates or different signal to noise ratio (SNR). According to aspects of the present disclosure, both puncturing schemes are compared, and the puncturing scheme resulting in the better performance is utilized for transmission.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: April 19, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Changlong Xu, Jian Li, Jilei Hou, Neng Wang
  • Patent number: 11302406
    Abstract: Multi-gate NOR flash thin-film transistor (TFT) string arrays are organized as three dimensional stacks of active strips. Each active strip includes a shared source sublayer and a shared drain sublayer that is connected to substrate circuits. Data storage in the active strip is provided by charge-storage elements between the active strip and a multiplicity of control gates provided by adjacent local word-lines. The parasitic capacitance of each active strip is used to eliminate hard-wire ground connection to the shared source making it a semi-floating, or virtual source. Pre-charge voltages temporarily supplied from the substrate through a single port per active strip provide the appropriate voltages on the source and drain required during read, program, program-inhibit and erase operations. TFTs on multiple active strips can be pre-charged separately and then read, programmed or erased together in a massively parallel operation.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: April 12, 2022
    Assignee: SUNRISE MEMORY CORPORATION
    Inventor: Eli Harari
  • Patent number: 11296728
    Abstract: An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises: performing first bit interleaving on a parity bits part of the LDPC codeword to obtain interleaved parity bits; splicing an information bit part of the codeword and the interleaved parity bits into a codeword after the first bit interleaving; dividing the codeword after the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding permutation order (bit-swapping pattern) to form a codeword after second bit interleaving; dividing the codeword after the second bit interleaving into two parts, and writing the two parts into storage space in a column order respectively and reading the two parts from the storage space in a row order respectively to obtain a codeword after third bit interleaving.
    Type: Grant
    Filed: September 27, 2020
    Date of Patent: April 5, 2022
    Assignee: Shanghai National Engineering Research Center of Digital Teievision Co., Ltd.
    Inventors: Wenjun Zhang, Yijun Shi, Dazhi He, Yunfeng Guan, Yin Xu, Xufeng Guo
  • Patent number: 11283542
    Abstract: An encoding circuit includes an allocator to allocate a symbol to bit-strings within a first frame, a converter to convert values of target-bit-strings that exclude a predetermined-bit-string so that, as a region within the constellation is closer to a center of the constellation, a number of symbols allocated in the region is larger, a generator to generate an error-correction-code of the bit-strings, and an insertion circuit to delay the error-correction-code and insert the error-correction-code in the predetermined-bit-string within a second frame that succeeds the first frame, wherein the allocator allocates, to the bit-strings, one symbol that corresponds to the values of the target-bit-strings, the one symbol being within a quadrant that corresponds to a value of the predetermined bit-string, and wherein the converter switches, based on the value of the predetermined-bit-string, association relationships between the values of the target-bit-strings before and after the conversion.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: March 22, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Yohei Koganei, Kiichi Sugitani
  • Patent number: 11283471
    Abstract: A bit-interleaved coded modulation (BICM) reception device and a BICM reception method are disclosed herein. The BICM reception device includes a demodulator, a bit deinterleaver, and a decoder. The demodulator performs demodulation corresponding to 1024-symbol mapping. The bit deinterleaver performs group-unit deinterleaving on interleaved values. The interleaved values are generated after the demodulation. The decoder restores information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving. The deinterleaved values corresponds to a LDPC codeword having a length of 64800 and a code rate of 2/15.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: March 22, 2022
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11269723
    Abstract: A memory controller controls a memory module including data chips and first and second parity chips. The memory controller includes an error correction code (ECC) engine. The ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder receives error information signals associated with the data chips, performs an ECC decoding on a codeword set from the memory module using the parity check matrix to generate a first syndrome and a second syndrome, and corrects bit errors in a user data set based on the error information signals and the second syndrome. The bit errors are generated by a row fault and uncorrectable using the first syndrome and the second syndrome. Each of the error information signals includes row fault information indicating whether the row fault occurs in at least one of memory cell rows in corresponding one of the data chips.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: March 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sanguhn Cha, Kijun Lee, Myungkyu Lee, Sunghye Cho
  • Patent number: 11271594
    Abstract: A transmitting device is described for a communication system. The transmitting device obtains an information message comprising information bits addressed for a receiving device and encodes the information message to obtain a codeword. The transmitting device rate-matches the codeword to produce a rate-matched codeword comprising systematic bits and parity-check bits. Furthermore, the transmitting device jointly interleaves the systematic bits and parity-check bits of the rate-matched codeword to obtain an interleaved codeword. The systematic bits of the interleaved codeword are mapped to modulation label positions of a modulation constellation with first reliabilities, and the parity-check bits of the interleaved codeword are mapped to modulation label positions of the modulation constellation with second reliabilities.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: March 8, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Anahid Robert Safavi, Alberto Giuseppe Perotti, Branislav M. Popovic
  • Patent number: 11265013
    Abstract: A transmitter is provided. The transmitter includes: a segmenter configured to segment information bits into a plurality of blocks based on one of a plurality of preset reference values; an outer encoder configured to encode each of the plurality of blocks to generate first parity bits; and a Low Density Parity Check (LDPC) encoder configured to encode each of the plurality of blocks and the first parity bits to generate an LDPC codeword including second parity bits, wherein the one of the preset reference values is determined depending on at least one of a code rate used to encode each of the plurality of blocks and the first parity bits and whether to perform repetition of at least a part of the LDPC codeword in the LDPC codeword.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: March 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Kyung-Joong Kim, Se-ho Myung
  • Patent number: 11265018
    Abstract: Embodiments of this application provide a method for processing information bits in a wireless communication network. A device obtains a Polar encoded bit sequence, then divide the Polar encoded bit sequence into g groups that are of equal length N/g, wherein g is 32. The device block interleaves the g groups to obtain an interleaved bit sequence according to a sequence S, wherein the sequence S comprises: group numbers of the g groups, wherein a group whose number is 0 is the first element in the sequence S, wherein a group whose number is 12 is the 17th element in the sequence S, wherein a group whose number is 31 is the 32nd element in the sequence S, wherein the S is an integer and output the interleaved bit sequence.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: March 1, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Gongzheng Zhang, Ying Chen, Yunfei Qiao, Yourui HuangFu, Rong Li
  • Patent number: 11264116
    Abstract: Several embodiments of systems incorporating memory sub-systems are disclosed herein. In one embodiment, a memory sub-system can include a memory component and a processing device configured to perform a background scan on a memory region of the memory component. In some embodiments, the background scan includes generating a bit error count (BEC) of a codeword saved on the memory region and saving statistical information corresponding to the BEC of the codeword to a histogram statistics log. In some embodiments, when the BEC of the codeword is greater than a BEC threshold, a refresh operation is scheduled for the memory region and/or logged. In these and other embodiments, when one or more error recovery error correction code (ECC) operations do not correct bit errors in the codeword, a refresh and/or retirement operation is schedule for the memory region and/or is logged.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Gerald L. Cadloni, Bruce A. Liikanen
  • Patent number: 11265019
    Abstract: The disclosed systems, structures, and methods are directed to encoding and decoding information for transmission across a communication channel. The method includes dividing the information between m parallel polar codes such that each of the m parallel polar codes includes a plurality of information bits, and splitting the information bits in each of the m parallel polar codes into a private part and a public part. The public part includes an information section and a repetition section, wherein the information bits of the public part are arranged in the information section. Bits in the information section of the public part of each of the m parallel polar codes are repeated in the repetition section of the public part of at least a second one of the m parallel polar codes.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: March 1, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hamid Ebrahimzad, Zhuhong Zhang
  • Patent number: 11258539
    Abstract: Technologies for performing encoding of data symbols for column read operations include a device having a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to obtain a data set to encode. The data set is defined by a set of data symbols. The circuitry is also configured to determine a set of codewords to encode the data symbols of the data set, including defining each codeword with a set bit distance of at least two from every other codeword in the set of codewords. Additionally, the circuitry is configured to write the data set to the memory as a function of the determined set of codewords.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: February 22, 2022
    Assignee: Intel Corporation
    Inventors: Wei Wu, Sourabh Dongaonkar, Jawad Khan
  • Patent number: 11245494
    Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver includes a block interleaver formed of a plurality of columns each comprising a plurality of rows, and the block interleaver is configured to divide the plurality of columns into at least two parts and interleave the LDPC codeword.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: February 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Se-ho Myung, Kyung-joong Kim
  • Patent number: 11239942
    Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder which encodes input bits including outer encoded bits to generate an LDPC codeword including the input bits and parity bits to be transmitted to a receiver in a current frame; a puncturer which punctures a part of the parity bits which is not transmitted in the current frame; and an additional parity generator which selects at least a part of the parity bits to generate additional parity bits transmitted to the receiver in a previous frame of the current frame, wherein a number of the additional parity bits is determined based on a number of the outer encoded bits and a number of the parity bits left after the puncturing.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: February 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Kyung-joong Kim, Se-ho Myung
  • Patent number: 11239865
    Abstract: Disclosed are devices, systems and methods for error correction decoding using an iterative decoding scheme. An error correction circuit includes a node processor to perform a plurality of iterations for updating values of one or more variable nodes and one or more check nodes using initial values assigned to the one or more variable nodes, respectively, a trapping set detector to detect a trapping set in at least one of the plurality of iterations by applying a predetermined trapping set determination policy, and a post processor to reduce at least one of the initial values or invert at least one of values of the variable nodes corresponding to an iteration in which the trapping set is detected, upon detection of the trapping set.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Jang Seob Kim
  • Patent number: 11237901
    Abstract: Apparatuses and methods related to correcting errors can include using FD decoders and AD decoders. Correcting errors can include receiving input data from the memory array, performing a plurality of operations associated with an error detection on the input data, and providing, based on processing the input data, output data, a validation flag, and a plurality of parity bits to a second decoder hosted by a controller coupled to the memory device.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Amato, Marco Sforzin
  • Patent number: 11232208
    Abstract: Methods, systems, and computer readable media for using variable metadata tags. A method occurs at a metadata processing system for enforcing security policies in a processor architecture. The method comprises: receiving, at the metadata processing system, a tag associated with a word in memory, wherein the tag indicates a memory location containing metadata associated with the word and wherein the tag length is at least in part determined using tag usage frequency; obtaining the metadata from the memory location, and determining, using the metadata, whether the word or a related instruction violates a security policy.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: January 25, 2022
    Assignee: THE TRUSTEES OF THE UNIVERSITY OF PENNSYLVANIA
    Inventors: Andre DeHon, Udit Dhawan, Nicholas Edward Roessler
  • Patent number: 11221789
    Abstract: When a plurality of write data is merged to generate a code for protecting data stored in the main memory, the write data is protected in the memory controller. A first code generation unit generates a first code based on the write data stored in a first sub memory, and stores the generated first code in a second sub memory. The sub memory controller reads the write data to be merged from the first sub memory, and verifies whether the read write data includes an error by using the first code stored in the second sub memory. When the read write data does not include an error, the sub memory controller merges valid data of the write data read from the first sub memory, and outputs the merged data to a second code generation unit. The second code generation unit generates a second code based on the merged data.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: January 11, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sho Yamanaka, Nobuhiko Honda, Takahiro Irita
  • Patent number: 11223441
    Abstract: Methods and apparatus for successive interference cancellation (SIC). In an embodiment, a method includes receiving symbols from a plurality of user equipment (UE), identify a target UE and non-target UEs, decoding code blocks from the symbols received from the non-target UEs to generate decoded bits for each code block. The method also includes performing a CRC check on each code block to generate a tag (0) when the CRC check passes and a tag (1) when the CRC check fails, and re-encoding the decoded bits to generate re-encoded code blocks having the associated tags attached. The method also includes reconstructing symbols from the re-encoded code blocks where symbols reconstructed from re-encoded code blocks having tag (0) are reconstructed with data and symbols reconstructed from re-encoded code blocks having tag (1) are reconstructed as zero value symbols, and utilizing the reconstructed symbols to cancel interference on symbols from the target UE.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: January 11, 2022
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Hong Jik Kim, Timothy Shee Yao, Nagabhushana Rao Kurapati
  • Patent number: 11218165
    Abstract: One embodiment provides a system and method for facilitating error-correction protection in a storage device. In response to a write request, the system organizes a block of data in a two-dimensional (2D) array, forms a plurality of first-dimension sub-blocks by dividing the 2D array along a first dimension, and forms a plurality of second-dimension sub-blocks by dividing the 2D array along a second dimension. In response to determining that second-dimension error correction code (ECC) encoding is enabled, the system performs second-dimension ECC encoding on the second-dimension sub-blocks to generate a set of second-dimension ECC bits and performs first-dimension ECC encoding on the first-dimension sub-blocks and the second-dimension ECC bits to generate a set of first-dimension ECC bits. The system writes the data block along with the second-dimension ECC bits and the first-dimension ECC bits to the storage device.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: January 4, 2022
    Assignee: Alibaba Group Holding Limited
    Inventors: Jian Chen, Ying Zhang
  • Patent number: 11200118
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may directly access a portion of memory array that is otherwise reserved for ECC functionality of a memory device. The memory array may correspond to a set of memory addresses, where each memory address of the set corresponds to a first portion of the memory array (e.g., user data plane) and to a second portion of the memory array (e.g., ECC plane). The second portion may be configured to store ECC data or second user data or metadata based on whether the ECC functionality is enabled or disabled. The memory device may determine a command directed to the memory address of the set is configured to access the first portion or the second portion based on a status of a pin associated with the command.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: December 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Todd M. Buerkle, Debra M. Bell, Joshua E. Alzheimer
  • Patent number: 11190210
    Abstract: A method for performing encoding on the basis of a parity check matrix of a LDPC code, according to one embodiment of the present invention, comprises the steps of: generating, by a terminal, a parity check matrix, wherein the parity check matrix corresponds to a characteristic matrix, each element of the characteristic matrix corresponds to a shift index value determined by a modulo operation between a corresponding element in a base matrix and a lifting value, and the base matrix is a 46×68 matrix; and performing, by the terminal, encoding of input data by using the parity check matrix, wherein the lifting value is associated with the length of the input data.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: November 30, 2021
    Assignee: LG Electronics Inc.
    Inventors: Ilmu Byun, Jinwoo Kim, Kwangseok Noh, Jongwoong Shin, Bonghoe Kim
  • Patent number: 11190219
    Abstract: An error correcting code (ECC) decoder for a non-volatile memory device is configured to decode data stored by the non-volatile memory device using a parity check matrix with columns of different column weights. The ECC decoder is further configured to artificially slow processing of one or more of the columns of the parity check matrix in response to column weights for the one or more columns satisfying a threshold.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: November 30, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ran Zamir, Dudy Avraham, Eran Sharon, Idan Alrod, Idan Goldenberg, Omer Fainzilber, Yuri Ryabinin, Yan Dumchin, Igal Mariasin, Eran Banani
  • Patent number: 11190528
    Abstract: This disclosure presents a technique to include a packet sequence number and an integrity check value (ICV) into a data frame while maintaining a total number of transmitted bytes. A transmitting device includes circuitry that generates the ICV, inserts a transmitter packet sequence number into the data frame that includes a data packet including a payload, the data packet following a preamble and an interpacket gap (IPG) following the data packet. The circuitry also inserts the ICV into the data frame, and transmits the data frame, wherein inserting the ICV into the data frame reduces a size of the IPG while maintaining a total number of bytes in the data frame. A receiving device includes circuitry that receives the data frame, compares a receiver packet sequence number to the transmitter packet sequence number, and determines whether the transmitter packet sequence number is valid based on the receiver packet sequence number.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: November 30, 2021
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Jeffrey Tzeng, Abhijit K. Choudhury, Alan Y. Kwentus
  • Patent number: 11184026
    Abstract: A memory controller is configured to perform first error correcting code (ECC) encoding on a plurality of first frames of data, generate a plurality of delta syndrome units corresponding, respectively, to the plurality of first frames of data, generate a delta syndrome codeword by performing second ECC encoding on the plurality of delta syndrome units, the delta syndrome codeword including one or more redundancy data units, perform third ECC encoding on at least one second frame of data such that the encoded at least one second frame of data is a first vector of bits, and determine a second vector of bits such that, adding the second vector of bits to the first vector of bits forms a combined vector of bits which is an ECC codeword having a delta syndrome a value of which is pre-fixed based on at least one of the one or more redundancy data units.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: November 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Amit Berman, Ariel Doubchak
  • Patent number: 11182245
    Abstract: An operating method of a memory controller to update metadata using journaling data in a short time during a booting operation, and to maintain reliability of the updated metadata. The operating method of a memory controller includes loading metadata into sub-regions of a buffer memory, updating the metadata using journaling data in a state that error correction code (ECC) functions of memory controller for the sub-regions are disabled, generating a first parity data of data stored in the first sub-region, and enabling the ECC function of the first sub-region, after the first parity data is generated.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: November 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bo Mi Kim, Dong Gun Kim, Soo Hyun Kim, Ki Hyun Choi, Pil Chang Son
  • Patent number: 11171738
    Abstract: The invention relates to method and apparatus for improving the performance of communication systems using Run length Limited (RLL) messages such as the existing Automatic Identification System (AIS). A binary data sequence is Forward Error Correction (FEC) coded and then the sequence is compensated, for example by bit-erasure, so that either bit-stuffing is not required, or a bit stuffer will not be activated to ensure that the coded sequence meets the RLL requirement. Various embodiments are described to handle different architectures or input points for the FEC encoder and bit erasure module. The bit erasure module may also add dummy bits to ensure a RLL compliant CRC or to selectively add bits to a reserve buffer to compensate for later bit stuffing in a header. Additional RLL training sequences may also be added to assist in, receiver acquisition.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 9, 2021
    Assignee: Myriota Pty Ltd
    Inventors: Alexander James Grant, Andre Pollok, Gottfried Lechner, David Victor Lawrie Haley, Robert George McKilliam, Ingmar Rudiger Land, Marc Pierre Denis Lavenant
  • Patent number: 11169877
    Abstract: A method is disclosed for use in an electronic device having a non-volatile storage device and a volatile storage device, the method comprising: retrieving a first encoded data packet from a first address in the non-volatile storage device; decoding the first encoded data packet to obtain a first data item and a first error code corresponding to the first data item, the first encoded data packet being decoded by using a first coding key that is associated with the first address; detecting whether the first data item is corrupt based on the first error code and an error correction function, storing the first data item at a first address in the volatile storage device when the first data item is not corrupt, and transitioning the electronic device into a safe state when the first data item is corrupt.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: November 9, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventors: Nicolas Rigoni, Nicolás Rafael Biberidis, Ahmed Hassan Fahmy, Octavio H. Alpago
  • Patent number: 11171725
    Abstract: A mobile terminal is provided. The mobile terminal includes a light emitter, a light receiver, a light fidelity (LiFi) controller coupled with the light emitter and the light receiver, and a time-of-flight (TOF) controller coupled with the light emitter and the light receiver. The LiFi controller is configured to control the light emitter to emit a signal and control the light receiver to receive another signal. The TOF controller is configured to control the light emitter to emit a measurement light and determine a measured distance by performing distance measurement according to a reflected light of the measurement light received by the light receiver.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: November 9, 2021
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: Ye Zhang
  • Patent number: 11163500
    Abstract: Provided is a method for writing and deleting files on a tape medium and a cache storage device. The method includes receiving a command to write one or more files of a directory to a tape medium. The method further includes identifying a cache limit associated with the tape medium. The method further comprises determining whether the amount of data of the directory that is already on the cache storage device exceeds the cache limit. In response to the amount of data not exceeding the cache limit, the method includes writing data of the one or more files to the cache storage device and the tape medium in parallel.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Tohru Hasegawa, Hiroshi Itagaki, Tsuyoshi Miyamura, Noriko Yamamoto, Shinsuke Mitsuma
  • Patent number: 11152958
    Abstract: A data storage device has a controller that is configured to generate SECDED codes based on a plurality (at least 2) of codes, where each of the constituent codes is a cyclic code over a finite field of size 2m for some integer m. Any 2 constituent codes are associated with 2m1 and 2m2, where m1 and m2 are coprime (i.e., gcd(m1,m2)=1) where gcd is the greatest common divisor. In such a case, it is possible to generate a cyclic code of length (2m1?1)*(2m2?1), which will be a long code, but enjoy the complexity, in encoding and decoding, of the small fields of the constituent codes.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: October 19, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Ishai Ilani
  • Patent number: 11151251
    Abstract: A malicious code detection module identifies potentially malicious instructions in volatile memory of a computing device before the instructions are executed. The malicious code detection module identifies an executable file, including an .exe file, in memory, validates one or more components of the executable file against the same file stored in non-volatile storage, and issues an alert if the validation fails.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: October 19, 2021
    Assignee: Endgame, Inc.
    Inventor: Joseph W. Desimone
  • Patent number: 11145389
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control a persistent storage media including a first media to store one or more source blocks of data and a second media to store one or more destination blocks of data, determine if an error rate associated with a read of a particular destination block of the one or more destination blocks exceeds a threshold error rate, identify a particular source block of the one or more source blocks which corresponds to erroneous data in the particular destination block, determine which of the particular source block and the particular destination block is a failed block, and retire the failed block. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Shankar Natarajan, Sriram Natarajan, Arun S. Athreya, Venkata S. Surampudi
  • Patent number: 11144386
    Abstract: A memory controller includes an error correction circuit that converts some bits of first data into parity bits for an error correction operation and generates second data including remaining bits of the first data and the parity bits replaced from the some bits, and a physical layer that transmits the second data instead of the first data to a memory device.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: October 12, 2021
    Assignee: UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITY
    Inventors: Ik Joon Chang, Duy Thanh Nguyen
  • Patent number: 11139835
    Abstract: The embodiments of the present disclosure provide a method and an apparatus for data processing with structured LDPC codes. The method includes: obtaining a code block size for structured LDPC coding; determining a coding expansion factor z based on at least one of the code block size, a parameter kb of a basic check matrix, a positive integer value p or the basic check matrix having mb rows and nb columns; and encoding a data sequence to be encoded, or decoding a data sequence to be decoded, based on the basic check matrix and the coding expansion factor. The present disclosure is capable of solving the problem in the related art associated with low flexibility in data processing with LDPC coding and improving the flexibility in data processing with LDPC coding.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 5, 2021
    Assignee: ZTE CORPORATION
    Inventors: Liguang Li, Jun Xu, Jin Xu
  • Patent number: 11138065
    Abstract: A storage system has a controller with an encoder. The encoder is configured to perform first and second stages of an encoding process in parallel on pipelined data blocks. In this way, while the first stage of the encoding process is being performed on a first data block, the second stage of the encoding process is performed on a second data block.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: October 5, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ran Zamir, Alexander Bazarsky, Eran Sharon
  • Patent number: 11133894
    Abstract: The present disclosure relates to information transmission method, decoding method, and apparatus. One example method includes encoding, by a sending device, a to-be-encoded sequence based on preset parameters to obtain an encoded sequence, where the preset parameters include a quantity of check bits, positions of the check bits, and a check equation, and sending the encoded sequence to a receiving device.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: September 28, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Huazi Zhang, Rong Li, Yunfei Qiao, Hejia Luo, Gongzheng Zhang, Ying Chen
  • Patent number: 11128315
    Abstract: Devices and methods for error correction are described. An exemplary error correction decoder includes a mapper configured to generate, based on a first set of read values corresponding to a first codeword, a first set of log likelihood ratio (LLR) values; a first buffer, coupled to the mapper, configured to store the first set of LLR values received from the mapper; and a node processor, coupled to the first buffer, configured to perform a first error correction decoding operation using the first set of LLR values received from the first buffer, wherein a first iteration of the first error correction decoding operation comprises refraining from updating values of one or more variable nodes, and performing a syndrome check using a parity check matrix and sign bits of the first set of LLR values stored in the first buffer.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: September 21, 2021
    Assignee: SK hynix Inc.
    Inventors: Myung Jin Jo, Dae Sung Kim, Wan Je Sung
  • Patent number: 11128320
    Abstract: This application relates to the communications field, and discloses an encoding method, a decoding method, an encoding apparatus, and a decoding apparatus. The encoding method includes: receiving a data bitstream; performing forward error correction FEC encoding on the data bitstream to obtain X Reed-Solomon RS outer codes, where each of the X RS outer codes includes N1 symbols, K1 of the N1 symbols are payload symbols; and performing FEC encoding on the X RS outer codes to obtain Y RS inner codes, where each of the Y RS inner codes includes N2 symbols, K2 of the N2 symbols are payload symbols. According to this application, error correction performance of FEC decoding can be improved.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: September 21, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yuchun Lu, Liang Li, Lin Ma
  • Patent number: 11119856
    Abstract: A method for storing data. The method includes receiving data to write to persistent storage, calculating parity values for a grid using the data, where each of the parity values is associated with one selected from of the Row Q Parity Group, the Row P Parity Group, the Column Q Parity Group, the Column P Parity Group, and the Intersection Parity Group. The method further includes writing the data to a data grid in the persistent storage, where the data grid is part of the grid, and writing the parity values for the grid to a portion of the grid, where the portion of the grid comprises physical locations associated with a Row Q Parity Group, a Row P Parity Group, a Column Q Parity Group, a Column P Parity Group, and an Intersection Parity Group, wherein the portion of the grid is distinct from the data grid.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: September 14, 2021
    Assignee: EMC IP Holding Company LLC
    Inventor: Jeffrey S. Bonwick
  • Patent number: 11115985
    Abstract: A physical broadcast channel (PBCH) transmission method and an apparatus. The method includes scrambling PBCH based on a first scrambling code of the PBCH, where the first scrambling code is one of four scrambling codes, where a combination of a second least significant bit and a third least significant bit of a system frame number (SFN) indicates one value of four values, and where the four scrambling codes have a one-to-one correspondence with the four values, and sending the PBCH to a terminal device.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: September 7, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jianqin Liu, Chuanfeng He
  • Patent number: 11115063
    Abstract: A flash memory controller is configured to decode a codeword. During the decoding process, the flash memory can check the decoding status of each codeword segment in the codeword and skip the decoding of a codeword segment whose decoding status is passed, thereby saving time decoding and also improving decoding efficiency. Even though only a part of the codeword segments in the codeword have been successfully decoded in the decoding process at the previous time, the flash memory controller can replace the part of the codeword segments in the codeword with the correct results obtained previously, and then decoding the re-formed codeword again. Accordingly, the decoding accuracy can be increased and the burden on the subsequent decoding process or data recovery can be reduced.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: September 7, 2021
    Assignee: SILICON MOTION, INC.
    Inventor: Shiuan-Hao Kuo