Abstract: A RAID distributed parity generation system includes a chassis housing a RAID subsystem coupled to storage devices. The RAID subsystem receives a write instruction including new primary data for a subset of the storage devices that it uses to generate first intermediate parity data that it provides in a parity data storage device. The RAID engine then causes a first primary data storage device that is not in the subset to generate second intermediate parity data using its first primary data and respective second primary data in second primary data storage device(s) that are not in the subset, and provide the second intermediate parity data in the first primary data storage device. The RAID subsystem then causes the parity data storage device to generate final parity data using the first intermediate parity data and the second intermediate parity data.

Abstract: Systems and devices can include a physical layer (PHY) that includes a logical PHY to support multiple interconnect protocols. The logical PHY can include a first set of cyclic redundancy check (CRC) encoders corresponding to a first interconnect protocol, and a second set of CRC encoders corresponding to a second interconnect protocol. A multiplexer can direct data to the first set or the second set of CRC encoders based on a selected interconnect protocol. The logical PHY can include a first set of error correcting code (ECC) encoders corresponding to the first interconnect protocol and a second set of ECC encoders corresponding to the second interconnect protocol. The multiplexer can direct data to the first set or the second set of ECC encoders based on the selected interconnect protocol. In embodiments, different CRC/ECC combinations can be used based on the interconnect protocol and the link operational conditions.

Abstract: Disclosed are methods and systems for using softbit decoding techniques in retransmission-based networks for error concealment of packets corrupted by bit-errors. The softbit decoding techniques derive softbit information from multiple corrupted hardbits of the retransmitted packet to aid a softbit decoder in decoding the packet. The approach realizes improved error concealment capability while maintaining a simple system architecture. A retransmission softbit module is inserted between a channel decoder used for channel-decoding and demodulating a compressed packet and the softbit decoder. The retransmission softbit module may derive an accumulated softbit packet from multiple corrupted copies of the packet received from the channel decoder, make bit decisions based on the accumulated softbit packet, and derive reliability information for the bit decisions. The bit decisions may be a majority decision packet (MDP) created using a majority voting scheme.

Abstract: A heterogeneous processing system including a host processor coupled to a host memory, a first processor coupled to a first memory, a second processor coupled to a second memory, multiple data transfer resources, and switch and bus circuitry that communicatively couples the host processor, the first processor, the second processor, and the data transfer resources. The host processor is configured to detect an application for execution by both the first processor and the second processor, to select one of multiple data transfer methods for transferring data between the first and second processors, and to configure the heterogeneous processing system based on the selected data transfer method. The data transfer methods include memory extension operation, one memory to memory transfer operation, and two memory to memory transfer operation using at least one intermediate host buffer.

Abstract: A coding method and apparatus for data communication are provided, and may be applied to a plurality of scenarios such as a metro network, a backbone network, and a data center interconnection. As an example method, a first codeword is formed, where the first codeword includes n image bits and n to-be-transmitted bits. The n image bits are selected from to-be-transmitted bits in m source codewords. The m source codewords are formed before the first codeword. Both n and m are positive integers, and n>m; The n to-be-transmitted bits in the first codeword are sent. The bit in the first codeword can be protected by a plurality of codewords generated at different moments. In addition, the bit in the codeword can be protected by different quantities of codewords.

Abstract: The present technology provides a controller for controlling a memory device comprising: a hard syndrome calculator configured to generate a hard syndrome of a hard data chunk received from the memory device; a delta syndrome calculator configured to generate a delta syndrome of a delta bit data received from the memory device, the delta bit data indicating a reliability of the hard data chunk; a soft syndrome generator configured to generate a soft syndrome of the hard syndrome and the delta syndrome; a data determinator configured to select, as hard decision data, one of the hard data chunk and a soft data chunk, the selected data chunk corresponding to a syndrome having a lowest syndrome weight; and an error corrector configured to perform an ECC decoding operation on the hard decision data.

Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

Abstract: Systems, devices, and methods for initiating an action based on location of a first device are provided. The first device, such as an earbud, includes a Bluetooth receiver. The Bluetooth receiver is configured to receive a wave signal transmitted by a second device, such as a smartphone. The first device further includes a processor. The processor is configured to calculate a location of the first device relative to the second device based on the wave signal. The processor is further configured to determine a zone status of the first device based on the location of the first device relative to the second device and a predetermined zone. The processor is further configured to initiate the action based on the zone status.

Abstract: A relay device includes a relay connected between a first communication network and a second communication network. The second communication network uses a communication protocol different from the first communication network. A first frame is transmitted in the first communication network, and has a first payload including control information, a first data ID for identifying the control information, and a data length code indicating a data length of the first payload. A second frame is transmitted in the second communication network, and has the first frame, a second data ID indicating that the first frame is included, and unique data stored in a predetermined storage area at a position behind the first frame. The relay recognizes the first frame without performing a frame recognition process on the data in the predetermined storage area when recognizing the first frame in the second frame on a basis of the data length code.

Abstract: Methods, systems, and computer readable media for measuring data integrity in time sensitive networks. An example method for testing a time sensitive network (TSN) device includes calculating a data integrity value for a preemptable frame. The method includes appending the data integrity value to an end of the preemptable frame and transmitting the preemptable frame to the TSN device, causing the TSN device to fragment the preemptable frame or to reassemble the preemptable frame after fragmentation. The method includes receiving the preemptable frame after traversing the TSN device and validating the data integrity value of the preemptable frame after traversing the TSN device.

Abstract: Quantum repeaters and network architectures use two concatenated quantum error correction codes to increase the transmission range of quantum information. A block of data qubits collectively encode a second-layer logical qubit according to a second-layer code concatenated with a first-layer code. A first-layer quantum repeater first-layer corrects each data qubit based on a first-layer syndrome extracted therefrom. The first-layer quantum repeater transmits these first-layer-corrected qubits to a second-layer quantum repeater via a quantum communication channel. The first-layer quantum repeater also transmits the first-layer syndromes to the second-layer quantum repeater via a classical communication channel. After extracting a second-layer syndrome from the first-layer-corrected qubits, the second-layer quantum repeater uses the first-layer syndromes and second-layer syndrome to second-layer correct the first-layer-corrected qubits.

Abstract: Techniques for storage-free message authentication for error-correcting-codes are disclosed. A storage controller of a storage device receives a request to encode a message in a format having an error-correcting code schema that generates a parity code. A key generator generates a pseudorandom transposition of the message and the parity code as a first part of a secret key. A pseudorandom character string is determined as a second part of the secret key. The output of the pseudorandom transposition and the pseudorandom character string are combined to generate the encoded message which is returned in response to the request. The secret key associated with the message is stored in non-volatile memory.

Abstract: The present invention provides an access controller, and a data transfer method. The access controller controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.

Abstract: A transmission apparatus includes a signal processing circuit configured to obtain information data bits to be transmitted; add known information data bits to the information data bits to generate first data blocks; perform error-correction coding on the first data blocks to generate first coded data blocks including parity data blocks such that the first coded data blocks satisfy a first code rate; remove the known information data bits from the first coded data blocks to generate second coded data blocks, the second coded data blocks satisfying a second code rate different from the first code rate; and modulate the second coded data blocks using a modulation scheme to generate a modulated signal, which is then transmitted. A number of the known information data bits depends on a number of the information data bits such that the first code rate is fixed regardless of the number of the information data bits.

Abstract: Example channel circuits, data storage devices, and methods for using an adjustable code rate based on an extendable parity code matrix are described. Data units may be read from a storage medium. Multiple sets of parity bits may be available for different data units, different sets of parity bits having a different number of parity bits corresponding to different parity matrices and desired code rates. A primary parity matrix may provide a base code rate and one or more extended parity matrices may provide increased code rates based on additional rows for increased decoding. Error correction code (ECC) decoding may be selectively performed based on the different sets of parity bits and corresponding parity matrices, resulting in the output of a decoded data units based on the data units from the read signal.

Abstract: Methods for diagnosing faults in memory periphery circuitry, computer readable media, and a test device for the same are provided. In one example, method is provided that includes receiving, at a test device, a first test syndrome from a memory device, the first test syndrome corresponds to a first test process executed by the memory device, wherein the memory device comprises a memory array and peripheral circuitry, and wherein the first test process is associated with a first circuit element of the peripheral circuitry; determining, by a processing device of the test device, a first fault associated with the first circuit element based on the first test syndrome; and diagnosing, by the processing device, the first fault to determine positional information of the first fault, the positional information is associated with the first circuit element.

Abstract: Provided is a radio communication device which can make Acknowledgement (ACK) reception quality and Negative Acknowledgement (NACK) reception quality to be equal to each other. The device includes: a scrambling unit (214) which multiplies a response signal after modulated, by a scrambling code “1” or “e?j(?/2)” so as to rotate a constellation for each of response signals on a cyclic shift axis; a spread unit (215) which performs a primary spread of the response signal by using a Zero Auto Correlation (ZAC) sequence set by a control unit (209); and a spread unit (218) which performs a secondary spread of the response signal after subjected to the primary spread, by using a block-wise spread code sequence set by the control unit (209).

Abstract: A device capable of operating in a wireless communication environment. The device may be configured to determine a plurality of control signaling bits. The device may determine a plurality of cyclic redundancy check (CRC) bits based on the plurality of control signaling bits. The device may apply a channel coding scheme to the plurality of control signaling bits and the plurality of CRC bits. The plurality of CRC bits may be distributed among the plurality of control signaling bits prior to applying the channel coding scheme. The device may transmit the channel coded plurality of control signaling bits and CRC bits.

Abstract: A manager includes an accepting unit that accepts a plurality of application IDs and a plurality of kinematic plans from a plurality of advanced driver assistance system (ADAS) applications; an arbitration unit that arbitrates the kinematic plans; and an output unit that outputs a motion request to an actuator system based on an arbitration result by the arbitration unit, the output unit outputting the motion request to the actuator system corresponding to the application ID.

Abstract: Devices and techniques for corrupted storage portion recovery in a memory device are described herein. A failure event can be detected during a garbage collection operation on a collection of storage portions (e.g., pages) in a memory array. Here, members of the collection of storage portions are being moved from a former physical location to a new physical location by the garbage collection operation. A reference to a former physical location of a possibly corrupt storage portion in the collection of storage portions can be retrieved in response to the failure event. Here, the possibly corrupt storage portion has already been written to a new physical location as part of the garbage collection operation. The possibly corrupt storage portion can then be rewritten at the new physical location using data from the former physical location.

Abstract: An LDPC decoder receives channel information and performs a bit flipping algorithm to correct unsatisfied checks with respect to a parity matrix H. The threshold condition for determining whether to flip a bit is a function of the channel information itself. A threshold Thk used to evaluate the threshold condition may vary between iterations based on the number of iterations, number of bits flipped in the previous iteration, and number of unsatisfied checks. A threshold Thki may be calculated for each bit position. Thki and the threshold condition may be a function of whether bit position i was flipped in a previous iteration. A binning approach for parameters of the threshold condition may be used to reduce hardware complexity.

Abstract: Embodiments of this application disclose provides a low density parity check (LDPC) channel encoding method for use in a wireless communications system. A communication device encodes an input bit sequence by using a LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. Embodiments of the application provide eight particular designs of the base matrix. The encoding method provided in the embodiments of the application can be used in various communications systems including the fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.

Abstract: The present disclosure relates to providing multiple error correction code protection levels in memory. One device includes an array of memory cells and an operating circuit for managing operation of the array. The operating circuit comprises an encoding unit configured to generate a codeword for a first error correction code (ECC) protection level and a second ECC protection level, and decoding unit configured to perform an ECC operation on the codeword at the first ECC protection level and the second ECC protection level. The codeword comprises payload data stored in a plurality of memory cells of the array, and parity data associated with the payload data stored in parity cells of the array.

Abstract: An LDPC decoder receives channel information and performs a bit flipping algorithm to correct unsatisfied checks with respect to a parity matrix H. The threshold condition for determining whether to flip a bit is a function of the channel information itself. A threshold Thk used to evaluate the threshold condition may vary between iterations based on the number of iterations, number of bits flipped in the previous iteration, and number of unsatisfied checks. A threshold Thki may be calculated for each bit position. Thki and the threshold condition may be a function of whether bit position i was flipped in a previous iteration. A binning approach for parameters of the threshold condition may be used to reduce hardware complexity.

Abstract: A method for encoding or transmitting. In some embodiments, the method includes forming a set of one or more unpunctured codewords by coding a plurality of payload bits at a mother code rate, removing a plurality of punctured bits from the set of one or more unpunctured codewords to form a set of one or more punctured codewords, and transmitting the set of one or more punctured codewords. In some embodiments, the number of punctured bits exceeds a first threshold, or the number of punctured bits exceeds a second threshold.

Abstract: In some embodiments, a wireless electronic device translation system includes a translator that includes a first antenna, a second antenna, and a controlling unit coupled to the first antenna and the second antenna. The translator may be configured to receive a wireless communication signal transmitted from a first electronic device at a first frequency, interpret a communication content from the wireless communication signal using a first communication protocol, translate the first communication content to be transmitted as a wireless translated signal using a second communication protocol, and transmit the wireless translated signal at a second frequency to be received by a second electronic device.

Abstract: Techniques for image data protection using cyclic redundancy checks are disclosed herein. Some of the techniques may include, at a processor, receiving image data that includes multiple lines of pixel data. The processor may also determine at least a first hash value representing a first line of pixel data of the multiple lines of pixel data and a second hash value representing a second line of pixel data of the multiple lines of pixel data. The processor may also send the image data to a computing device that is configured to determine, based at least in part on the first hash value and the second hash value, whether the image data is corrupt.

Abstract: A low density parity check (LDPC) channel encoding method is used in a wireless communications system. A communication device encodes an input bit sequence by using an LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. The base matrix may be one of eight exemplary designs. The encoding method can be used in various communications systems including fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.

Abstract: Systems and methods are disclosed for implementing a high performance decoder. In certain embodiments, an apparatus may comprise a decoder circuit configured to decode a codeword of bits, including: a check node processor configured to provide a plurality of check to variable (c2v) messages to a variable node processor in parallel, the plurality of c2v messages including log likelihood ratio (LLR) data related a parity sum of multiple bits of the codeword; the variable node processor configured to generate a decision vector based on the plurality of c2v messages; and a convergence checker circuit configured to determine whether the codeword has been decoded based on the decision vector and output decoded data when the codeword has been decoded.

Abstract: A method for product decoding within a data storage system includes receiving data to be decoded within a first decoder; performing a plurality of decoding iterations to decode the data utilizing a first decoder and a second decoder; and outputting fully decoded data based on the performance of the plurality of decoding iterations.

Abstract: According to some embodiments, a method of operation of a wireless transmitter in a wireless communication network comprises: encoding a set of information carrying data bits u of length K with a linear outer code to generate a set of outer parity bits p along with the data bits u; interleaving the set of outer parity bits p and the data bits u using a predetermined interleaving mapping function that depends on the number of data bits K and is operable to distribute some bits of the set of parity bits p in front of some data bits u; and encoding the interleaved bits using a Polar encoder to generate a set of encoded bits x. Various interleaving mapping functions are disclosed.

Abstract: Systems and methods are disclosed for implementing a low latency decoder. In certain embodiments, an apparatus may comprise decoder configured decode a codeword of bits, including: a variable node processor configured to provide a plurality of variable-to-check (v2c) message vectors to the edge combiner in parallel, the plurality of v2c message vectors including estimates for a selected set of bits of the codeword; the edge combiner configured to generate a plurality of output message vectors for a plurality of check node vectors based on the plurality of v2c message vectors, and provide the plurality of output message vectors to the plurality of check node vectors simultaneously; a check node processor configured to update the plurality of check node vectors based on the plurality of output message vectors; and a convergence checker circuit configured to detect a valid code word based on bit value estimates from the variable node processor.

Abstract: A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.

Abstract: Techniques regarding quantum error mitigation are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an error mitigation component that can add a set of scaled quantum gates to a quantum circuit for error mitigation. The set of scaled quantum gates can comprise a quantum gate and an inverse of the quantum gate. Also, the set of scaled quantum gates can have a rotation angle based on a pulse schedule to achieve a target stretch factor.

Abstract: A method of operating a memory device is provided. The method includes: receiving a first command from a controller; activating a page of a memory cell array based on the first command; reading data of the activated page; detecting an error from the read data; correcting the detected error to generate error correction data; writing back the error correction data to the activated page in based on the detected error being a single-bit error; and blocking write-back of the error correction data to the activated page based on the detected error being a multi-bit error.

Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

Abstract: A method for generating and processing a broadcast signal according to an embodiment of the present invention includes encoding broadcast data for one or more broadcast services, encoding first level signaling information including information describing properties of the one or more broadcast services, encoding second level signaling information including information for scanning the one or more broadcast services and generating a broadcast signal including the broadcast data, the first level signaling information and the second level signaling information, wherein the first level signaling information includes user service description (USD) information describing service layer properties with respect to the broadcast services, wherein the USD information includes capability information specifying capabilities necessary to present broadcast content of the broadcast services.

Abstract: A memory controller determines the number of pieces of correction information of an a-th correction information for each of M component codes according to a value based on the number of component codes, and determines a correction information address which is an address on a correction information memory of the a-th correction information based on the number of pieces of correction information.

Abstract: Apparatus and method for functionally securely transfer data in a two-sided data exchange of safety-related data between two communication partners (A, B), wherein a mapping is defined, which assigns to a consumer ID a provider ID of the same end point in the case of each bidirectional connection, and the mapping is made known to the two end points a priori, where the mapping could consist of the one's complement or alternatively of the two's complement, and wherein the connection between the data provider and the data consumer is established as described, the data consumer receives the address identification of the data provider via an additional side channel, for example, and after the connection has been established, the identification of the data provider can be securely checked.

Abstract: A decoding method and device are provided. The method includes: decoding grouped original data in parallel by a first decoding unit to obtain grouped decoded data; decoding merged grouped decoded data by a second decoding unit to obtain decoded data; and if the sum of the lengths of the decoded data is an integer multiple of an upper limit of the decoding times of the second decoding unit, updating the first decoding unit and the second decoding unit, and if the sum of the lengths of the decoded data is not an integer multiple of the upper limit of the decoding times of the second decoding unit, updating the second decoding unit to obtain the decoded data again, until the sum of the lengths of the decoded data is equal to a decoding length, and merging the decoded data to serve as a decoding result of the original data.

Abstract: The disclosure relates to a method performed by a wireless device, for receiving system information from a network node of a wireless communication system. The system information is received in a synchronization signal (SS) block of an SS burst set comprising at least one SS block. The system information is multiplexed with information providing a time index indicating which SS block of the SS burst set that is being received. The method comprises receiving the information providing the time index, and receiving the system information, which comprises descrambling the system information using a scrambling sequence generated based on the information providing the time index. The method also comprises determining an accuracy of the information providing the time index, based on an error-detection code related to the received system information. The disclosure also relates to corresponding network node method and apparatus.

Abstract: A memory system includes a memory controller. The memory controller executes first calculation of obtaining a first degree to k-th degree error locator polynomials (1?k<t) by using a syndrome, determines whether error locations can be calculated by the error locator polynomials up to the k-th degree, obtains an initial value of a parameter to be used for second calculation of obtaining error locator polynomials up to t-th degree when it is determined that the error locations cannot be calculated, executes the second calculation using the initial value, calculates the error locations by using an error locator polynomial determined to be able to calculate the error locations among the first degree to k-th degree error locator polynomials or by using error locator polynomials obtained in the second calculation, and corrects errors in the calculated error locations.

Abstract: A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.

Abstract: A deduplication pipeline method to enable shorter overall latency, servicing of multiple calls in parallel, and implementing higher data compression ratio. The method includes receiving user data for storage, performing deduplication operation on the data to obtain non-duplicative data, buffering the non-duplicative data in persistent memory, and accepting next user data for deduplication processing. In parallel to receiving the next user data, operating a co-processor to asynchronously compressing the data stored in the persistent memory and storing the compressed data in RAID.

Abstract: A network device includes a switch chip and a CPU, wherein the switch chip at least includes a CPU interface, and the CPU at least includes a media access controller and a Buffer. The network device further includes a conversion apparatus. The conversion apparatus receives a first packet uploaded by the switch chip to the CPU through the CPU interface, obtains a second packet by migrating a private information header in an Ethernet header of the first packet to a specified position of the first packet, calculates a Cyclic Redundancy Check, CRC, code of the second packet, obtains a third packet by replacing a CRC code already carried in the second packet with the calculated CRC code, and sends the third packet to the Buffer on the CPU for buffering, wherein the specified position is a position other than the Ethernet header in the first packet.

Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

Abstract: Systems, devices, and methods for encoding information bits for storage, including encoding information bits and balance bits to obtain a first bit chunk of a first arrangement; permuting the first bit chunk to obtain a second bit chunk of a second arrangement; encoding the second bit chunk to obtain a third bit chunk of the second arrangement; permuting a first portion of the third bit chunk to obtain a fourth bit chunk of the first arrangement, and encoding the fourth bit chunk to obtain a fifth bit chunk of the first arrangement; permuting a second portion of the third bit chunk, and adjusting the balance bits based on the fifth bit chunk and the permutated second portion of the third bit chunk; adjusting the first arrangement based on the adjusted balance bits, and obtaining a codeword based on the adjusted first arrangement; and transmitting the codeword to a storage device.

Abstract: A transmitter is provided.

Abstract: A transmission device, a transmission method, a reception device, and a reception method for securing good communication quality in data transmission using an LDPC code. The LDPC coding is performed using a parity check matrix with the code length N of 17280 bits and the coding rate r of 13/16 or 14/16. The LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits. The information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix for every 360 columns.

Abstract: A CRC code is generated from an original data, a BCH code is generated with respect to the original data and the CRC code, and the original data, the CRC code, and the BCH code are recorded in pages selected from different planes of a plurality of memory chips. An RS code is generated from the original data across pages, a CRC code is generated with respect to the RS code, a BCH code is generated with respect to the RS code and the CRC code, and the RS code, the CRC code, the BCH code are recorded in a memory chip different from a memory chip including the original data. When reading data, error correction is performed on the original data by using the BCH code, and then CRC is calculated. If the number of errors is the number of errors that is correctable by erasure correction using the RS code, the original data is corrected by the erasure correction.