Error Correcting Code With Additional Error Detection Code (e.g., Cyclic Redundancy Character, Parity) Patents (Class 714/758)
  • Patent number: 10992315
    Abstract: A method includes: sending a first boundary bit block; sequentially sending an Ith bit block; determining a first parity check result and a second parity check result, where a check object of the first parity check result includes m consecutive bits of each bit block in the N bit blocks, a check object of the second parity check result includes n consecutive bits of each bit block in the N bit blocks, and at least one of m and n is greater than or equal to 2; and sending a second boundary bit block, the first parity check result, and the second parity check result.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: April 27, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xiaojun Zhang, Qiwen Zhong, Jing Huang, Min Zha
  • Patent number: 10990327
    Abstract: A memory controller includes an error correction code (ECC) module for performing ECC decoding based on read data received from a non-volatile memory device for performing an on-chip valley search (OVS) read operation. A read voltage modification module receives status bits representing a latch that latches the read data among a plurality of latches included in the non-volatile memory device to store result values of the OVS read operation and determine whether to change a read voltage based on the status bits when the ECC decoding is successfully performed.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: April 27, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Ryong Park
  • Patent number: 10992508
    Abstract: The disclosure relates to a method performed by a wireless device, for receiving system information from a network node of a wireless communication system. The system information is received in a synchronization signal (SS) block of an SS burst set comprising at least one SS block. The system information is multiplexed with information providing a time index indicating which SS block of the SS burst set that is being received. The method comprises receiving the information providing the time index, and receiving the system information, which comprises descrambling the system information using a scrambling sequence generated based on the information providing the time index. The method also comprises determining an accuracy of the information providing the time index, based on an error-detection code related to the received system information. The disclosure also relates to corresponding network node method and apparatus.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: April 27, 2021
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Jianfeng Wang, Asbjörn Grövlen, Henrik Sahlin
  • Patent number: 10985873
    Abstract: Example information transmission methods and devices are disclosed. One example method is applied to a network device and includes determining CRC bits of to-be-sent information bits, concatenating the CRC bits and the to-be-sent information bits to obtain a first information sequence, and interleaving bits in the first information sequence in an interleaving manner or scrambling the bits in the first information sequence in a scrambling manner, to obtain a second information sequence, to ensure that bits at locations of the CRC bits after a cyclic shift cannot check bits at locations of the to-be-sent information bits after the cyclic shift. A cyclic shift is performed on the second information sequence to obtain a third information sequence, where a quantity of cyclically shifted bits is used to carry information about some bits of a system frame number, and the third information sequence is sent.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: April 20, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Shengchen Dai, Gongzheng Zhang, Chen Xu, Hejia Luo, Yinggang Du
  • Patent number: 10983883
    Abstract: A method is performed at an electronic device that includes magnetic random access memory (MRAM). The method includes loading the MRAM with data including main data, first error correcting data, and second error correcting data. The MRAM comprises a plurality of MRAM cells characterized by a first magnetic anisotropy corresponding to a first error rate at a predefined temperature that exceeds a threshold for correcting errors using only the first error correcting data. The method further includes, after loading the MRAM with the data, heating the MRAM to the predefined temperature and correcting errors in the main data using both the first error correcting data and the second error correcting data. The method further includes after correcting the errors in the main data, erasing, from the MRAM, the second error correcting data and maintaining, on the MRAM, the first error correcting data.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: April 20, 2021
    Assignee: SPIN MEMORY, INC.
    Inventors: Michail Tzoufras, Marcin Gajek
  • Patent number: 10977116
    Abstract: A data access method, a memory control circuit unit and a memory storage device are provided. The method includes generating a first error correction code corresponding to received first data according to a first error correction encoding operation; and generating a second error correction code corresponding to received second data according to a second error correction encoding operation, wherein the second error correction code includes a first and a second partial error correction code. The method further includes writing the first data, the first error correction code and the second partial error correction code to a data bit area and a redundant bit area of a first physical programming unit respectively; and writing the second data and the first partial error correction code to the data bit area and the redundant bit area of a second physical programming unit respectively.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: April 13, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10978120
    Abstract: A memory interface circuit, a memory storage device and a signal generation method are provided. The memory interface circuit is configured to connect a volatile memory module and a memory controller. The memory interface circuit includes a clock generation circuit, a first interface circuit and a second interface circuit. The clock generation circuit is configured to provide a reference clock signal. The first interface circuit is configured to provide an address signal to the volatile memory module based on a first transition point of the reference clock signal. The second interface circuit is configured to provide a command signal to the volatile memory module based on a second transition point of the reference clock signal. The first transition point is one of a rising edge and a falling edge of the reference clock signal. The second transition point is the other one of the rising edge and the falling edge of the reference clock signal.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: April 13, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Ming-Chien Huang
  • Patent number: 10979080
    Abstract: The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 9/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: April 13, 2021
    Assignee: Saturn Licensing LLC
    Inventors: Ryoji Ikegaya, Makiko Yamamoto, Yuji Shinohara
  • Patent number: 10979078
    Abstract: A transmission method includes performing LDPC coding on a basis of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 3/16, and performing group-wise interleaving in which the LDPC code is interleaved in units of bit groups of 360 bits. The transmission method further includes mapping the LDPC code to one of 16 signal points of uniform constellation (UC) in 16QAM on a 4-bit basis. In the group wise interleaving, an (i+1)th bit group from a head of the LDPC code is set as a bit group i, and a sequence of bit groups 0 to 191 of the 69120-bit LDPC code is interleaved into a sequence of bit groups.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: April 13, 2021
    Assignee: SONY CORPORATION
    Inventors: Yuji Shinohara, Makiko Yamamoto
  • Patent number: 10970166
    Abstract: A memory system of an embodiment includes a memory controller and a non-volatile memory. The memory controller executes error correction encoding on user data received from a host to generate first encoded data, adds the first encoded data to each of one or more pieces of second encoded data, obtained by performing error correction encoding on each of one or more pieces of predetermined data, to generate one or more pieces of third encoded data, obtained by executing error mitigation encoding on the first encoded data, and selects any one piece of encoded data from the first encoded data and the one or more pieces of third encoded data. The non-volatile memory stores the selected encoded data.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: April 6, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Toshiyuki Yamagishi
  • Patent number: 10966591
    Abstract: A medical signal processing device 6 receives a picture signal imaged by a medical observation device 2 and processes the picture signal. The medical signal processing device 6 includes: a signal input unit 61 that receives the picture signal; a first signal converting unit 62 that converts the picture signal received by the signal input unit 61 from an RGB signal into a luminance signal and a color difference signal by performing a matrix calculating process; an identification information appending unit 63 that appends color gamut identification information related to a color gamut of the picture signal and corresponding to the matrix calculating process, to the picture signal resulting from the conversion; and a signal output unit 64 that outputs the picture signal to which the color gamut identification information has been appended, to either a medical display device 4 or a medical recording device provided externally.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: April 6, 2021
    Assignee: SONY OLYMPUS MEDICAL SOLUTIONS INC.
    Inventor: Takayuki Takeda
  • Patent number: 10970162
    Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: April 6, 2021
    Assignee: InterDigital Technology Corporation
    Inventor: Kyle Jung-Lin Pan
  • Patent number: 10965866
    Abstract: An image generation system according to an embodiment includes an acquisition unit, a first processing unit, and a second processing unit. The acquisition unit acquires first image data. The first processing unit generates second image data by subjecting the first image data, acquired by the acquisition unit, to a predetermined type of image processing. The second processing unit performs recognition processing on the second image data. The first processing unit and the second processing unit perform their respective processing in synchronization with each other without depending on an instruction from a processor.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: March 30, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Yudai Ishibashi
  • Patent number: 10963337
    Abstract: Devices and methods that generate code on chip-kill parity in which the code is generated and shortened using variable node degree information for improved decoding of data. In one aspect, memory controller comprises an encoder configured to construct a first code of D data bits and P parity bits, determine the number of distinct variable degree nodes L and the number of data bits of each of the variable degree nodes in the first code, and construct a second code that is shorter than the first code based on the determined number of variable degree nodes and the number of data bits of each of the variable degree nodes in the first code.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: March 30, 2021
    Assignee: SK hynix Inc.
    Inventors: Naveen Kumar, Aman Bhatia, Yu Cai, Chenrong Xiong, Fan Zhang
  • Patent number: 10963339
    Abstract: Methods, systems and devices for efficiently performing a read fail recovery operation are described. An exemplary data storage device includes a nonvolatile memory device including a page group in which program-completed pages and program-in-progress pages are mixed, a buffer memory configured to buffer data and an XOR parity to be stored in pages of the page group. The data storage device also includes a recovery circuit configured to recover an error of read-failed data, and a processor configured to control the recovery circuit to read data and an XOR parity corresponding to the program-in-progress pages from the buffer memory. The processor is also configured to recover the error of the read-failed data using data corresponding to remaining program-completed pages other than a page in which the read-failed data is stored among the program-completed pages, and the data and the XOR parity read from the buffer memory.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: March 30, 2021
    Assignee: SK hynix Inc.
    Inventors: Seung Gu Ji, Hyun Jun Lee, Byeong Gyu Park
  • Patent number: 10958530
    Abstract: A system for transmitting information over a network may include a server that generates random superpositions each including multiple packet fragments encoded using a Galois field and transmits them over multiple communication links to a client device. The packet fragments may be a plurality of fixed-size vectors that define the information to be transmitted. The server also may select a subset of the fixed-size vectors based on heuristics and generate a coefficient for each of the selected vectors. The coefficients may include any natural number. The superposition may be a sum of the selected fixed-size vectors multiplied by their associated coefficients. The server may repeat the process until the client acknowledges receipt of the information or another condition is met. The client device may then decode the received superposition, such as by solving the set of linear equations represented by the received superpositions. Other implementations also are described.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: March 23, 2021
    Assignee: Jump Algorithms, LLC
    Inventors: Kevin J. Bowers, Nicholas E. Bridge
  • Patent number: 10958587
    Abstract: Systems and methods of reducing transmission time are described. Uniform-sized original packets are generated from a data frame having a payload with an identifier and data. The packets include the identifier, total block number, block index that specifies an order of the packet, and the data. The packets are encoded to form redundant packets with the identifier, block number, block index and redundant data. The available block index for the original and redundant packets are different. The packets are transmitted by individual modems over different channels at transmission rates that are each configured to minimize free space in an input buffer of the modem and are dependent on feedback from the receiver. The feedback indicates a difference between the transmission rate and a reception rate. The encoding rate is dependent on the original packets over the original and redundant packets or a maximum transmission rate over the remaining transmission rates.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Andrey Belogolovy, Jeffrey Boyd, Hao Ruan, Longcheng Zhu
  • Patent number: 10944431
    Abstract: The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15 or 12/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: March 9, 2021
    Assignee: SATURN LICENSING LLC
    Inventors: Ryoji Ikegaya, Makiko Yamamoto, Yuji Shinohara
  • Patent number: 10944503
    Abstract: A network coding system. A packet decoding engine receives a number of received packets. A packet repository is coupled to the decoding engine to temporarily store the received packets. The packet decoding engine is configured to generate a decoding matrix by forming a sub-matrix by selecting columns of a network code matrix that have indices that are the same as the indices of the encoded packets that correspond to the selected received packets. The packet decoding engine is also configured to invert the sub-matrix to form the decoding matrix and multiply the received packet matrix by the decoding matrix to generate a recovered matrix where each column corresponds to a decoded packet.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: March 9, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Samantha Rose Summerson, Anuj Batra, Srinath Hosur, Georgios Angelopoulos
  • Patent number: 10944427
    Abstract: A data transmission method, a sending device, and a receiving device are provided. A sending device obtains information data, encodes the information data by using a quasi-cyclic low-density parity-check (LDPC) code matrix, modulates the encoded data to obtain first data, and sends the first data. A receiving device obtains second data, demodulates the second data to obtain to-be-decoded data, and decodes the to-be-decoded data by using a block matrix in an LDPC code matrix, where the block matrix is a submatrix in the quasi-cyclic LDPC matrix, and in the quasi-cyclic LDPC matrix, a row weight of a row (H?1) is greater than or equal to a row weight of a row H, or a row weight of a row (H?1) is less than or equal to a row weight of a row H. In this way, decoding efficiency can be improved.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: March 9, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Liang Ma, Yuejun Wei
  • Patent number: 10938417
    Abstract: The present invention provides an encoding circuit of a flash memory controller, wherein the encoding circuit includes an auxiliary data generating circuit and an encoder. In the operations of the encoding circuit, the auxiliary data generating circuit is configured to receive a plurality of data chunks to generate auxiliary data corresponding to the data chunks. The encoder is configured to encode the data blocks to generate parity codes according to a parity check matrix, and to use the auxiliary data to replace a portion of the parity codes to generate adjusted parity codes, wherein the data chunks and the adjusted parity codes are written into a flash.
    Type: Grant
    Filed: September 1, 2019
    Date of Patent: March 2, 2021
    Assignee: Silicon Motion, Inc.
    Inventor: Shiuan-Hao Kuo
  • Patent number: 10931312
    Abstract: The present technology relates to a transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 69120 bits is interleaved in units of 360-bit bit groups. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, in a case of performing data transmission using an LDPC code, and the like.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: February 23, 2021
    Assignee: SONY CORPORATION
    Inventors: Yuji Shinohara, Makiko Yamamoto
  • Patent number: 10929223
    Abstract: A memory controller is provided. The memory controller includes an error correction code (ECC) circuit configured to correct an error of a read codeword provided from a memory device, the ECC circuit including: a codeword combination generator configured to receive a first read codeword including a plurality of first read codeword bit values that are read from a first region of the memory device, generate a change codeword by changing values of one or more of the plurality of first read codeword bit values, and provide a codeword combination including the change codeword; and an ECC decoder including a plurality of ECC engines, wherein the ECC decoder is configured to perform ECC decoding in parallel on a plurality of codewords included in the codeword combination.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: February 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun Chu Oh, Young-Jin Cho, Young-Geun Lee
  • Patent number: 10915127
    Abstract: The invention relates to a parameterizable energy supply device comprising; a wireless communication interface for capturing parameterization data for arameterizing the parameterizable energy supply device by means of a communication network; and a processor which is designed to control at least one operational parameter of the parameterizable energy supply device based on the captured parameterization data.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: February 9, 2021
    Assignee: PHOENIX CONTACT GMBH & CO KG
    Inventors: Jochen Zeuch, Hartmut Henkel, Patrick Schweer
  • Patent number: 10915468
    Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: February 9, 2021
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Robert G. Blankenship, Suresh S. Chittor, Kenneth C. Creta, Balint Fleischer, Michelle C. Jen, Mohan J. Kumar, Brian S. Morris
  • Patent number: 10911220
    Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for storing blockchain data based on error correction code. One of the methods includes determining, by a blockchain node, block data associated with a current block of a blockchain; performing error correction coding of the block data to generate encoded data; dividing, based on one or more predetermined rules, the encoded data into a plurality of data sets; storing, based on the one or more predetermined rules, one or more data sets of the plurality of data sets; hashing each data set of remaining data sets of the plurality of data sets to generate one or more hash values corresponding to the remaining data sets; and storing the one or more hash values.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: February 2, 2021
    Assignee: Advanced New Technologies Co., Ltd.
    Inventor: Haizhen Zhuo
  • Patent number: 10908988
    Abstract: A storage apparatus includes: a controller; and a plurality of storage drives, wherein the controller issues a read command for specifying a value associated with an error correction mode to a first storage drive of the plurality of storage drives, the first storage drive selects the error correction mode associated with the value specified by the read command from a plurality of error correction modes, the plurality of error correction modes include a first error correction mode and a second error correction mode with a higher correcting capability and a longer maximum delay time than those of the first error correction mode, and the first storage drive executes a read of data from a storage medium in the selected error correction mode.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: February 2, 2021
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Date, Hideyuki Koseki, Akifumi Suzuki, Masahiro Tsuruya
  • Patent number: 10908992
    Abstract: A controller for controlling a memory device includes a read control component suitable for controlling a recovery soft read operation of the memory device on bits contained in error correction-failed data groups, when error correction on data of a target data group and error correction on one or more of data of corresponding data groups failed; an error correction code (ECC) component suitable for performing the error correction, and performing a selective data recovery operation on the target data group depending on reliabilities of the respective bits, derived as a result of the recovery soft read operation; and a read bias determiner suitable for determining a recovery soft read voltage to maximize the number of bits recovered by the selective data recovery operation, among bits contained in the target data group.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: February 2, 2021
    Assignee: SK hynix Inc.
    Inventor: Jae-Yoon Lee
  • Patent number: 10904228
    Abstract: An encoder for providing encrypted data for transmission via a transmission medium includes an encryption unit that is configured to encrypt data received at the encoder block by block and a processing unit. The processing unit is configured to randomly distribute an encrypted data block to a plurality of channels that are allocated to the transmission medium and to provide a sub-block, which includes part of the encrypted data block, to be transmitted via one of the channels, together with a channel identification allocated to the channel and a code value that is based on the encrypted data in the sub-block to be transmitted and the channel identification, for transmission via the allocated channel of the transmission medium.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: January 26, 2021
    Assignees: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V., timeproof gmbh
    Inventors: Olaf Feller, Ute Troppenz, Norbert Grote, Torsten Mehlhorn
  • Patent number: 10903855
    Abstract: The present disclosure provides a method, system, and terminal device for data transmission in an unlicensed spectrum, effectively reduce mutual signal interference between different systems while meeting regulation constraints on use of the unlicensed spectrum. The method in the present disclosure includes: at a processing start moment of a terminal device in a current channel occupancy time window of a network device, when remaining duration of the current channel occupancy time window of the network device is greater than or equal to duration for the terminal device to transmit a to-be-sent data packet to the network device, selecting based on a user attribute of the terminal device and from a mapping relationship between a user attribute and a transmission mode; and sending the to-be-sent data packet to the network device in the selected transmission mode.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: January 26, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Mo Li, Zhiyu Xiao
  • Patent number: 10901842
    Abstract: A memory system includes a memory controller including: a system error correction code generation circuit configured to generate a first system error correction code based on write data, and generate a second system error correction code based on the write data and the first system error correction code; and a memory including: a memory error correction code generation circuit configured to generate a memory error correction code based on the write data and the first system error correction code transferred from the memory controller; and a memory core configured to store the write data, the first system error correction code, the second system error correction code and the memory error correction code.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: January 26, 2021
    Assignee: SK hynix Inc.
    Inventors: Hoiju Chung, Young-Do Hur, Hyuk Lee, Jang-Ryul Kim
  • Patent number: 10897271
    Abstract: The disclosure relates in some aspects to multi-dimensional quasi-cyclic (QC) low-density parity-check (LDPC) code generation. In one example, a controller of a data storage apparatus determines a plurality of dimensions for a code, the plurality of dimensions comprising a plurality of coprime numbers, generates distinct circulant rotation values based on at least a root of unity number and a prime number, assigns a different one of the distinct circulant rotation values to each of a plurality of circulant locations defined within the plurality of dimensions to generate the code, and encodes data using the code.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: January 19, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Richard Leo Galbraith, Iouri Oboukhov, Niranjay Ravindran
  • Patent number: 10891187
    Abstract: A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure different blocks of the plurality of blocks of memory cells in different configurations, which can include blocks configured to include only groups of user data memory cells for storing user data, blocks configured to include only groups of overhead data memory cells for storing error correction code (ECC) data, and blocks configured to include groups of user data memory cells and groups of overhead data memory cells.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: William H. Radke, Tommaso Vali, Michele Incarnati
  • Patent number: 10886947
    Abstract: Various implementations are directed to systems and methods for maintaining integrity and reliability of data in an SSD device using error correction coding. According to certain aspects, for frames of data having an ECC code with two or more sub-codes, while one sub-decoder is not in use it could be used to start a decode of another frame. By “interleaving” and alternating the frames between sub-decoders, two or more frames can be decoded simultaneously in an efficient manner. This can clearly be extended to more sub-codes (i.e. dimensions greater than two).
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 5, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Paul Edward Hanham, David Malcolm Symons, Francesco Giorgio
  • Patent number: 10873344
    Abstract: The present technique relates to a transmission apparatus, a transmission method, a reception apparatus, and a reception method that can ensure favorable communication quality in data transmission using an LDPC code. LDPC coding is performed based on a check matrix of an LDPC code with a code length N of 69120 bits and a code rate r of 9/16 or 10/16. The LDPC code includes information bits and parity bits, and the check matrix includes an information matrix corresponding to the information bits and a parity matrix corresponding to the parity bits. The information matrix is represented by a check matrix initial value table. The check matrix initial value table is a table indicating positions of elements of 1 in the information matrix on the basis of 360 columns and is a predetermined table. The present technique can be applied to, for example, data transmission using the LDPC code.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: December 22, 2020
    Assignee: SONY CORPORATION
    Inventors: Yuji Shinohara, Makiko Yamamoto
  • Patent number: 10867633
    Abstract: Systems and methods are disclosed for reducing adjacent track erasure from write retry operations. In certain embodiments, an apparatus may comprise a circuit configured to abort a write operation while writing to a selected sector of a disc storage medium during a first revolution of the disc storage medium, and mark the selected sector as a temporary bad sector in a mapping table. The circuit may perform a write retry to continue the write operation starting at a next sector contiguously following the selected sector, without attempting to write the selected sector again, during a second revolution of the magnetic disc.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: December 15, 2020
    Assignee: Seagate Technology LLC
    Inventors: Xiong Liu, Brian T. Edgar, Feng Shen, Wenxiang Xie, Quan Li
  • Patent number: 10867239
    Abstract: A co-processor is configured for performing vector matrix multiplication (VMM) to solve computational problems such as partial differential equations (PDEs). An analog Discrete Fourier Transform (DFT) can be implemented by invoking VMM of input signals with Fourier basis functions using analog crossbar arrays. Linear and non-linear PDEs can be solved by implementing spectral PDE solution methods as an alternative to massively discretized finite difference methods, while exploiting inherent parallelism realized through the crossbar arrays. A digital controller interfaces with the crossbar arrays to direct write and read operations to the crossbar arrays.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: December 15, 2020
    Assignee: SPERO DEVICES, INC.
    Inventors: Jai Gupta, Nihar Athreyas, Abbie Mathew
  • Patent number: 10866855
    Abstract: A memory system includes a memory device and a memory controller. The memory device outputs data in response to a read command. The memory device includes a first function circuit which performs a first operation based on data stored in the memory device, in response to the read command, to generate first processed data. The memory controller provides the read command to the memory device in response to a read request received from a host. The memory controller receives status information associated with performing the first operation. The memory controller includes a second function circuit which performs a second operation based on the first processed data to generate second processed data. A manner of the second operation varies based on the status information.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: December 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyejeong Hong, Sanguhn Cha
  • Patent number: 10860258
    Abstract: A control circuit configured to associate a plurality of memory with an error correction scheme. The control circuit including an internal operation circuit configured to generate an internal command based on an access unit of the plurality of memory. The control circuit including a storage circuit configured to store information on the access unit of the plurality of memory.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventor: Won Ha Choi
  • Patent number: 10862620
    Abstract: A control unit of a multipath data transportation system that optimizes the load of the multiple communication paths of this system when the system transmits a data segment over these paths in parallel with forward error correction. The control unit determines an optimized number of packets to send over each path based on a prediction of quality for each path. The transmitted packets include systematic packets and coded packets.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: December 8, 2020
    Assignee: Dolby Laboratories Licensing Corporation
    Inventors: Mingchao Yu, Mark Craig Reed
  • Patent number: 10860415
    Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: December 8, 2020
    Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Om Ranjan, Riccardo Gemelli, Abhishek Gupta
  • Patent number: 10855405
    Abstract: Various aspects of the disclosure relate to retransmission techniques for communication of information (e.g., for wireless communication). In some aspects, if a device's first transmission including encoded data and parity information (subject to puncture) fails, the device's retransmission (e.g., in response to a NAK) involves transmitting the parity information that was punctured. In some aspects, the coding rate used for encoding the data for the first transmission is selected to meet an error rate (e.g., a block error rate) for the second transmission. The second transmission may also include repetition information that includes the encoded data. The repetition information could also include at least a portion of the encoded parity information.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: December 1, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Changlong Xu, Jian Li, Chao Wei, Chong Li, Joseph Binamira Soriaga, Jilei Hou
  • Patent number: 10846169
    Abstract: Semiconductor memory device includes a memory cell array and an interface circuit including an ECC engine. The memory cell array includes a normal cell region and a parity cell region including a first sub parity region and a second sub parity region. The interface circuit receives main data and sub data comprising external parity or a data mask signal, generates a flag signal based on mask bits of the data mask signal, performs ECC encoding operation on the main data in response to an operation mode and the flag signal, stores the main data in the normal cell region, stores either the external parity or the flag signal in the second sub parity region in response to the operation mode, performs an ECC decoding operation on the main data read from the normal cell region in response to the operation mode and the flag signal.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Nam-Sung Kim, Kyo-Min Sohn
  • Patent number: 10848272
    Abstract: Systems and method for error detection in automobile tell-tales are provided. An initial cyclic redundancy check (CRC) for a tell-tale to be calculated and stored at a primary control system within the vehicle. When a fault or condition is detected which generates the tell-tale, the primary control system passes video information to a display embedded control unit (ECU) along with the initial CRC. A circuit in the display ECU performs its own CRC calculation and compares the initial CRC to the calculated CRC. If there is not a match, then a fault indication may be provided to the primary control system for action by the primary control system. Still further, back up or fail-operational options may be invoked so that the tell-tale is provided to the operator.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: November 24, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Robert Hardacker, Rahul Gulati, Alex Jong
  • Patent number: 10846879
    Abstract: The present invention provides a methods, apparatus and systems for improving a systems-level data rate on a communications link such the orthogonal frequency division multiplexed multiple access (OFDMA) downlink used in used in WiFi and LTE cellular/wireless mobile data applications. The present invention preferably uses a form of multilevel coding and decoding known as tiled-building-block encoding/decoding. With the present invention, different receivers coupled to different parallel downlink channels with different channel qualities decode different received signal constellations at different levels of resolution. This allows the downlink of the OFDMA system to operate with a significantly higher data rate, thus eliminating existing inefficiencies in the downlink and significantly increasing system level bandwidth efficiency.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: November 24, 2020
    Inventors: Muhammad Ahsan Naim, John P. Fonseka
  • Patent number: 10826533
    Abstract: A method for decoding a cyclic code is disclosed. The method includes: determining a plurality of syndromes for the cyclic code; determining, by a hardware processor, a first coefficient and a second coefficient based on the plurality of syndromes; determining, by the hardware processor, a third coefficient based on the second coefficient; and generating an error-locator polynomial based on the first coefficient, the second coefficient, and the third coefficient.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: November 3, 2020
    Assignee: CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS
    Inventors: Yong Li, Hsin-Chiu Chang, Qianbin Chen, Trieu-Kien Truong
  • Patent number: 10826529
    Abstract: Systems and methods providing low-density parity-check (LDPC) decoder configurations capable of decoding multiple code blocks in parallel are described. Parallel LDPC decoders of embodiments can be reconfigured to simultaneously decode multiple codewords with reconfigurable size. In operation of embodiments of a parallel LDPC decoder, a plurality of active portions of the decoder logic are configured for parallel processing of a plurality of code blocks, wherein each active region processes a respective code block. The decoder logic active portions of embodiments are provided using a reconfigurable segmented scalable cyclic shifter supporting multiple instruction, multiple data (MIMD), wherein multiple individual different data shifts are implemented with respect to a plurality of code blocks in an instance of data shifting operation.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: November 3, 2020
    Assignee: Hong Kong Applied Science and Technology Research Institute Co., Ltd.
    Inventors: Hing-Mo Lam, Syed Mohsin Abbas, Zhuohan Yang, Zhonghui Zhang, Man-Wai Kwan, Ching-Hong Leung, Kong-Chau Tsang
  • Patent number: 10826652
    Abstract: The described technology is generally directed towards adaptive interleaving in network communications systems based on one or more conditions with respect to user equipment. When conditions such as the speed of the user equipment indicate that performance can be increased by interleaving the data traffic, data is transmitted to the user equipment using an adaptive interleaver in the coding chain of MIMO systems. The adaptive interleaver is not used when conditions indicate performance is unlikely to improve. Adaptive interleaving may be performed in the frequency domain, in the frequency and time domain, or the frequency time and space domain. Multiple interleavers with different interleaving patterns may be used in the frequency domain and in the frequency and time domain. Adaptive interleaving may be based on one or more various criteria corresponding to the condition data received from the user equipment.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: November 3, 2020
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: SaiRamesh Nammi, Arunabha Ghosh
  • Patent number: 10819372
    Abstract: Disclosed are a method for dividing a transport block of a low density parity check (LDPC) code and an apparatus therefor. A method for dividing a transport block of an LDPC code according to the present disclosure can improve the performance of the LDPC code by dividing the transport block using a minimum number of code blocks. In addition, it is possible to minimize shortening bits by making the size of some of the code blocks smaller than the size of the other code blocks. Further, it is possible to prevent performance degradation due to a minimum size code block by minimizing the number of the code blocks and performing shortening on a large size code block.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: October 27, 2020
    Assignee: LG Electronics Inc.
    Inventors: Kwangseok Noh, Bonghoe Kim, Jinwoo Kim, Ilmu Byun, Jongwoong Shin, Seunggye Hwang
  • Patent number: 10817180
    Abstract: An example apparatus includes a non-volatile memory including a first memory having a first write rate and a second memory having a second write rate, the first write rate greater than the second write rate An example controller is to determine, based on a ratio, a first portion of the data to be written to the first memory, and a second portion of the data to be written to the second memory type, the second portion of the data not included in the first portion of the data.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: October 27, 2020
    Assignee: Intel corporation
    Inventors: Yogesh B. Wakchaure, Xin Guo, David J. Pelster, Eric L. Hoffman