Abstract: Various embodiments described herein provide for in-service scanning and correction of stored data for achieving functional safety. For some embodiments, a data scanning and correction system periodically reads data from different portions (e.g., addresses) of a storage device (e.g., memory) implemented with ECC to detect any errors in the data. If an error is detected, the data scanning and correction system generates corrected data and rewrites the corrected data to the portion of the storage device. The data scanning and correction system may continuously cycle this process through different portions of the storage device to detect and correct errors while the storage device is in-service.

Abstract: According to certain embodiments, a method is provided for fast layered decoding for Low-density Parity-Check (LDPC) codes with a Parity-Check Matrix (PCM) that includes at least a first layer and a second layer. The method includes reading, from a memory, Variable Node (VN) soft information, wherein the VN soft information is associated with a message from a VN to a Check Node (CN) of the second layer of the PCM. A new CN to VN message is calculated from the CN of the second layer of the PCM. New VN soft information is calculated for the VN. The new VN soft information is calculated based on the VN soft information and a new CN to VN message from a CN of the first layer to the VN and an old CN to VN message from the CN of the first layer to the VN such that the updating of new VN soft information is delayed by at least one layer. The fast layered decoding has lower decoding latency and utilizes the decoding hardware more efficiently than standard layered decoding techniques.

Abstract: First data is received. First error-checking data generated based on a cyclic redundancy check (CRC) operation of the first data is received. Second data is generated by combining the first data with a first data pattern. Second error-checking data of the second data is generated by using a combination of the first error-checking data and a second data pattern. The second data pattern has a size that is based on the first data pattern.

Abstract: An information transmission method, a base station and a base station are provided. The information transmission method includes: judging whether a bit count of uplink control information UCI meets a predetermined bit count range; in a case that the bit count of the UCI meets the predetermined bit count range, determining, according to a reference cyclic redundancy check CRC bit count, a resource for transmitting UCI; transmitting the UCI on the determined resource for transmitting UCI.

Abstract: A memory controller generates error codes associates with write data and a write address and provides the error codes over a dedicated error detection code link to a memory device during a write operation. The memory device performs error detection, and in some cases correction, on the received write data and write address based on the error codes. If no uncorrectable errors are detected, the memory device furthermore stores the error codes in association with the write data. On a read operation, the memory device outputs the error codes over the error detection code link to the memory controller together with the read data. The memory controller performs error detection, and in some cases correction, on the received read data based on the error codes.

Abstract: An artifact is received from which features are extracted and used to populate a vector. The features in the vector are then reduced using a feature reduction operation to result in a modified vector having a plurality of buckets. Features within the buckets of the modified vector above a pre-determined projected bucket clipping threshold are then identified. Using the identified features, and overflow vector is then generated. The modified vector is then input into a classification model to generate a score. This score is adjusted based on the overflow vector and can then be provided to a consuming application or process. Related apparatus, systems, techniques and articles are also described.

Abstract: A method for configuring a computer system memory, includes powering on the computer system; retrieving options for initializing the computer system; assigning to a first segment of the memory a first pre-defined setting; assigning to a second segment of the memory a second pre-defined setting; and booting the computer system.

Abstract: In one embodiment, a controller predicts an occurrence of an event in a wireless network, based in part on a movement of a mobile node of the wireless network. The controller initiates application of network-layer forward error correction encoding to a stream of packets to be sent during the event between the mobile node and an access point of the wireless network, to form one or more encoded packets. The controller causes the one or more encoded packets to be transmitted in conjunction with the stream of packets during the event. The controller ceases application of the network-layer forward error correction encoding after the event has occurred.

Abstract: A decoding method of low-density parity-check (LDPC) codes based on partial average residual belief propagation includes the following steps: S1: calculating a size of a cluster ? in a protograph based on a code length m and a code rate of a target codeword; S2: pre-computing an edge residual rci?vj corresponding to each edge from a variable node to a check node in a check matrix H; S3: calculating, based on ?, a partial average residual (PAR) value corresponding to each cluster in the check matrix H; S4: sorting m/? clusters in descending order of corresponding PAR values, and updating an edge with a largest edge residual in each cluster; S5: updating edge information mci?vi from a check node ci to a variable node vj, and then updating a log-likelihood ratio (LLR) value L(vj) of the variable node vj; and S6: after the updating, making a decoding decision.

Abstract: Methods, apparatus, systems and articles of manufacture to determine and apply polarity-based error correction code are disclosed. In some examples, the methods and apparatus create an array by setting a first set of bit locations of a code word to have a first value and setting a second set of bit locations of the code word to have a second value different from the first value. In some examples, when the array satisfies a parity check, the methods and apparatus determine that bit locations having the first value from the array form a polarity-based error correction code.

Abstract: Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.

Abstract: Systems and methods are disclosed that are of retrieving, by a processing device, a codeword stored at a memory sub-system, determining parity data of the codeword, generating additional parity bits based on one or more bits of the parity data of the codeword, and generating host data by decoding the codeword using the additional parity bits.

Abstract: A user equipment (UE) may be configured to receive a signal in a time slot, wherein the signal includes a first reference signal, a second reference signal and data scrambled using a data scrambling sequence. Further, the first reference signal and the second reference signal are not scrambled using the data scrambling sequence. The second reference signal having a code sequence being a non-zero power of two in length and is time multiplexed with the data. The UE recovers the data of the received signal using the first or second reference signal.

Abstract: A method, apparatus, and system for level dependent error correction code protection in multi-level non-volatile memory. A write command to write data to a non-volatile memory array may be received. At least one multi-level page of multi-level storage cells may be determined for the write data. A coding rate for the write data of the at least one multi-level page may be determined based on an attribute of the at least one multi-level page. An ECC codeword may be generated that satisfies the coding rate and includes the write data. The ECC codeword may then be stored on the at least one multi-level page.

Abstract: A display panel driving apparatus includes an interface, a timing controller, a gate driver, and data driver. The interface includes a data determiner to determine whether or not input image data has a communication error and to process a packet of a data stream of the input image data, even though the input image data has the communication error. The timing controller receives the processed input image data from the interface and generates a data signal, a gate control signal, and a data control signal. The gate driver generates a gate signal based on the gate control signal. The data driver generates a data voltage based on the data control signal and the data signal.

Abstract: Implementations include providing a security rating and a data criticality value of one or more transactions, the one or more transactions to be recorded to a blockchain, and the blockchain being of a blockchain network, selecting a consensus protocol, the consensus protocol selected from a set of consensus protocols, and the consensus protocol selected based on the security rating and the data criticality value, defining a set of consensus nodes, the set of consensus nodes including nodes from one of a super node pool and a weak node pool, and executing, by the set of consensus nodes, the consensus protocol to record the one or more transactions to the blockchain.

Abstract: Methods and systems are presented for automatically verifying online content for different device configurations and/or account configurations. A request for verifying a user interface software workflow is received from a device. The request can specify particular parameters and content to see if that content appeared correctly when presented to users. Session data associated with one or more real-world user interaction sessions between user devices and a service provider server is obtained. The session data is used to generate data representing how one or more user interface elements are rendered on one or more user devices during the one or more real-world user interaction sessions. The data is comparable against benchmark data to determine if content was correctly presented. Reporting data can be made available that indicates if the user interface workflows are operating correctly.

Abstract: Methods, systems, and devices for code word formats and structures are described. A code word format and structure may include various fields that facilitate a reliable transaction of user data during an access operation associated with a memory medium. For example, the bit fields may include information directed to an error control operation for a port manager to perform on a code word configured in accordance with the code word format and structure. Additionally, the code word format and structure may be configured for low latency operation and reliable transaction of the user data during the access operation. For example, the port manager may receive a first portion of the code word and parse the first portion of the code word concurrently with receiving an additional portion of the code word.

Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM). Problematic patterns in a block of input data are identified, and the problematic patterns are relocated from an initial location to an erasure region of the block to generate a modified block. The modified block is erasure encoded into an erasure codeword, at least part of the erasure codeword is stored in the NVSM.

Abstract: Systems, apparatuses, and methods for implementing masked fault detection for reliable low voltage cache operation are disclosed. A processor includes a cache that can operate at a relatively low voltage level to conserve power. However, at low voltage levels, the cache is more likely to suffer from bit errors. To mitigate the bit errors occurring in cache lines at low voltage levels, the cache employs a strategy to uncover masked faults during runtime accesses to data by actual software applications. For example, on the first read of a given cache line, the data of the given cache line is inverted and written back to the same data array entry. Also, the error correction bits are regenerated for the inverted data. On a second read of the given cache line, if the fault population of the given cache line changes, then the given cache line's error protection level is updated.

Abstract: A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

Abstract: A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in a symbol and a second data path for a second bit (e.g., the most significant bit (MSB)) in the symbol. Each path may include a de-emphasis or pre-emphasis buffer circuit that inverts and delays signals received at the de-emphasis or pre-emphasis buffer circuit. The delayed and inverted data signals may control de-emphasis or pre-emphasis drivers that are configured to apply de-emphasis or pre-emphasis to a multi-level signal.

Abstract: An example apparatus includes a first communications module having a first transceiver. The first communications module is operable to transmit, using the first transceiver, a plurality of first groups of optical subcarriers to a plurality of second communications modules via free-space optical communication. The first groups of optical subcarriers carry first data, and each of the first groups of optical subcarriers is associated, respectively, with a different one of the second communications modules. The first communications module is also operable to receive, using the first transceiver, plurality of second groups of optical subcarriers from the second communications modules via free-space optical communication. The second groups of optical subcarriers carry second data and each of the second groups of optical subcarriers is associated, respectively, with a different one of the second communications modules.

Abstract: Embodiments of the present disclosure provide an encoding/decoding method, apparatus, and system. The method includes: encoding information bits to obtain a first-level encoded code word; obtaining a sorting value of each check bit of the first-level encoded code word, and adjusting each check bit to a corresponding position according to the sorting value of each check bit, where the sorting value refers to a value of S when the check bit is related to first S information bits of the information bits in the first-level encoded code word, and S is a non-zero integer; and performing second-level encoding on the first-level encoded code word after positions of the check bits are adjusted, thereby obtaining a second-level encoded code word. The present disclosure is applicable to various communication systems.

Abstract: One embodiment provides a system which facilitates data management. During operation, the system receives, by a storage device, a plurality of data blocks. The system compresses the data blocks to obtain compressed data blocks, and performs error correction code (ECC)-encoding on the compressed data blocks to obtain ECC-encoded data blocks. The system stores the ECC-encoded data blocks in a buffer prior to writing the ECC-encoded data blocks in a non-volatile memory of the storage device, and reorganizes an order of the ECC-encoded data blocks in the buffer to match a size of a physical page of the non-volatile memory. Responsive to a first set of the reorganized ECC-encoded data blocks filling a first physical page, the system writes the first set of the reorganized ECC-encoded data blocks to the first physical page.

Abstract: Provided are a partial pseudo-randomization processing method, a corresponding apparatus, a device and a storage medium. The method includes performing pseudo-randomization processing on part of N bits b1, b2, . . . , bN to generate new N bits d1, d2, . . . , dN; and encoding the d1, d2, . . . , dN.

Abstract: The present embodiment relates to a method and a system for data transmission and reception of a display device and, more specifically, to a method and a system for repeatedly checking whether an error has occurred in a data driving device configuration for high-speed communication when driving the display device to prevent the image quality degradation due to the configuration error.

Abstract: A memory controller that includes, in one implementation, a memory interface and a controller circuit. The memory interface is configured to interface with a non-volatile memory. The controller circuit is configured to receive a skewed codeword read from the non-volatile memory. The controller circuit is also configured to scan the skewed codeword by inserting or removing a quantity of bits at different locations in the skewed codeword and determining resulting syndrome weights of the skewed codeword. The controller circuit is further configured to determine an adjusted codeword by inserting or removing the quantity of bits at one of the different locations in the skewed codeword which results in a smallest syndrome weight. The controller circuit is also configured to decode the adjusted codeword.

Abstract: A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a connection destination of an input of the convolutional interleaver to one end of one of a plurality of branches; a FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a connection destination of an output of the convolutional interleaver to another end of one of the plurality of branches. The first and second switches switch the connection destination when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the connection destination sequentially and repeatedly among the plurality of branches.

Abstract: A communication device communicating with a base station, where the communication device includes: communication circuitry for performing wireless communication; and control circuitry for selectively switching between a first Physical Uplink Control CHannel (PUCCH) and a second PUCCH, each of the first PUCCH and second PUCCH for transmitting control information from the communication device to the base station. Here, a number of first symbols and a number of first resource blocks of the first PUCCH are different from a number of second symbols and a second number of resource blocks of the second PUCCH, and the first PUCCH and second PUCCH are allocated by the base station for use by the communication device during one or more predetermined periods.

Abstract: Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include performing a first error code correction (ECC) operation on a portion of data, performing a second ECC operation on the portion of data in response to the first ECC operation failing, and performing a third ECC operation on the portion of data in response to the second ECC operation failing.

Abstract: An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a first memory, a second memory, and a controller coupled to the first and second memories. The controller is configured to receive a transaction from a master, the transaction directed to the first memory and comprising an address; re-calculate an error correcting code (ECC) for a line of data in the second memory associated with the address; determine that a non-correctable error is present in the line of data in the second memory based on a comparison of the re-calculated ECC and a stored ECC for the line of data; and in response to the determination that a non-correctable error is present in the line of data in the second memory, terminate the transaction without accessing the first memory.

Abstract: A system for generating a parity check matrix for low-density parity-check (LDPC) codes includes a memory and a processing circuitry that retrieves a base matrix from the memory. The base matrix represents sets of valid and invalid positions for a set of circulant matrices. The processing circuitry determines a value for each valid position based on a heuristic function. The value for each valid position indicates a corresponding circulant matrix of the set of circulant matrices. The processing circuitry replaces each valid position with the corresponding circulant matrix based on the determined value, and each invalid position with a null matrix, to generate the parity check matrix. The parity check matrix thus generated has a high girth and equal distribution of cycles within the parity check matrix.

Abstract: An operation method of a storage controller which includes a nonvolatile memory device, the method including: collecting a first parameter indicating a degradation factor of a first memory area of the nonvolatile memory device and a second parameter indicating a degree of degradation occurring at the first memory area, in an initial driving period; selecting a first function model of a plurality of function models based on the first parameter and the second parameter and predicting a first error tendency of the first memory area based on the first function model; determining a first reliability interval based on the first error tendency; and performing a first reliability operation on the first memory area of the nonvolatile memory device based on the first reliability interval.

Abstract: Systems, apparatuses, and methods related to memory device protection are described. A quantity of errors within a memory device can be determined and the determined quantity can be used to further determine whether to utilize single or multiple memory devices for an error correction and/or detection operation. Multiple memory devices need not be utilized for the error correction and/or detection operation unless a quantity of errors within the memory device exceeds a threshold quantity.

Abstract: A computer-implemented method of storing an item of data across a plurality of storage media, the method comprising the steps of: receiving an item of data to be stored; splitting the item of data into N pieces of data; generating M redundancy pieces of data, usable to rebuild the item of data; storing each of the N pieces of data and M redundancy pieces of data on separate storage media of the plurality of storage media at a same offset within a file of the respective storage medium, the files of the storage media containing the N pieces of data and the M redundancy pieces of data being associated as a file set; and storing, separately to the N pieces of data and M redundancy pieces of data, the offset and the file set.

Abstract: Systems, methods, and apparatus related to data recovery in memory devices. In one approach, a memory device encodes stored data. The memory device reads a codeword from a storage media and determines that a number errors in the codeword exceeds an error correction capability of the memory device. The errors are due, for example, to one or more stuck bits. In response to this determination, one or more data patterns are written to the storage media at the same address from which the codeword is read. The data patterns are read to identify bit locations of the stuck bits. The identified locations are used to correct bit errors of the read codeword that correspond to the identified locations. The corrected code word is sent to a host device (e.g., which requested data from the memory device using a read command).

Abstract: Sub bands can be scheduled with optimal modulation and coding scheme (MCS) when the user equipment reports the sub band channel quality indicator (CQI) and sub band pre-coding matrix index (PMI). The network can use multiple downlink control channels to indicate the sub band resources and the corresponding MCS for that resource allocation. By using multiple downlink control channels to indicate the sub band MCS, the network can use resources more efficiently.

Abstract: Various implementations are directed to systems and methods for maintaining integrity and reliability of data in an SSD device using error correction coding. According to certain aspects, for frames of data having an ECC code with two or more sub-codes, while one sub-decoder is not in use it could be used to start a decode of another frame. By “interleaving” and alternating the frames between sub-decoders, two or more frames can be decoded simultaneously in an efficient manner. This can clearly be extended to more sub-codes (i.e. dimensions greater than two).

Abstract: Methods, systems, and devices for adaptive parity techniques for a memory device are described. An apparatus, such as a memory device, may use one or more error correction code (ECC) schemes, an error cache, or both to support access operations. The memory device may receive a command from a host device to read or write data. If the error cache includes an entry for the data, the memory device may read or write the data using a first ECC scheme. If the error cache does not include an entry for the data, the memory device may read or write the data without using an ECC scheme or using a second ECC scheme different than the first ECC scheme.

Abstract: According to one embodiment, a controller executes a first operation. The first operation includes reading a plurality of data units from a nonvolatile memory and executing a process on the read plurality of data units. The process includes an inverse conversion of a conversion applied to the plurality of data units and first decoding using the plurality of data units that has executed the inverse conversion. The controller acquires first information from one of the plurality of data units that has executed the first operation. The controller compares the acquired first information with an expected value of the first information and re-executes the first operation when the acquired first information and the expected value are not equal to each other.

Abstract: This invention presents a method and apparatus for vertical layered finite alphabet iterative decoding of low-density parity-check codes (LDPC) which operate on parity check matrices that consist of blocks of sub-matrices. The iterative decoding involves passing messages between variable nodes and check nodes of the Tanner graph that associated with one or more sub-matrices constitute decoding blocks, and the messages belong to a finite alphabet. Various embodiments for the method and apparatus of the invention are presented that can achieve very high throughputs with low hardware resource usage and power.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the method comprises: receiving data and a corresponding metadata from a host device; performing a CRC operation upon the data to generate a CRC code; encoding the metadata and the CRC code to generate an adjusted parity code; encoding the data and the adjusted parity code to generate encoded data, wherein the encoded data comprises the data, the adjusted parity code and an error correction code corresponding to the data and the adjusted parity code; and writing the encoded data and the metadata to a page of a block of a flash memory module.

Abstract: This application relates to communicating information between communication devices. A channel coding method is disclosed. A communication device obtains an input sequence of K bits. The communication device encodes the input sequence using a low density parity check (LDPC) matrix H, to obtain an encoded sequence. The LDPC matrix H is determined according to a base matrix and a lifting factor Z. The base matrix includes m rows and n columns, m is greater than or equal to 5, and n is greater than or equal to 27. The lifting factor Z satisfies a relationship of 22*Z?K. According to the encoding method provided in the embodiments, information bit sequences of a plurality of lengths can be encoded for transmission between the communication devices.

Abstract: Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.

Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

Abstract: Provided is a coding unit to determine the number of code block groups, divide an input bit sequence to code block segmentation into code block groups of the number of the code block groups, determine the number of code blocks for each of the code block groups, divide each of the code block groups into code blocks of the number of the code blocks, and apply channel coding to each of the code blocks.

Abstract: A control unit of a multipath data transportation system that optimizes the load of the multiple communication paths of this system when the system transmits a data segment over these paths in parallel with forward error correction. The control unit determines an optimized number of packets to send over each path based on a prediction of quality for each path. The transmitted packets include systematic packets and coded packets.

Abstract: A method for generating and processing a broadcast signal according to an embodiment of the present invention includes encoding broadcast data for one or more broadcast services, encoding first level signaling information including information describing properties of the one or more broadcast services, encoding second level signaling information including information for scanning the one or more broadcast services and generating a broadcast signal including the broadcast data, the first level signaling information and the second level signaling information, wherein the first level signaling information includes user service description (USD) information describing service layer properties with respect to the broadcast services, wherein the USD information includes capability information specifying capabilities necessary to present broadcast content of the broadcast services.

Abstract: A technique for communicating protocol data units, PDUs, in a radio communication from a transmitter (100) to a receiver (200) is described. As to a method aspect of the technique, one or more control messages indicative of Quality of Service, QoS, requirements for the radio communication are received. The QoS requirements include a control command for a reliability of the radio communication and a control command for a latency of the radio communication. A batch of redundant PDUs is transmitted from the transmitter (100) to the receiver (200). A number of the redundant PDUs per batch depends on the control command for the reliability and a temporal spread of the redundant PDUs per batch depends on the control command for the latency.