Error Correcting Code With Additional Error Detection Code (e.g., Cyclic Redundancy Character, Parity) Patents (Class 714/758)
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Patent number: 11928004Abstract: Techniques regarding quantum error mitigation are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an error mitigation component that can add a set of scaled quantum gates to a quantum circuit for error mitigation. The set of scaled quantum gates can comprise a quantum gate and an inverse of the quantum gate. Also, the set of scaled quantum gates can have a rotation angle based on a pulse schedule to achieve a target stretch factor.Type: GrantFiled: December 8, 2021Date of Patent: March 12, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nathan Don Earnest-Noble, Caroline Tornow, Daniel Josef Egger
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Patent number: 11929762Abstract: A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.Type: GrantFiled: August 1, 2022Date of Patent: March 12, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kangseok Lee, Geunyeong Yu, Youngjun Hwang, Hongrak Son, Junho Shin, Bohwan Jun, Hyunseung Han
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Patent number: 11929761Abstract: Systems and methods are disclosed for implementing a low latency decoder. In certain embodiments, an apparatus may comprise decoder configured decode a codeword of bits, including: a variable node processor configured to provide a plurality of variable-to-check (v2c) message vectors to the edge combiner in parallel, the plurality of v2c message vectors including estimates for a selected set of bits of the codeword; the edge combiner configured to generate a plurality of output message vectors for a plurality of check node vectors based on the plurality of v2c message vectors, and provide the plurality of output message vectors to the plurality of check node vectors simultaneously; a check node processor configured to update the plurality of check node vectors based on the plurality of output message vectors; and a convergence checker circuit configured to detect a valid code word based on bit value estimates from the variable node processor.Type: GrantFiled: October 7, 2022Date of Patent: March 12, 2024Assignee: Seagate Technology LLCInventor: Bengt Anders Ulriksson
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Patent number: 11921579Abstract: A method of operating a memory device is provided. The method includes: receiving a first command from a controller; activating a page of a memory cell array based on the first command; reading data of the activated page; detecting an error from the read data; correcting the detected error to generate error correction data; writing back the error correction data to the activated page in based on the detected error being a single-bit error; and blocking write-back of the error correction data to the activated page based on the detected error being a multi-bit error.Type: GrantFiled: March 11, 2022Date of Patent: March 5, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki-Heung Kim, Jun Hyung Kim, Chang-Yong Lee, Sang Uhn Cha, Kyung-Soo Ha
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Patent number: 11907139Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.Type: GrantFiled: December 20, 2022Date of Patent: February 20, 2024Assignee: Rambus Inc.Inventors: Chi-Ming Yeung, Yoshie Nakabayashi, Thomas Giovannini, Henry Stracovsky
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Patent number: 11888916Abstract: A method for generating and processing a broadcast signal according to an embodiment of the present invention includes encoding broadcast data for one or more broadcast services, encoding first level signaling information including information describing properties of the one or more broadcast services, encoding second level signaling information including information for scanning the one or more broadcast services and generating a broadcast signal including the broadcast data, the first level signaling information and the second level signaling information, wherein the first level signaling information includes user service description (USD) information describing service layer properties with respect to the broadcast services, wherein the USD information includes capability information specifying capabilities necessary to present broadcast content of the broadcast services.Type: GrantFiled: May 27, 2022Date of Patent: January 30, 2024Assignee: LG ELECTRONICS INC.Inventors: Minsung Kwak, Kyoungsoo Moon, Jangwon Lee, Woosuk Ko, Sungryong Hong
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Patent number: 11886738Abstract: A memory controller determines the number of pieces of correction information of an a-th correction information for each of M component codes according to a value based on the number of component codes, and determines a correction information address which is an address on a correction information memory of the a-th correction information based on the number of pieces of correction information.Type: GrantFiled: August 15, 2022Date of Patent: January 30, 2024Assignee: KIOXIA CORPORATIONInventors: Takahiro Kubota, Hironori Uchikawa, Yuta Kumano
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Patent number: 11863533Abstract: Apparatus and method for functionally securely transfer data in a two-sided data exchange of safety-related data between two communication partners (A, B), wherein a mapping is defined, which assigns to a consumer ID a provider ID of the same end point in the case of each bidirectional connection, and the mapping is made known to the two end points a priori, where the mapping could consist of the one's complement or alternatively of the two's complement, and wherein the connection between the data provider and the data consumer is established as described, the data consumer receives the address identification of the data provider via an additional side channel, for example, and after the connection has been established, the identification of the data provider can be securely checked.Type: GrantFiled: March 10, 2020Date of Patent: January 2, 2024Assignee: SIEMENS AKTIENGESELLSCHAFTInventors: Frank Schmid, Herbert Barthel, Thomas Markus Meyer, Walter Maximilian
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Patent number: 11848688Abstract: A decoding method and device are provided. The method includes: decoding grouped original data in parallel by a first decoding unit to obtain grouped decoded data; decoding merged grouped decoded data by a second decoding unit to obtain decoded data; and if the sum of the lengths of the decoded data is an integer multiple of an upper limit of the decoding times of the second decoding unit, updating the first decoding unit and the second decoding unit, and if the sum of the lengths of the decoded data is not an integer multiple of the upper limit of the decoding times of the second decoding unit, updating the second decoding unit to obtain the decoded data again, until the sum of the lengths of the decoded data is equal to a decoding length, and merging the decoded data to serve as a decoding result of the original data.Type: GrantFiled: September 22, 2020Date of Patent: December 19, 2023Assignee: SANECHIPS TECHNOLOGY CO., LTD.Inventors: Jialong Ding, Guangming Shi
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Patent number: 11838164Abstract: The disclosure relates to a method performed by a wireless device, for receiving system information from a network node of a wireless communication system. The system information is received in a synchronization signal (SS) block of an SS burst set comprising at least one SS block. The system information is multiplexed with information providing a time index indicating which SS block of the SS burst set that is being received. The method comprises receiving the information providing the time index, and receiving the system information, which comprises descrambling the system information using a scrambling sequence generated based on the information providing the time index. The method also comprises determining an accuracy of the information providing the time index, based on an error-detection code related to the received system information. The disclosure also relates to corresponding network node method and apparatus.Type: GrantFiled: November 5, 2020Date of Patent: December 5, 2023Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Jianfeng Wang, Asbjörn Grövlen, Henrik Sahlin
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Patent number: 11831330Abstract: A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.Type: GrantFiled: March 18, 2022Date of Patent: November 28, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Se-ho Myung, Belkacem Mouhouche, Daniel Ansorregui Lobete, Kyung-joong Kim, Hong-sil Jeong
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Patent number: 11831335Abstract: A memory system includes a memory controller. The memory controller executes first calculation of obtaining a first degree to k-th degree error locator polynomials (1?k<t) by using a syndrome, determines whether error locations can be calculated by the error locator polynomials up to the k-th degree, obtains an initial value of a parameter to be used for second calculation of obtaining error locator polynomials up to t-th degree when it is determined that the error locations cannot be calculated, executes the second calculation using the initial value, calculates the error locations by using an error locator polynomial determined to be able to calculate the error locations among the first degree to k-th degree error locator polynomials or by using error locator polynomials obtained in the second calculation, and corrects errors in the calculated error locations.Type: GrantFiled: June 15, 2022Date of Patent: November 28, 2023Assignee: Kioxia CorporationInventors: Naoaki Kokubun, Yuki Kondo, Hironori Uchikawa
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Patent number: 11809282Abstract: A deduplication pipeline method to enable shorter overall latency, servicing of multiple calls in parallel, and implementing higher data compression ratio. The method includes receiving user data for storage, performing deduplication operation on the data to obtain non-duplicative data, buffering the non-duplicative data in persistent memory, and accepting next user data for deduplication processing. In parallel to receiving the next user data, operating a co-processor to asynchronously compressing the data stored in the persistent memory and storing the compressed data in RAID.Type: GrantFiled: September 29, 2020Date of Patent: November 7, 2023Assignee: EMC IP HOLDING COMPANY LLCInventors: Shuguang Gong, Yong Zou, Jet Chen
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Patent number: 11765102Abstract: A network device includes a switch chip and a CPU, wherein the switch chip at least includes a CPU interface, and the CPU at least includes a media access controller and a Buffer. The network device further includes a conversion apparatus. The conversion apparatus receives a first packet uploaded by the switch chip to the CPU through the CPU interface, obtains a second packet by migrating a private information header in an Ethernet header of the first packet to a specified position of the first packet, calculates a Cyclic Redundancy Check, CRC, code of the second packet, obtains a third packet by replacing a CRC code already carried in the second packet with the calculated CRC code, and sends the third packet to the Buffer on the CPU for buffering, wherein the specified position is a position other than the Ethernet header in the first packet.Type: GrantFiled: November 26, 2019Date of Patent: September 19, 2023Assignee: New H3C Technologies Co., Ltd.Inventor: Yuewu Li
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Patent number: 11736125Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.Type: GrantFiled: May 13, 2022Date of Patent: August 22, 2023Assignee: STREAMSCALE, INC.Inventor: Michael H. Anderson
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Patent number: 11711099Abstract: Systems, devices, and methods for encoding information bits for storage, including encoding information bits and balance bits to obtain a first bit chunk of a first arrangement; permuting the first bit chunk to obtain a second bit chunk of a second arrangement; encoding the second bit chunk to obtain a third bit chunk of the second arrangement; permuting a first portion of the third bit chunk to obtain a fourth bit chunk of the first arrangement, and encoding the fourth bit chunk to obtain a fifth bit chunk of the first arrangement; permuting a second portion of the third bit chunk, and adjusting the balance bits based on the fifth bit chunk and the permutated second portion of the third bit chunk; adjusting the first arrangement based on the adjusted balance bits, and obtaining a codeword based on the adjusted first arrangement; and transmitting the codeword to a storage device.Type: GrantFiled: March 23, 2022Date of Patent: July 25, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Lior Kissos, Yaron Shany, Amit Berman, Ariel Doubchak
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Patent number: 11705985Abstract: A transmitter is provided.Type: GrantFiled: December 3, 2021Date of Patent: July 18, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hong-Sil Jeong, Kyung-Joong Kim, Se-ho Myung
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Patent number: 11700019Abstract: A transmission device, a transmission method, a reception device, and a reception method for securing good communication quality in data transmission using an LDPC code. The LDPC coding is performed using a parity check matrix with the code length N of 17280 bits and the coding rate r of 13/16 or 14/16. The LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits. The information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix for every 360 columns.Type: GrantFiled: October 17, 2018Date of Patent: July 11, 2023Assignee: SONY GROUP CORPORATIONInventors: Makiko Yamamoto, Yuji Shinohara
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Patent number: 11698851Abstract: A technique includes receiving, by a computer, user input representing creation of a first programmatic description of a first test object of source code to be tested. The technique includes, in response to receiving the user input, determining, by the computer, based on other programmatic descriptions of other test objects, a recommendation of a parameter to be used in the first programmatic description to identify the first test object. The technique includes causing, by the computer, a display of the recommendation.Type: GrantFiled: April 28, 2018Date of Patent: July 11, 2023Assignee: Micro Focus LLCInventors: Peng-Ji Yin, Cheng Hua, Jie Zhang
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Patent number: 11698748Abstract: A memory system according to the present technology may include a plurality of memory devices including a plurality of blocks configured of memory cells and a memory controller configured to control the plurality of memory devices corresponding to a plurality of zones by configuring the plurality of zones with the plurality of blocks included in each of the plurality of memory devices, wherein the memory controller is further configured to: receive a write request from a host, determine a target zone indicated by the write request among the plurality of zones, and determine a logical address of the target zone on which a write operation is to be started based on a write pointer and an offset corresponding to the target zone.Type: GrantFiled: May 4, 2021Date of Patent: July 11, 2023Assignee: SK hynix Inc.Inventors: Yu Jung Lee, Bo Kyeong Kim, Do Hyeong Lee, Min Kyu Choi
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Patent number: 11683677Abstract: A transmitter is configured to communicate with a multiplicity of receivers, and is configured to transmit first data, the first data including a non-unique addressing information addressing a subset of the multiplicity of receivers, the subset including at least two receivers, the transmitter further being configured to transmit second data, the second data including a further addressing information or transmitted according to a further addressing information, the addressing information addressing one receiver (or one group of receivers) of the subset of the multiplicity of receivers.Type: GrantFiled: September 3, 2019Date of Patent: June 20, 2023Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V.Inventors: Gerd Kilian, Josef Bernhard, Michael Schlicht, Jakob Kneißl, Frank Nachtrab, Johannes Wechsler, Dominik Soller
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Patent number: 11675655Abstract: Systems and methods for selecting an optimal error recovery procedure for correcting a read error in a solid-state drive are provided. A machine learning model is trained to forecast which error recovery procedure of a plurality of error recovery procedures is most likely to achieve a predetermined goal given a state of a solid-state drive. The predetermined goal is based on at least one of a read latency and a failure rate of the solid-state drive. A current state of the solid-state drive is determined. An error recovery procedure is selected from among the plurality of error recovery procedures by inputting the current state of the solid-state drive into the trained machine learning model, thereby triggering the trained machine learning model to output the selected error recovery procedure. The selected error recovery procedure is executed to recover data from the solid-state drive.Type: GrantFiled: March 10, 2022Date of Patent: June 13, 2023Assignee: Marvell Asia Pte, Ltd.Inventors: Phong Sy Nguyen, Dung Viet Nguyen, Christophe Therene, Nedeljko Varnica
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Patent number: 11671115Abstract: Methods and devices are disclosed for encoding source words and decoding codewords with LDPC matrices, comprising: receiving a 1×K source word row vector ?; and generating a 1×N codeword vector c=?·G, wherein G is a K×N generator matrix derived from a parity check matrix Hl; and wherein Hl is derived from a base parity check matrix H by summing different rows in the base parity check matrix H to obtain an intermediate parity check matrix, and applying a lifting matrix to the intermediate base parity check matrix to obtain Hl.Type: GrantFiled: July 30, 2021Date of Patent: June 6, 2023Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Guido Montorsi, Sergio Benedetto, Yan Xin, Min Yan
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Patent number: 11671114Abstract: Reduced complexity decoders with improved error correction and related systems, methods, and apparatuses are disclosed. An apparatus includes an input terminal and a processing circuitry. The input terminal is provided at a physical layer device to receive, from a network, a low density parity check (LDPC) frame including bits. The bits correspond to log-likelihood ratio (LLR) messages indicating probabilities that the bits have predetermined logic values. The processing circuitry is to saturate LLR values of a portion of the LLR messages corresponding to known bits of the LDPC frame to a highest magnitude value represented by the LLR messages, and pass the LLR messages between check nodes and message nodes. The message nodes correspond to the bits. The check nodes correspond to parity check equations of a parity check matrix.Type: GrantFiled: September 20, 2021Date of Patent: June 6, 2023Assignee: Microchip Technology IncorporatedInventor: Sailaja Akkem
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Patent number: 11664824Abstract: According to certain embodiments, a method is provided for fast layered decoding for Low-density Parity-Check (LDPC) codes with a Parity-Check Matrix (PCM) that includes at least a first layer and a second layer. The method includes reading, from a memory, Variable Node (VN) soft information, wherein the VN soft information is associated with a message from a VN to a Check Node (CN) of the second layer of the PCM. A new CN to VN message is calculated from the CN of the second layer of the PCM. New VN soft information is calculated for the VN. The new VN soft information is calculated based on the VN soft information and a new CN to VN message from a CN of the first layer to the VN and an old CN to VN message from the CN of the first layer to the VN such that the updating of new VN soft information is delayed by at least one layer. The fast layered decoding has lower decoding latency and utilizes the decoding hardware more efficiently than standard layered decoding techniques.Type: GrantFiled: January 9, 2018Date of Patent: May 30, 2023Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)Inventors: Amirpasha Shirazinia, Mattias Andersson, Magnus Malmberg, Sara Sandberg
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Patent number: 11663078Abstract: Various embodiments described herein provide for in-service scanning and correction of stored data for achieving functional safety. For some embodiments, a data scanning and correction system periodically reads data from different portions (e.g., addresses) of a storage device (e.g., memory) implemented with ECC to detect any errors in the data. If an error is detected, the data scanning and correction system generates corrected data and rewrites the corrected data to the portion of the storage device. The data scanning and correction system may continuously cycle this process through different portions of the storage device to detect and correct errors while the storage device is in-service.Type: GrantFiled: October 15, 2021Date of Patent: May 30, 2023Assignee: Ethernovia Inc.Inventors: Darren S. Engelkemier, Tom Quoc Wellbaum, Roy T. Myers, Jr., Hossein Sedarat
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Patent number: 11646094Abstract: A memory controller generates error codes associates with write data and a write address and provides the error codes over a dedicated error detection code link to a memory device during a write operation. The memory device performs error detection, and in some cases correction, on the received write data and write address based on the error codes. If no uncorrectable errors are detected, the memory device furthermore stores the error codes in association with the write data. On a read operation, the memory device outputs the error codes over the error detection code link to the memory controller together with the read data. The memory controller performs error detection, and in some cases correction, on the received read data based on the error codes.Type: GrantFiled: June 15, 2022Date of Patent: May 9, 2023Assignee: Rambus Inc.Inventors: Frederick A. Ware, John Eric Linstadt
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Patent number: 11646819Abstract: An information transmission method, a base station and a base station are provided. The information transmission method includes: judging whether a bit count of uplink control information UCI meets a predetermined bit count range; in a case that the bit count of the UCI meets the predetermined bit count range, determining, according to a reference cyclic redundancy check CRC bit count, a resource for transmitting UCI; transmitting the UCI on the determined resource for transmitting UCI.Type: GrantFiled: July 23, 2019Date of Patent: May 9, 2023Assignee: DATANG MOBILE COMMUNICATIONS EQUIPMENT CO., LTD.Inventor: Xuejuan Gao
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Patent number: 11645147Abstract: First data is received. First error-checking data generated based on a cyclic redundancy check (CRC) operation of the first data is received. Second data is generated by combining the first data with a first data pattern. Second error-checking data of the second data is generated by using a combination of the first error-checking data and a second data pattern. The second data pattern has a size that is based on the first data pattern.Type: GrantFiled: May 19, 2021Date of Patent: May 9, 2023Assignee: Micron Technology, Inc.Inventors: Ning Chen, Juane Li
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Patent number: 11636202Abstract: An artifact is received from which features are extracted and used to populate a vector. The features in the vector are then reduced using a feature reduction operation to result in a modified vector having a plurality of buckets. Features within the buckets of the modified vector above a pre-determined projected bucket clipping threshold are then identified. Using the identified features, and overflow vector is then generated. The modified vector is then input into a classification model to generate a score. This score is adjusted based on the overflow vector and can then be provided to a consuming application or process. Related apparatus, systems, techniques and articles are also described.Type: GrantFiled: February 21, 2020Date of Patent: April 25, 2023Assignee: Cylance Inc.Inventor: Eric Glen Petersen
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Patent number: 11615021Abstract: A method for configuring a computer system memory, includes powering on the computer system; retrieving options for initializing the computer system; assigning to a first segment of the memory a first pre-defined setting; assigning to a second segment of the memory a second pre-defined setting; and booting the computer system.Type: GrantFiled: May 30, 2019Date of Patent: March 28, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: Paul Dennis Stultz, James T Bodner, Kevin G Depew
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Patent number: 11606264Abstract: In one embodiment, a controller predicts an occurrence of an event in a wireless network, based in part on a movement of a mobile node of the wireless network. The controller initiates application of network-layer forward error correction encoding to a stream of packets to be sent during the event between the mobile node and an access point of the wireless network, to form one or more encoded packets. The controller causes the one or more encoded packets to be transmitted in conjunction with the stream of packets during the event. The controller ceases application of the network-layer forward error correction encoding after the event has occurred.Type: GrantFiled: March 24, 2021Date of Patent: March 14, 2023Assignee: Cisco Technology, Inc.Inventors: Alessandro Erta, Rupak Chandra
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Patent number: 11601138Abstract: A decoding method of low-density parity-check (LDPC) codes based on partial average residual belief propagation includes the following steps: S1: calculating a size of a cluster ? in a protograph based on a code length m and a code rate of a target codeword; S2: pre-computing an edge residual rci?vj corresponding to each edge from a variable node to a check node in a check matrix H; S3: calculating, based on ?, a partial average residual (PAR) value corresponding to each cluster in the check matrix H; S4: sorting m/? clusters in descending order of corresponding PAR values, and updating an edge with a largest edge residual in each cluster; S5: updating edge information mci?vi from a check node ci to a variable node vj, and then updating a log-likelihood ratio (LLR) value L(vj) of the variable node vj; and S6: after the updating, making a decoding decision.Type: GrantFiled: March 31, 2022Date of Patent: March 7, 2023Assignee: Sun Yat-sen UniversityInventors: Xingcheng Liu, Shuo Liang, Shizhan Cheng
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Patent number: 11601139Abstract: Methods, apparatus, systems and articles of manufacture to determine and apply polarity-based error correction code are disclosed. In some examples, the methods and apparatus create an array by setting a first set of bit locations of a code word to have a first value and setting a second set of bit locations of the code word to have a second value different from the first value. In some examples, when the array satisfies a parity check, the methods and apparatus determine that bit locations having the first value from the array form a polarity-based error correction code.Type: GrantFiled: November 12, 2019Date of Patent: March 7, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Manish Goel, Yuming Zhu
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Patent number: 11556421Abstract: Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.Type: GrantFiled: April 28, 2021Date of Patent: January 17, 2023Assignee: Texas Instruments IncorporatedInventors: Sandeep Rao, Karthik Ramasubramanian, Brian Paul Ginsburg
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Patent number: 11550663Abstract: Systems and methods are disclosed that are of retrieving, by a processing device, a codeword stored at a memory sub-system, determining parity data of the codeword, generating additional parity bits based on one or more bits of the parity data of the codeword, and generating host data by decoding the codeword using the additional parity bits.Type: GrantFiled: February 22, 2021Date of Patent: January 10, 2023Assignee: MICRON TECHNOLOGY, INC.Inventors: Tingjun Xie, Ying Yu Tai, Jiangli Zhu
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Patent number: 11552672Abstract: A user equipment (UE) may be configured to receive a signal in a time slot, wherein the signal includes a first reference signal, a second reference signal and data scrambled using a data scrambling sequence. Further, the first reference signal and the second reference signal are not scrambled using the data scrambling sequence. The second reference signal having a code sequence being a non-zero power of two in length and is time multiplexed with the data. The UE recovers the data of the received signal using the first or second reference signal.Type: GrantFiled: August 23, 2021Date of Patent: January 10, 2023Assignee: Intellectual Ventures Holding 81 LLCInventor: Nicholas William Anderson
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Patent number: 11527300Abstract: A method, apparatus, and system for level dependent error correction code protection in multi-level non-volatile memory. A write command to write data to a non-volatile memory array may be received. At least one multi-level page of multi-level storage cells may be determined for the write data. A coding rate for the write data of the at least one multi-level page may be determined based on an attribute of the at least one multi-level page. An ECC codeword may be generated that satisfies the coding rate and includes the write data. The ECC codeword may then be stored on the at least one multi-level page.Type: GrantFiled: March 26, 2021Date of Patent: December 13, 2022Assignee: Western Digital Technologies, Inc.Inventors: Nian Yang, Sahil Sharma, Harish Singidi
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Patent number: 11527185Abstract: A display panel driving apparatus includes an interface, a timing controller, a gate driver, and data driver. The interface includes a data determiner to determine whether or not input image data has a communication error and to process a packet of a data stream of the input image data, even though the input image data has the communication error. The timing controller receives the processed input image data from the interface and generates a data signal, a gate control signal, and a data control signal. The gate driver generates a gate signal based on the gate control signal. The data driver generates a data voltage based on the data control signal and the data signal.Type: GrantFiled: August 9, 2021Date of Patent: December 13, 2022Assignee: Samsung Display Co., Ltd.Inventor: Ho-Seok Han
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Patent number: 11520904Abstract: Implementations include providing a security rating and a data criticality value of one or more transactions, the one or more transactions to be recorded to a blockchain, and the blockchain being of a blockchain network, selecting a consensus protocol, the consensus protocol selected from a set of consensus protocols, and the consensus protocol selected based on the security rating and the data criticality value, defining a set of consensus nodes, the set of consensus nodes including nodes from one of a super node pool and a weak node pool, and executing, by the set of consensus nodes, the consensus protocol to record the one or more transactions to the blockchain.Type: GrantFiled: August 27, 2019Date of Patent: December 6, 2022Assignee: Accenture Global Solutions LimitedInventors: Prashant Sanghvi, Asmita Bhattacharya, Pravesh Kumar, Avishek Saha, Piyush Manocha, Rakesh Sharma
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Patent number: 11520513Abstract: Methods, systems, and devices for code word formats and structures are described. A code word format and structure may include various fields that facilitate a reliable transaction of user data during an access operation associated with a memory medium. For example, the bit fields may include information directed to an error control operation for a port manager to perform on a code word configured in accordance with the code word format and structure. Additionally, the code word format and structure may be configured for low latency operation and reliable transaction of the user data during the access operation. For example, the port manager may receive a first portion of the code word and parse the first portion of the code word concurrently with receiving an additional portion of the code word.Type: GrantFiled: October 20, 2020Date of Patent: December 6, 2022Assignee: Micron Technology, Inc.Inventor: Joseph T. Pawlowski
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Patent number: 11521210Abstract: Methods and systems are presented for automatically verifying online content for different device configurations and/or account configurations. A request for verifying a user interface software workflow is received from a device. The request can specify particular parameters and content to see if that content appeared correctly when presented to users. Session data associated with one or more real-world user interaction sessions between user devices and a service provider server is obtained. The session data is used to generate data representing how one or more user interface elements are rendered on one or more user devices during the one or more real-world user interaction sessions. The data is comparable against benchmark data to determine if content was correctly presented. Reporting data can be made available that indicates if the user interface workflows are operating correctly.Type: GrantFiled: May 13, 2020Date of Patent: December 6, 2022Assignee: PayPal, Inc.Inventor: Dieter Davis
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Patent number: 11513895Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM). Problematic patterns in a block of input data are identified, and the problematic patterns are relocated from an initial location to an erasure region of the block to generate a modified block. The modified block is erasure encoded into an erasure codeword, at least part of the erasure codeword is stored in the NVSM.Type: GrantFiled: June 11, 2021Date of Patent: November 29, 2022Assignee: Western Digital Technologies, Inc.Inventors: Iouri Oboukhov, Richard L. Galbraith, Jonas A. Goode
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Patent number: 11509333Abstract: Systems, apparatuses, and methods for implementing masked fault detection for reliable low voltage cache operation are disclosed. A processor includes a cache that can operate at a relatively low voltage level to conserve power. However, at low voltage levels, the cache is more likely to suffer from bit errors. To mitigate the bit errors occurring in cache lines at low voltage levels, the cache employs a strategy to uncover masked faults during runtime accesses to data by actual software applications. For example, on the first read of a given cache line, the data of the given cache line is inverted and written back to the same data array entry. Also, the error correction bits are regenerated for the inverted data. On a second read of the given cache line, if the fault population of the given cache line changes, then the given cache line's error protection level is updated.Type: GrantFiled: December 17, 2020Date of Patent: November 22, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Shrikanth Ganapathy, John Kalamatianos
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Patent number: 11500723Abstract: A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.Type: GrantFiled: April 22, 2020Date of Patent: November 15, 2022Assignee: STREAMSCALE, INC.Inventor: Michael H. Anderson
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Patent number: 11502881Abstract: A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in a symbol and a second data path for a second bit (e.g., the most significant bit (MSB)) in the symbol. Each path may include a de-emphasis or pre-emphasis buffer circuit that inverts and delays signals received at the de-emphasis or pre-emphasis buffer circuit. The delayed and inverted data signals may control de-emphasis or pre-emphasis drivers that are configured to apply de-emphasis or pre-emphasis to a multi-level signal.Type: GrantFiled: April 13, 2021Date of Patent: November 15, 2022Assignee: Micron Technology, Inc.Inventors: Feng Lin, Timothy M. Hollis
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Patent number: 11496217Abstract: An example apparatus includes a first communications module having a first transceiver. The first communications module is operable to transmit, using the first transceiver, a plurality of first groups of optical subcarriers to a plurality of second communications modules via free-space optical communication. The first groups of optical subcarriers carry first data, and each of the first groups of optical subcarriers is associated, respectively, with a different one of the second communications modules. The first communications module is also operable to receive, using the first transceiver, plurality of second groups of optical subcarriers from the second communications modules via free-space optical communication. The second groups of optical subcarriers carry second data and each of the second groups of optical subcarriers is associated, respectively, with a different one of the second communications modules.Type: GrantFiled: December 24, 2020Date of Patent: November 8, 2022Assignee: Infinera CorporationInventors: Steven Joseph Hand, Tulasi Veguru, Prasad Paranjape, Han Henry Sun
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Patent number: 11463111Abstract: Embodiments of the present disclosure provide an encoding/decoding method, apparatus, and system. The method includes: encoding information bits to obtain a first-level encoded code word; obtaining a sorting value of each check bit of the first-level encoded code word, and adjusting each check bit to a corresponding position according to the sorting value of each check bit, where the sorting value refers to a value of S when the check bit is related to first S information bits of the information bits in the first-level encoded code word, and S is a non-zero integer; and performing second-level encoding on the first-level encoded code word after positions of the check bits are adjusted, thereby obtaining a second-level encoded code word. The present disclosure is applicable to various communication systems.Type: GrantFiled: April 15, 2021Date of Patent: October 4, 2022Assignee: Huawei Technologies Co., Ltd.Inventors: Bin Li, Hui Shen
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Patent number: 11461173Abstract: One embodiment provides a system which facilitates data management. During operation, the system receives, by a storage device, a plurality of data blocks. The system compresses the data blocks to obtain compressed data blocks, and performs error correction code (ECC)-encoding on the compressed data blocks to obtain ECC-encoded data blocks. The system stores the ECC-encoded data blocks in a buffer prior to writing the ECC-encoded data blocks in a non-volatile memory of the storage device, and reorganizes an order of the ECC-encoded data blocks in the buffer to match a size of a physical page of the non-volatile memory. Responsive to a first set of the reorganized ECC-encoded data blocks filling a first physical page, the system writes the first set of the reorganized ECC-encoded data blocks to the first physical page.Type: GrantFiled: April 21, 2021Date of Patent: October 4, 2022Assignee: ALIBABA SINGAPORE HOLDING PRIVATE LIMITEDInventor: Shu Li
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Patent number: 11456819Abstract: Provided are a partial pseudo-randomization processing method, a corresponding apparatus, a device and a storage medium. The method includes performing pseudo-randomization processing on part of N bits b1, b2, . . . , bN to generate new N bits d1, d2, . . . , dN; and encoding the d1, d2, . . . , dN.Type: GrantFiled: May 28, 2019Date of Patent: September 27, 2022Assignee: ZTE CorporationInventors: Yuzhou Hu, Zhifeng Yuan, Weimin Li, Jianqiang Dai, Li Tian, Hong Tang