Error Correcting Code With Additional Error Detection Code (e.g., Cyclic Redundancy Character, Parity) Patents (Class 714/758)
  • Patent number: 10666386
    Abstract: One coding method is selected from a plurality of coding methods per data symbol group, an information sequence is encoded by using the selected coding method. The plurality of coding methods includes at least a first coding method and a second coding method. The first coding method is a coding method with a first coding rate for generating a first codeword as a first encoded sequence by using a first parity check matrix. The second coding method is a coding method with a second coding rate different from the first coding rate and obtained after puncturing processing, where a second encoded sequence is generated by performing the puncturing processing on a second codeword by using a second parity check matrix different from the first parity check matrix. A number of bits of the first encoded sequence is equal to a number of bits of the second encoded sequence.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: May 26, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yutaka Murakami, Tomohiro Kimura, Mikihiro Ouchi
  • Patent number: 10666390
    Abstract: A method of receiving a broadcast signal is disclosed. A method of receiving a broadcast signal according to an embodiment of the present invention includes synchronizing and orthogonal frequency division multiplexing (OFDM) demodulating a received broadcast signal, parsing a signal frame of the received broadcast signal, time deinterleaving broadcast data of the signal frame, forward error correction (FEC) decoding the broadcast data, and output formatting the broadcast data and outputting a data stream.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: May 26, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Jongseob Baek, Woosuk Ko
  • Patent number: 10664347
    Abstract: A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: May 26, 2020
    Assignee: STREAMSCALE, INC.
    Inventor: Michael H. Anderson
  • Patent number: 10666295
    Abstract: An apparatus includes an interface and a control circuit. The interface may be configured to process transfers to/from a medium. The control circuit may be configured to generate a trapping set list of trapping sets of a low-density parity check code, classify bit positions of the trapping sets as belonging to either a user bits field or a parity bits field of a codeword, encode data using the low-density parity check code to generate the codeword, and present the codeword to the interface to transfer the codeword to the medium. The generation of the codeword may include at least one of a shortening or a puncturing of bit locations in the codeword in response to the classifying of the bit positions of the trapping sets. All of the data may be held in the bit locations of the codeword other than the bit locations that are shortened or punctured.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: May 26, 2020
    Assignee: Seagate Technology LLC
    Inventors: Ludovic Danjean, Sundararajan Sankaranarayanan, Ivana Djurdjevic, AbdelHakim Alhussien, Erich F. Haratsch
  • Patent number: 10666296
    Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: May 26, 2020
    Assignee: STREAMSCALE, INC.
    Inventor: Michael H. Anderson
  • Patent number: 10651872
    Abstract: An in-between layer partial syndrome stopping (IBL-PS) criterion for a layered LDPC decoder. The IBL-PS syndrome is obtained by applying the parity checks (Hr,r+1) of a couple of a first layer (r) and a second layer (r+1) on the variables after the first layer has been processed and before the second layer is processed by the decoder, the decoding being stopped if said in-between layer syndrome (sr,r+1) is satisfied for at least a couple of consecutive layers.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: May 12, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, POLITECHNICA UNIVERSITY OF TIMISOARA, ECOLE NATIONALE SUPERIEURE DE L'ELECTRONIQUE ET APPLICATIONS(ENSEA), CY CERGY PARIS UNIVERSITE
    Inventors: Valentin Savin, Oana Boncalo, David Declercq
  • Patent number: 10637506
    Abstract: An apparatus and method for transmitting/receiving a Forward Error Correction (FEC) packet in a mobile communication system are provided. In the FEC packet transmission method, an FEC packet transmission apparatus transmits an FEC delivery block to an FEC packet reception apparatus. The FEC delivery block includes N payloads. Each of the N payloads includes a payload header. Each payload header included in each of C payloads among the N payloads includes packet oriented header information and an FEC delivery block oriented header information fragment. The packet oriented header information is applied to a related payload, and the FEC delivery block oriented header information fragment is generated by fragmenting FEC delivery block oriented header information applied to the N payloads.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sung-Hee Hwang
  • Patent number: 10635531
    Abstract: An error correction circuit of a semiconductor memory device including a memory cell array includes an error correction code (ECC) memory that stores an ECC and an ECC engine. The ECC is represented by a generation matrix. The ECC engine generates first parity data based on main data using the ECC, and corrects at least one error bit in the main data read from the memory cell array using the first parity data. The main data includes a plurality of data bits divided into a plurality of sub codeword groups. The ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub codeword groups. The column vectors have elements configured to restrict a location of a sub codeword group in which a mis-corrected bit occurs, in which the mis-corrected bit is generated due to error bits in the main data.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: April 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Myeong-O Kim
  • Patent number: 10623137
    Abstract: A transmission apparatus includes, a receiving circuit that receives a reception signal indicating a coded bit string, a decoding circuit that decodes and corrects the bit string by using a spatially-coupled low density parity check code constituted by arranging element matrixes stepwise in a diagonal direction, a parity check matrix of the spatially-coupled low density parity check code including at least one element matrix having at least one of a number of rows and a number of columns different from a number of rows and a number of columns of other element matrixes when each sparse matrix constituting the parity check matrix is regarded as an element matrix, and outputs the corrected bit string.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: April 14, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Yohei Koganei
  • Patent number: 10615909
    Abstract: This disclosure relates to the mobile communications field, and in particular, to data transmission technologies in the mobile communications field. In a data transmission method, a base station allocates, to a terminal, some of time domain symbols that are used for data transmission and that are in a scheduling period of the terminal, and the terminal performs data transmission based on the allocated time domain symbols. According to the method, time domain symbols in the scheduling period that originally belong to the terminal are punctured, a resource waste caused when the terminal occupies all time domain symbols that are used for data transmission and that are in the scheduling period during scheduling each time can be avoided, so that radio resources can be flexibly allocated based on requirements on delays and bandwidth, thereby improving resource utilization.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: April 7, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Hao Tang, Guohua Zhou
  • Patent number: 10607713
    Abstract: A memory device includes: a non-volatile memory circuit suitable for storing defective column information; a defective latch circuit suitable for receiving and storing the defective column information from the non-volatile memory circuit during a boot-up operation; an error correction code generation circuit suitable for generating an error correction code for correcting an error of the defective column information based on the defective column information; an error correction code latch circuit suitable for storing the error correction code; an error correction circuit suitable for correcting an error of the defective column information transferred from the defective latch circuit based on the error correction code which is transferred from the error correction code latch circuit so as to produce an error-corrected defective column information; and a memory bank suitable for performing a column repair operation based on the error-corrected defective column information.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: March 31, 2020
    Assignee: SK hynix Inc.
    Inventor: Sung-Ho Kim
  • Patent number: 10606689
    Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: March 31, 2020
    Assignee: SK hynix Inc.
    Inventors: Kang-Sub Kwak, Young-Jun Yoon, Joon-Yong Choi
  • Patent number: 10594439
    Abstract: This application provides an encoding method and apparatus in wireless communications between a network device and a terminal. The method includes: performing CRC encoding on A to-be-encoded information bits based on a CRC polynomial, to obtain a first bit sequence, where the first bit sequence includes L CRC bits and A information bits, L=11; and performing polar encoding on the first bit sequence. Based on an improved CRC polynomial, encoding satisfying an FAR requirement is implemented.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: March 17, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Lingchen Huang, Shengchen Dai, Chen Xu, Yunfei Qiao, Rong Li
  • Patent number: 10592332
    Abstract: An aspect includes a method for auto-disabling dynamic random access memory (DRAM) error checking based on a threshold. A method includes receiving data at a DRAM and executing error checking logic based on the data. The error checking logic detects an error condition in the data and it is determined, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached. The error checking logic is disabled at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edgar R. Cordero, Marc A. Gollub, Warren E. Maule, Lucas W. Mulkey, Anuwat Saetow
  • Patent number: 10580514
    Abstract: Log likelihood ratio (LLR) values that are computed in a flash memory controller during read retries change over time as the number of program-and-erase cycles (PECs) that the flash memory die has been subjected to increases. Therefore, in cases where an LLR table is used to provide pre-defined, fixed LLR values to the error-correcting code (ECC) decoding logic of the controller, decoding success and the resulting BER will degrade over time as the number of PECs to which the die has been subjected increases. In accordance with embodiments, a storage system, a flash memory controller for use in the storage system and method are provided that periodically measure the LLR values and update the LLR table with new LLR values. Periodically measuring the LLR values and updating the LLR table with new LLR values ensures high decoding success and a low BER over the life of the flash memory die.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: March 3, 2020
    Assignee: Seagate Technology LLC
    Inventors: Yunxiang Wu, Yu Cai, Zhengang Chen, Erich Haratsch
  • Patent number: 10582274
    Abstract: A method of processing transmission of a broadcast signal includes generating broadcast data for one or more broadcast services, generating first level signaling information including information for describing attribute for the one or more broadcast services, generating second level signaling information including information for listing the one or more broadcast services, generating link layer packets including the encoded broadcast data, the first level signaling information, and the second level signaling information, and generating a broadcast signal including the generated link layer packets.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: March 3, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Minsung Kwak, Jangwon Lee, Woosuk Kwon, Woosuk Ko, Kyoungsoo Moon, Sungryong Hong
  • Patent number: 10574394
    Abstract: An adaptive cyclic redundancy check process for uplink control information signaling is provided to allow a number of cyclic redundancy check bits to be adjusted based on the likelihood of data being corrupted during transmission. In an embodiment, a base station device can send a cyclic redundancy check length map to a mobile device that indicates to the mobile device to use a specific number of cyclic redundancy bits to use per a specified payload size of uplink control information. Optionally, the mobile device can determine a number of cyclic redundancy bits to include in the uplink control information, and use two stage uplink control information signaling to indicate to the base station how many cyclic redundancy check bits there are in the succeeding stage.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 25, 2020
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Xiaoyi Wang, SaiRamesh Nammi, Arunabha Ghosh
  • Patent number: 10575210
    Abstract: Certain aspects of the present disclosure provide methods and apparatus for managing cyclic redundancy check field lengths in wireless communications. An exemplary method generally includes determining a size of a cyclic redundancy check (CRC) field, from a plurality of possible sizes for a given type of physical wireless channel, to be used for a transmission to be sent on the physical wireless channel, and performing communication based on the transmission on the physical wireless channel with the CRC field of the determined size.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: February 25, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Wanshi Chen, Peter Gaal, Tingfang Ji
  • Patent number: 10574272
    Abstract: A memory system includes a nonvolatile memory and a memory controller configured to perform reading of a concatenation code from the nonvolatile memory in response to an external command, the memory controller including a decoder circuit which decodes a reception word in the concatenation code. The decoder circuit includes a first external code decoder that performs decoding on an external code portion, an internal code in-error bit estimation unit that performs estimation of an in-error bit on a bit sequence from the first external code decoder, based on a rule for an internal code in the concatenation code, and outputs a set of in-error bits that is obtained by the estimation, and a second external code decoder that performs decoding which uses the set of in-error bits that is output from the internal code in-error bit estimation unit, on the bit sequence from the first external code decoder.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: February 25, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuta Kumano, Kazumasa Yamamoto, Hironori Uchikawa, Akira Yamaga
  • Patent number: 10565039
    Abstract: A method and system for storing hints in poisoned data of a computer system memory includes receiving poisoned data in a component of the system; forwarding the poisoned data to a memory controller of the system; and forwarding additional data regarding the poisoned data to a memory controller. The memory controller writes the poisoned data to the system memory wherein the written poisoned data includes a poison signature and a hint based on the additional data regarding the poisoned data; and when the written poisoned data is read signaling a system error and returning the poison signature and the hint to a system software of the system.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: February 18, 2020
    Assignee: Intel Corporation
    Inventor: Thanunathan Rangarajan
  • Patent number: 10558606
    Abstract: Systems, apparatuses, and methods for reliably transmitting data over voltage scaled links are disclosed. A computing system includes at least first and second devices connected via a link. In one implementation, if a data block can be compressed to less than or equal to half the original size of the data block, then the data block is compressed and sent on the link in a single clock cycle rather than two clock cycles. If the data block cannot be compressed to half the original size, but if the data block can be compressed enough to include error correction code (ECC) bits without exceeding the original size, then ECC bits are added to the compressed block which is sent on the link at a reduced voltage. The ECC bits help to correct for any errors that are generated as a result of operating the link at the reduced voltage.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: February 11, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shomit N. Das, Matthew Tomei, Shrikanth Ganapathy, John Kalamatianos
  • Patent number: 10560118
    Abstract: Aspects of the present disclosure relate to low density parity check (LDPC) coding utilizing LDPC base graphs. Two or more LDPC base graphs may be maintained that are associated with different ranges of overlapping information block lengths. A particular LDPC base graph may be selected for an information block based on the information block length of the information block. Additional metrics that may be considered when selecting the LDPC base graph may include the code rate utilized to encode the information block and/or the lift size applied to each LDPC base graph to produce the information block length of the information block.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: February 11, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Joseph Binamira Soriaga, Gabi Sarkis, Shrinivas Kudekar, Thomas Richardson, Vincent Loncke
  • Patent number: 10554223
    Abstract: Input bits are encoded into codewords that include coded bits. Encoding involves applying a first set of polar encoding matrices GY of prime number dimension Y to the input bits to produce output bits, and applying a second set of polar encoding matrices GZ of prime number dimension Z to the output bits to produce the codeword. One or both of GX and GY could be non-2-by-2. Such kernel design and other aspects of code construction, including reliabilities and selection of sub-channels for code construction, non-CRC-aided error correction, and code shortening and puncturing, are discussed in further detail herein.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: February 4, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Yiqun Ge
  • Patent number: 10545805
    Abstract: A memory system, a reading method and a writing method are provided. The memory system includes a memory controller and a memory array electrically connected to the memory controller. A parity information is stored in the memory array. The memory array includes a plurality of memory devices. The reading method comprises the following steps: A reading command for requesting a user data stored in the memory array is received from a host interface. The user data is recovered according to the parity information when the user data is error at one of the memory devices. The user data, which is recovered, is transferred to the host interface and the user data is refreshed.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: January 28, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Shih-Chung Wang
  • Patent number: 10545804
    Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: January 28, 2020
    Assignee: Sony Corporation
    Inventors: Tatsuo Shinbashi, Keiichi Tsutsui, Hideaki Okubo, Lui Sakai, Kenichi Nakanishi, Yasushi Fujinami
  • Patent number: 10536240
    Abstract: This application provides a channel encoding method and apparatus in wireless communications. The method includes: performing CRC encoding on A to-be-encoded information bits, to obtain a first bit sequence, where the first bit sequence includes L CRC bits and A information bits; performing an interleaving operation on the first bit sequence, to obtain a second bit sequence, where a first interleaving sequence used for the interleaving operation is obtained based on a system-supported maximum-length interleaving sequence with the length of Kmax+L, and Kmax is a maximum information bit quantity corresponding to the maximum-length interleaving sequence and a preset rule, and a length of the first interleaving sequence is equal to A+L. Therefore, during distributed CRC encoding, when an information bit quantity is less than the maximum information bit quantity, an interleaving sequence required for completing an interleaving process is obtained based on the system-supported maximum-length interleaving sequence.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 14, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Lingchen Huang, Shengchen Dai, Chen Xu, Yunfei Qiao, Rong Li
  • Patent number: 10530393
    Abstract: A device includes a low density parity check (LDPC) decoder that is configured to receive a representation of a codeword. The LDPC decoder includes a circuit configured to set a message length of a decoding message at least partially based on an error metric associated with the representation of the codeword. The LDPC decoder also includes a processing unit including a first group of components and a second group of components. The processing unit configured to selectively couple the first group of components to the second group of components based on the message length of the decoding message.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: January 7, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yuri Ryabinin, Yan Dumchin
  • Patent number: 10528410
    Abstract: Techniques and mechanisms to identify an error to a host that controls a memory component based on communications based on a Mobile Industry Processor Interface (MIPI) Unified Protocol specification. In an embodiment, the memory component detects an error based on a data frame sent to the memory component from the host. In response to detecting the error, the memory device sends to the host a negative acknowledgment control (NAC) message including a negative acknowledgment identifier and an error code identifying an error type of the detected error. The NAC message is based on a NAC frame structure defined by the MIPI Unified Protocol specification. In another embodiment, the host receives the NAC message and stores error information based on the error code of the NAC message. The stored error information is accessible for purposes such as performance evaluation of the host and debugging.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: January 7, 2020
    Assignee: INTEL CORPORATION
    Inventor: Oshri Ben Hamo
  • Patent number: 10523240
    Abstract: Methods, apparatus, systems and articles of manufacture to determine and apply polarity-based error correction code are disclosed. In some examples, the methods and apparatus create an array by setting a first set of bit locations of a code word to have a first value and setting a second set of bit locations of the code word to have a second value different from the first value. In some examples, when the array satisfies a parity check, the methods and apparatus determine that bit locations having the first value from the array form a polarity-based error correction code.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: December 31, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Manish Goel, Yuming Zhu
  • Patent number: 10523239
    Abstract: A method for generating encoded data includes: generating at least one local LDPC matrix and a global LDPC matrix, the global LDPC matrix relating to each of the at least one local LDPC matrix; repeatedly selecting one of the at least one local LDPC matrix as a target local LDPC matrix until a number t of the target local LDPC matrices are selected, where t is a user-defined number that is greater than one; generating a block matrix that includes the target local LDPC matrices; generating a primary LDPC matrix that includes a first primary matrix part relating to the block matrix, and a second primary matrix part relating to the global LDPC matrix; and encoding data based on the primary LDPC matrix.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: December 31, 2019
    Assignee: National Chiao Tung University
    Inventors: Hsie-Chia Chang, Shu Lin, Yen-Chin Liao
  • Patent number: 10521299
    Abstract: Embodiments of the present disclosure relate to method and apparatus for data protection. For example, there is provided a computer-implemented method. According to the computer-implemented method, it only needs to read the changed data to be protected rather than the entire data to be protected during the procedure of generating a redundant data portion for the changed data to be protected.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: December 31, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Ronnie Yu Cai, Ao Sun, Gary Jialei Wu, Lu Lei, Chen Wang
  • Patent number: 10516683
    Abstract: Systems and methods for detection of security breaches in intravehicular communication systems are disclosed. In some embodiments, this may include intravehicular communication using messages sent with a checksum and a dynamic mathematical operator field. Errors in the checksum may be interpreted as ordinary transmission errors, whereas errors in the dynamic mathematical operator field may be interpreted as potential threats. Repeated errors in the dynamic mathematical operator, and/or unexpected messages in the intravehicular communications, may be interpreted as confirmed hacking. Upon confirmation of hacking, a warning may be issued to an operator and a vehicle safe mode may be entered, including restricting vehicle functionality.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: December 24, 2019
    Assignee: Ford Global Technologies, LLC
    Inventors: Dana Conner, Mahmoud Yousef Ghannam, Darren Lee
  • Patent number: 10511328
    Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to an efficient list decoder for list decoding low density parity check (LDPC) codes.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: December 17, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Shrinivas Kudekar, Thomas Joseph Richardson, Gabi Sarkis, Vincent Loncke
  • Patent number: 10511488
    Abstract: A system for performing an integrity verification based on a distributed delegator and verifying an integrity of a plurality of individual devices based on a network includes: a first individual device which is an integrity verification target of the plurality of individual devices; a second individual device configured to vicariously verify the verification target device of the plurality of individual devices; and a remote device management server configured to select the second individual device of the plurality of individual devices as a verification delegator, and to receive a result of integrity verification of the first individual device by the second individual device.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: December 17, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong Hyuk Moon, Dae Won Kim, Young Sae Kim, Seung Yong Yoon, Jin Hee Han, Jae Deok Lim, Jeong Nyeo Kim, Yong Sung Jeon
  • Patent number: 10511327
    Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). Disclosed is an apparatus for performing an iteration decoding scheme for a Low Density Parity Check (LDPC) code. The apparatus includes a receiver configured to receive an encoded signal based on a parity matrix set for a plurality of variable nodes including a first variable node with a first degree and a second variable node with a second degree. The apparatus further includes a processor configured to determine at least one variable node based on a first threshold determined according to the first degree and a second threshold determined according to the second degree among the plurality of variable nodes and to generate decoded data from the signal based on the at least one determined variable node.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: December 17, 2019
    Assignees: Samsung Electronics Co., Ltd., Korea University Research and Business Foundation
    Inventors: Myeong-Woo Lee, Tae Hyun Kim, Jong Hyun Baik, Jun Heo
  • Patent number: 10505671
    Abstract: Disclosed in embodiments of the present disclosure are a polar code encoding method and device. The method includes: utilizing a common information bit set to represent each of m polar code blocks, the polar codes in each polar code block having the same code length and different code rates, and m being greater than or equal to 2; according to the common information bit set corresponding to the polar code block, acquiring an information bit set corresponding to each polar code in the polar code block; and according to the information bit set corresponding to each polar code in the polar code block, conducting polar code encoding on information to be encoded, thus reducing polar code representation overhead, and solving the problem in the prior art of excessively high polar code representation overhead.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 10, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hui Shen, Bin Li, Jun Chen
  • Patent number: 10496471
    Abstract: A system for register error detection is described, the system comprising: a plurality of addressable registers comprising sets of registers, the registers in each set having contiguous addresses; a cyclic redundancy check generator coupled to the addressable registers and configured to determine a cyclic-redundancy-check result for each set of registers from the values of each of the respective set of registers; a controller coupled to the registers and the cyclic-redundancy-check generator.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: December 3, 2019
    Assignee: NXP USA, Inc.
    Inventors: Andres Barrilado Gonzalez, Ralf Reuter, Dominique Delbecq, Francesco d'Esposito, Arnaud Sion, Gustavo Adolfo Guarin Aristizabal, Marcel Christoph Welpot
  • Patent number: 10491244
    Abstract: Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a hard decision decoding on a codeword, determining which check nodes are satisfied and which check nodes are unsatisfied after the hard decision decoding, scheduling a check node processing order by moving at least one unsatisfied check node to be processed ahead of at least one satisfied check node and performing a soft decision decoding on the codeword according to the check node processing order.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: November 26, 2019
    Assignee: Nyquist Semiconductor Limited
    Inventors: Yuan-mao Chang, Jie Chen, Chung-Li Wang
  • Patent number: 10489244
    Abstract: Examples described herein generally relate to a computer device including a memory and at least one processor configured to execute a process and manage the memory for the process. The processor is configured to receive a registration from the process for notifications regarding errors in the memory. The processor is configured to create first metadata regarding content of a portion of the memory allocated to the process when a physical memory address associated with a virtual address for the portion of memory is made non-writable to the process. The processor is configured to detect an error in the memory by comparing second metadata for current contents of the portion of memory to the first metadata. The processor is configured to provide a notification to the process in response to detecting the error. In some implementations, the processor is configured to determine whether the error is correctable based on the metadata.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: November 26, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Mehmet Iyigun, Yevgeniy Bak
  • Patent number: 10482921
    Abstract: A memory system includes a memory device, a command clock (CK_t clock) that provides a first clock signal at a first frequency, and a data path clock (WCK_t clock) that provides a second clock signal at a second frequency different than the first frequency. Data path circuitry is synchronized with the WCK_t clock and provides an error detection code (EDC) hold pattern during an idle state. EDC hold pattern synchronization logic synchronizes a start of transmission of the EDC hold pattern synchronous to the CK_t clock.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: November 19, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Stefan Dietrich
  • Patent number: 10476632
    Abstract: A transmission device is implemented in a first node in an optical transmission system in which a frame is transmitted from the first node to a second node via an optical interface. The transmission device includes a decision unit that decides whether a type of a first error correction code used in the first node is the same as a type of a second error correction code used in the second node. When a type of the first error correction code is the same as a type of the second error correction code, the transmission device transmits the frame to which an error correction code used in the first node is added to the second node without terminating the error correction code.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: November 12, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Toshiki Tanaka, Tomoo Takahara
  • Patent number: 10476524
    Abstract: A method and apparatus is described for assigning columns of an LDPC H matrix to a plurality of decoding logics for efficient decoding of codewords. The rows of the LDPC H matrix are evaluated in a number of different orderings, and for each row in each ordering, a number of columns containing non-zero circulants are determined that cannot be evenly distributed to a plurality of decoding logics. As each row is evaluated, one or more columns of the LDPC H matrix are assigned to temporary bins for storage. After the LDPC H matrix has been evaluated a plurality of times, the arrangement that resulted in the fewest number of “mismatched” columns is selected, and the columns of the LDPC H matrix that were assigned to the temporary storage bins for that particular row arrangement is used to assign the columns in the bins to the plurality of decoding logics.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: November 12, 2019
    Assignee: Goke US Research Laboratory
    Inventors: Ko-Chung Tseng, Chandra Varanasi, Engling Yeo
  • Patent number: 10469152
    Abstract: An information processing apparatus, comprising: a matrix inversion calculating unit that includes a higher level matrix inversion processing block containing at least four lower level matrix inversion processing blocks and two assistant processing blocks and; a control unit that reconfigures an internal structure of the matrix inversion calculating unit depending on the input matrix size.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: November 5, 2019
    Assignee: NEC CORPORATION
    Inventor: Xiao Peng
  • Patent number: 10459785
    Abstract: The present disclosure, in various embodiments, describes technologies and techniques for detecting errors in a non-volatile memory (NVM) device prior to performing re-training/recalibration. A processing device in a NVM controller detects a cyclic redundancy check (CRC) condition for detecting error in the NVM device, and a re-training condition that is based on the CRC condition. A CRC circuit generates CRC code when a CRC condition is detected, and the processing is configured to compare CRC code received from the NVM controller with the generated CRC code to detect error. A calibration circuit then re-trains the NVM device if the CRC circuit detects error and the re-training condition has been met.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: October 29, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Gautam Ashok Dusija, Venkatesh Prasa Ramachandra, Mrinal Kochar
  • Patent number: 10454499
    Abstract: Certain aspects of the present disclosure generally relate to techniques for enhanced puncturing and low-density parity-check (LDPC) code structure. A method for wireless communications by a transmitting device is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a base matrix having a first number of variable nodes and a second number of check nodes; puncturing the code word according to a puncturing pattern designed to puncture bits corresponding to at least two of the variable nodes to produce a punctured code word; adding at least one additional parity bit for the at least two punctured variable nodes; and transmitting the punctured code word.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: October 22, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Joseph Richardson, Shrinivas Kudekar
  • Patent number: 10454957
    Abstract: A method for use in a network communication system including a plurality of electronic controllers that communicate with each other via a bus in accordance with a Controller Area Network (CAN) protocol includes determining whether or not content of a predetermined field in a transmitted frame meets a predetermined condition indicating fraud, transmitting an error frame before an end of the frame is transmitted in a case where it is determined that the frame meets the predetermined condition, recording a number of times the error frame is transmitted, for each identifier (ID) represented by content of an ID field included in a plurality of frames which has been transmitted, and providing a notification in a case where the number of times recorded for an ID exceeds a predetermined count.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: October 22, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Yoshihiro Ujiie, Hideki Matsushima, Tomoyuki Haga, Manabu Maeda, Yuji Unagami, Takeshi Kishikawa
  • Patent number: 10447487
    Abstract: According to an embodiment, a data generating device includes a first generator, an obtainer, a second generator, a verifier, and an operation selector. The first generator generates device-specific first data. The obtainer obtains second data from outside of the data generating device. The second generator generates third data based on the first data and the second data. The verifier verifies correctness of the third data. When the third data is determined to be incorrect, the operation selector selects at least one of regenerating the first data, re-obtaining the second data, and disabling the data generating device according to a predetermined selection rule.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: October 15, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Komano, Hideo Shimizu, Takeshi Kawabata
  • Patent number: 10440759
    Abstract: Techniques for performing forward error correction of data to be transmitted over an optical communications channel. The techniques include: receiving data bits; organizing the data bits into an arrangement having a plurality of blocks organized into rows and columns and into a plurality of strands including a first strand of blocks that includes a back portion comprising a first row of the plurality of blocks, and a front portion comprising blocks from at least two different columns in at least two different rows other than the first row of blocks; and encoding at least some of the data bits in the arrangement using a first error correcting code at least in part by generating first parity bits by applying the first error correcting code to first data bits in the front portion of the first strands and second data bits in the back portion of the first strand.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: October 8, 2019
    Assignee: Acacia Communications, Inc.
    Inventor: Pierre Humblet
  • Patent number: 10439649
    Abstract: A memory device includes a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform coarse decoding and fine decoding. In coarse decoding, the decoder decodes in parallel two or more codewords, which share a common block of bits, to determine error information. Next, the decoder corrects errors in a first codeword based on the error information. Then, it is determined if the shared common block of data bits is corrected. If the shared common data block is updated, then error correction based on the error information is prohibited in codewords sharing the common block of data bits with the first codeword. In fine decoding, a single codeword is decoded at a time for error correction.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: October 8, 2019
    Assignee: SK Hynix Inc.
    Inventors: Naveen Kumar, Yi-Min Lin, Aman Bhatia
  • Patent number: 10430374
    Abstract: A method for data transfer includes transmitting a sequence of data packets, including at least a first packet and a second packet transmitted subsequently to the first packet, from a first computer over a network to a second computer in a single remote direct memory access (RDMA) data transfer transaction. Upon receipt of the second packet at the second computer without previously having received the first packet, a negative acknowledgment (NAK) packet is sent from the second computer over the network to the first computer, indicating that the first packet was not received. In response to the NAK packet, the first packet is retransmitted from the first computer to the second computer without retransmitting the second packet.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: October 1, 2019
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Adi Menachem, Ariel Shahar, Noam Bloch, Diego Crupnicoff, Michael Kagan