Abstract: A memory controller includes an error correction circuit that converts some bits of first data into parity bits for an error correction operation and generates second data including remaining bits of the first data and the parity bits replaced from the some bits, and a physical layer that transmits the second data instead of the first data to a memory device.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control a persistent storage media including a first media to store one or more source blocks of data and a second media to store one or more destination blocks of data, determine if an error rate associated with a read of a particular destination block of the one or more destination blocks exceeds a threshold error rate, identify a particular source block of the one or more source blocks which corresponds to erroneous data in the particular destination block, determine which of the particular source block and the particular destination block is a failed block, and retire the failed block. Other embodiments are disclosed and claimed.

Abstract: A storage system has a controller with an encoder. The encoder is configured to perform first and second stages of an encoding process in parallel on pipelined data blocks. In this way, while the first stage of the encoding process is being performed on a first data block, the second stage of the encoding process is performed on a second data block.

Abstract: The embodiments of the present disclosure provide a method and an apparatus for data processing with structured LDPC codes. The method includes: obtaining a code block size for structured LDPC coding; determining a coding expansion factor z based on at least one of the code block size, a parameter kb of a basic check matrix, a positive integer value p or the basic check matrix having mb rows and nb columns; and encoding a data sequence to be encoded, or decoding a data sequence to be decoded, based on the basic check matrix and the coding expansion factor. The present disclosure is capable of solving the problem in the related art associated with low flexibility in data processing with LDPC coding and improving the flexibility in data processing with LDPC coding.

Abstract: The present disclosure relates to information transmission method, decoding method, and apparatus. One example method includes encoding, by a sending device, a to-be-encoded sequence based on preset parameters to obtain an encoded sequence, where the preset parameters include a quantity of check bits, positions of the check bits, and a check equation, and sending the encoded sequence to a receiving device.

Abstract: Devices and methods for error correction are described. An exemplary error correction decoder includes a mapper configured to generate, based on a first set of read values corresponding to a first codeword, a first set of log likelihood ratio (LLR) values; a first buffer, coupled to the mapper, configured to store the first set of LLR values received from the mapper; and a node processor, coupled to the first buffer, configured to perform a first error correction decoding operation using the first set of LLR values received from the first buffer, wherein a first iteration of the first error correction decoding operation comprises refraining from updating values of one or more variable nodes, and performing a syndrome check using a parity check matrix and sign bits of the first set of LLR values stored in the first buffer.

Abstract: This application relates to the communications field, and discloses an encoding method, a decoding method, an encoding apparatus, and a decoding apparatus. The encoding method includes: receiving a data bitstream; performing forward error correction FEC encoding on the data bitstream to obtain X Reed-Solomon RS outer codes, where each of the X RS outer codes includes N1 symbols, K1 of the N1 symbols are payload symbols; and performing FEC encoding on the X RS outer codes to obtain Y RS inner codes, where each of the Y RS inner codes includes N2 symbols, K2 of the N2 symbols are payload symbols. According to this application, error correction performance of FEC decoding can be improved.

Abstract: A method for storing data. The method includes receiving data to write to persistent storage, calculating parity values for a grid using the data, where each of the parity values is associated with one selected from of the Row Q Parity Group, the Row P Parity Group, the Column Q Parity Group, the Column P Parity Group, and the Intersection Parity Group. The method further includes writing the data to a data grid in the persistent storage, where the data grid is part of the grid, and writing the parity values for the grid to a portion of the grid, where the portion of the grid comprises physical locations associated with a Row Q Parity Group, a Row P Parity Group, a Column Q Parity Group, a Column P Parity Group, and an Intersection Parity Group, wherein the portion of the grid is distinct from the data grid.

Abstract: This application discloses an information processing method and apparatus, a communications device, and a communications system. The method includes: encoding an input sequence by using a low density parity check LDPC matrix to obtain a bit sequence D, where a base matrix of the LDPC matrix is represented by a matrix of m rows and n columns, each column corresponds to a group of Z continuous bits in the bit sequence D, and both n and Z are integers greater than 0; and obtaining an output bit sequence based on a bit sequence V, where the bit sequence V is obtained by permuting groups of bits corresponding to at least two parity check columns in the bit sequence D.

Abstract: A physical broadcast channel (PBCH) transmission method and an apparatus. The method includes scrambling PBCH based on a first scrambling code of the PBCH, where the first scrambling code is one of four scrambling codes, where a combination of a second least significant bit and a third least significant bit of a system frame number (SFN) indicates one value of four values, and where the four scrambling codes have a one-to-one correspondence with the four values, and sending the PBCH to a terminal device.

Abstract: A flash memory controller is configured to decode a codeword. During the decoding process, the flash memory can check the decoding status of each codeword segment in the codeword and skip the decoding of a codeword segment whose decoding status is passed, thereby saving time decoding and also improving decoding efficiency. Even though only a part of the codeword segments in the codeword have been successfully decoded in the decoding process at the previous time, the flash memory controller can replace the part of the codeword segments in the codeword with the correct results obtained previously, and then decoding the re-formed codeword again. Accordingly, the decoding accuracy can be increased and the burden on the subsequent decoding process or data recovery can be reduced.

Abstract: A method for extracting path overhead (POH) data blocks from a data stream in a 64B/66B-block communication link, the method includes receiving at a sink node a data stream in a 64B/66B-block communication link, detecting within the data stream at a PCS sublayer a micro-packet starting with an /S/ control block, including K POH data blocks, and ending with a /T/ control block, extracting the micro-packet from the data stream, and extracting the POH data blocks from the micro-packet.

Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may measure a physical channel such as a narrowband physical broadcast channel (NPBCH) to supplement (e.g., or as an alternative to) reference signal measurements when determining a received signal measurement, such as a received signal strength or received signal quality of a cell. A base station may transmit an indication to a UE that identifies the frequency at which a portion of NPBCH transmissions (e.g., reserved fields of a master information block (MIB)) is expected to change from one NPBCH transmission to another. The UE may adjust its utilization of NPBCH for determining the received signal measurement based on the indication. Further, the UE may communicate with the cell based on the determination of the received signal measurement, which are based on the indication.

Abstract: A method for polar encoding includes: receiving a message including information bits; encoding the message using a first polar code to obtain a first codeword; and encoding the message using a second polar code to obtain a second codeword. The second codeword includes two parts, and the first part of the second codeword is same as the first codeword. The method for polar encoding also includes transmitting the first codeword to a receiver in a first transmission; and transmitting the second part of the second codeword in a second transmission without transmitting the first part of the second codeword when the receiver is unable to decode the message based on the first codeword.

Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for storing blockchain data based on error correction code. One of the methods includes determining, by a blockchain node, block data associated with a current block of a blockchain; performing error correction coding of the block data to generate encoded data; dividing, based on one or more predetermined rules, the encoded data into a plurality of data sets; storing, based on the one or more predetermined rules, one or more data sets of the plurality of data sets; hashing each data set of remaining data sets of the plurality of data sets to generate one or more hash values corresponding to the remaining data sets; and storing the one or more hash values.

Abstract: Apparatuses, systems, and techniques to compute cyclic redundancy checks use a graphics processing unit (GPU) to compute cyclic redundancy checks. For example, in at least one embodiment, an input data sequence is distributed among GPU threads for parallel calculation of an overall CRC value for the input data sequence according to various novel techniques described herein.

Abstract: Provided is an optical transmission/reception device including an error correction decoding unit (36) for decoding a received sequence encoded with an LDPC code, in which the error correction decoding unit (36) is configured to perform decoding processing using a parity check matrix (70) of a spatially-coupled LDPC code, which includes a plurality of parity check sub-matrices (71) combined with each other, in which the decoding processing is windowed decoding processing that uses a window (80) over one or more parity check sub-matrices (71), and in which a window size of the window (80) and a decoding iteration count due to throughput and requested correction performance are variable and input from a control circuit (12) connected to the error correction decoding device (36).

Abstract: A display panel driving apparatus includes an interface, a timing controller, a gate driver, and data driver. The interface includes a data determiner to determine whether or not input image data has a communication error and to process a packet of a data stream of the input image data, even though the input image data has the communication error. The timing controller receives the processed input image data from the interface and generates a data signal, a gate control signal, and a data control signal. The gate driver generates a gate signal based on the gate control signal. The data driver generates a data voltage based on the data control signal and the data signal.

Abstract: The invention provides a data accessing method for a memory apparatus. The data accessing method includes: performing a reading operation on the memory apparatus based on an address information to obtain a codeword and an indicator, where the indicator corresponds to the codeword; enabling a first error correction code (ECC) operation or second ECC operation to be operated on the codeword for generating an error corrected data, wherein, the first ECC operation corrects less bits than the second ECC operation.

Abstract: An apparatus comprising data processing circuitry for processing data in one of a plurality of operating states, an instruction decoder for decoding instructions and error checking circuitry for performing error checking operations. In response to a touch instruction being decoded by the instruction decoder, error checking operation is performed on selected architectural state. The architectural state is architecturally inaccessible to the operating state. As a result of the touch instruction, the architectural state remains unchanged, at least when no error is detected.

Abstract: A plurality of storage nodes within a single chassis is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. The plurality of storage nodes has a non-volatile solid-state storage for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data. The plurality of storage nodes is configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to the user data from a remainder of the plurality of storage nodes. The plurality of storage nodes is configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory.

Abstract: Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

Abstract: An exemplary communications receiver includes an error detector for determining whether a first and second received frame is corrupted, each frame comprising of a plurality of bits. The receiver includes a filter for determining whether the second received corrupted frame should be recovered. The receiver includes a frame generator for generating a recovered frame based on the plurality of bits of the first and second corrupted frame and frame information of the second corrupted frame, in response to the error detector determining that the first and second received frames are corrupted and the filter determining that the second received frame should be recovered.

Abstract: An apparatus is provided which comprises at least one processor, at least one memory including computer program code, and the at least one processor, with the at least one memory and the computer program code, being arranged to cause the apparatus to at least perform generating a code block including information bits and parity bits, the parity bits being generated by performing a cyclic redundancy check on the information bits, determining the number of parity bits used in generating the code block based on an applied linear error correcting code base graph and/or based on the number of the information bits, and encoding the code block by using the applied linear error correcting code base graph.

Abstract: A technique of managing storage includes receiving a request to change an initial portion of data, the initial portion of data (i) associated with an initial redundant region and (ii) including a first segment to be changed and a set of other segments not to be changed; updating the first segment in response to the request; and generating an updated redundant region based on a computation involving the initial redundant region and the first segment but not involving the set of other segments.

Abstract: This document discloses a solution for error detection. According to an aspect, a method comprises: generating, by a first apparatus, a transport block and error detection bits for the transport block; generating, by the first apparatus, a first number of code block groups by using the transport block and the error detection bits, wherein the first number is two or higher and based on a number of code blocks a second apparatus is able to decode in parallel processing; generating, by the first apparatus, error detection bits for at least one of the code block groups; generating, by the first apparatus, a plurality of code blocks for each code block group, and causing transmission of the plurality of code blocks to the second apparatus.

Abstract: A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.

Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

Abstract: A data storage device is disclosed comprising a head actuated over a disk. A first plurality of codewords and corresponding parity sector are generated, and a second plurality of codewords and corresponding parity sector are generated. The first and second plurality of codewords are written to the disk, and during a read of the first and second set of codewords, M codeword locations within the data track that are unrecoverable are saved, and N codeword locations out of the M codeword locations are selected based on a quality metric of the read. The N codewords are reread from the data track at the N codeword locations and reliability metrics associated with the N codewords are saved. The saved reliability metrics are updated using at least one of the first parity sector or the second parity sector.

Abstract: Parity logic is widely used in forward error correction codes and error detection codes. When used for error correction and error detection applications, the role of parity bits is to increase code distance by introducing memory between encoded bits and input bits at cost of overhead bits. Present disclosure provide systems and methods for implementing invertible parity functions using parity logic wherein ‘k’ input bits are received and encoded using a first invertible parity function. The ‘k’ input bits can be iteratively encoded to obtain nonlinearity and higher dependency between set of encoded parity bits and the ‘k’ input bits or other data bits. Further the decoding is performed on the set of encoded bits to retrieve original ‘k’ input bits using a second invertible parity function.

Abstract: This application provides an encoding method. The method includes: determining a frame of an outer code of to-be-encoded data, where the frame of the outer code includes a data information code and a check code of the data information code, the frame of the outer code is divided into Q data blocks, each data block in the Q data blocks includes W bits, and W and Q are integers greater than 0; and encoding the Q data blocks to obtain Q codewords of an inner code, where the Q data blocks are in a one-to-one correspondence with the Q codewords of the inner code, a first codeword in the Q codewords of the inner code includes a first data block and a check code of the first data block, the first codeword is any codeword in the Q codewords of the inner code.

Abstract: An optical communication system includes a first communication device configured to transmit optical signals, and a second communication device configured to receive the optical signals. The first transmission device includes encoding circuit that configured to assign, to a plurality of bit strings, symbols each corresponding to a value of every one of the plurality of bit strings, the symbols being among a plurality of symbols in a constellation of a multi-level modulation scheme, convert values of bit strings, generate the second error correction code from a second bit string among the plurality of bit strings in every one of a plurality of periods, delay the first error correction code, and delay the second error correction code, wherein the encoding circuit uses the delayed first error correction code and the delayed second error correction code to convert a value of the second bit string.

Abstract: A data processing method and apparatus. The data process method includes: determining, by a transmitting node, a code block length N0 for encoding an information bit sequence to be transmitted according to a data characteristic for representing the information bit sequence to be transmitted and a preset parameter corresponding to the data characteristic; performing, by the transmitting node, polar encoding on the information bit sequence to be transmitted according to the code block length N0; and transmitting, by the transmitting node, a code block obtained through the polar encoding to a receiving node.

Abstract: A network node and a user device are provided. The network node comprises a processor to determine for each of the plurality of user devices a corresponding check element position of a corresponding check element in a control information message addressed to the user device; a transmitter to transmit a first control signal (CS1) to each of the plurality of user devices, the CS1 indicating the determined corresponding check element position. The user device comprising: a receiver to receive a CS1 indicating a corresponding check element position of a check element associated with the user device in a control information message (M), the control information message (M) comprising control information (d) and at least two check elements, a processor to derive the corresponding check element position of the check element associated with the user device from the CS1.

Abstract: Certain aspects of the present disclosure generally relate to techniques for enhanced puncturing and low-density parity-check (LDPC) code structure. A method for wireless communications by a transmitting device is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a base matrix having a first number of variable nodes and a second number of check nodes; puncturing the code word according to a puncturing pattern designed to puncture bits corresponding to at least two of the variable nodes to produce a punctured code word; adding at least one additional parity bit for the at least two punctured variable nodes; and transmitting the punctured code word.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to perform a low-density parity check (LDPC) encoding on input bits using a parity check matrix to generate an LDPC codeword comprising information word bits and parity bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Abstract: The present disclosure relates to a parameterizable energy supply apparatus comprising a communications interface for receiving parametrizing data via a communications network; and a processor which is designed to adjust an output characteristic of the parameterizable energy supply apparatus on the basis of the parametrizing data received.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

Abstract: Systems and methods are provided for fast cyclic redundancy check code generation. For example, a method includes representing the sequence of bits as a polynomial over a Galois field base 2; partitioning the polynomial into a plurality of partial polynomials, wherein the polynomial equals the sum of the partial polynomials; concurrently generating a respective partial CRC code for each of the partial polynomials; weighting each partial CRC code according to a position of the respective partial polynomial in the polynomial; and summing the weighted partial CRC codes.

Abstract: A transmission apparatus determines the size of padding data by using the group size of each of a plurality of transmission streams calculated on the basis of a code rate and a modulation scheme that are set for each transmission stream and the number of groups calculated from the size of input transmission data and the group size of the each transmission stream, adds padding data having the determined size to the transmission data, distributes the transmission data and the padding data to generate the plurality of transmission streams, encodes and modulates each of the generated transmission streams with the code rate and the modulation scheme that are set for each transmission stream, converts the modulated transmission streams into radio signals, and transmits the radio signals from a plurality of transmitting antennas.

Abstract: A memory controller includes an error correction code (ECC) module for performing ECC decoding based on read data received from a non-volatile memory device for performing an on-chip valley search (OVS) read operation. A read voltage modification module receives status bits representing a latch that latches the read data among a plurality of latches included in the non-volatile memory device to store result values of the OVS read operation and determine whether to change a read voltage based on the status bits when the ECC decoding is successfully performed.

Abstract: The disclosure relates to a method performed by a wireless device, for receiving system information from a network node of a wireless communication system. The system information is received in a synchronization signal (SS) block of an SS burst set comprising at least one SS block. The system information is multiplexed with information providing a time index indicating which SS block of the SS burst set that is being received. The method comprises receiving the information providing the time index, and receiving the system information, which comprises descrambling the system information using a scrambling sequence generated based on the information providing the time index. The method also comprises determining an accuracy of the information providing the time index, based on an error-detection code related to the received system information. The disclosure also relates to corresponding network node method and apparatus.

Abstract: A method includes: sending a first boundary bit block; sequentially sending an Ith bit block; determining a first parity check result and a second parity check result, where a check object of the first parity check result includes m consecutive bits of each bit block in the N bit blocks, a check object of the second parity check result includes n consecutive bits of each bit block in the N bit blocks, and at least one of m and n is greater than or equal to 2; and sending a second boundary bit block, the first parity check result, and the second parity check result.

Abstract: A method is performed at an electronic device that includes magnetic random access memory (MRAM). The method includes loading the MRAM with data including main data, first error correcting data, and second error correcting data. The MRAM comprises a plurality of MRAM cells characterized by a first magnetic anisotropy corresponding to a first error rate at a predefined temperature that exceeds a threshold for correcting errors using only the first error correcting data. The method further includes, after loading the MRAM with the data, heating the MRAM to the predefined temperature and correcting errors in the main data using both the first error correcting data and the second error correcting data. The method further includes after correcting the errors in the main data, erasing, from the MRAM, the second error correcting data and maintaining, on the MRAM, the first error correcting data.

Abstract: Example information transmission methods and devices are disclosed. One example method is applied to a network device and includes determining CRC bits of to-be-sent information bits, concatenating the CRC bits and the to-be-sent information bits to obtain a first information sequence, and interleaving bits in the first information sequence in an interleaving manner or scrambling the bits in the first information sequence in a scrambling manner, to obtain a second information sequence, to ensure that bits at locations of the CRC bits after a cyclic shift cannot check bits at locations of the to-be-sent information bits after the cyclic shift. A cyclic shift is performed on the second information sequence to obtain a third information sequence, where a quantity of cyclically shifted bits is used to carry information about some bits of a system frame number, and the third information sequence is sent.

Abstract: A transmission method includes performing LDPC coding on a basis of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 3/16, and performing group-wise interleaving in which the LDPC code is interleaved in units of bit groups of 360 bits. The transmission method further includes mapping the LDPC code to one of 16 signal points of uniform constellation (UC) in 16QAM on a 4-bit basis. In the group wise interleaving, an (i+1)th bit group from a head of the LDPC code is set as a bit group i, and a sequence of bit groups 0 to 191 of the 69120-bit LDPC code is interleaved into a sequence of bit groups.

Abstract: A memory interface circuit, a memory storage device and a signal generation method are provided. The memory interface circuit is configured to connect a volatile memory module and a memory controller. The memory interface circuit includes a clock generation circuit, a first interface circuit and a second interface circuit. The clock generation circuit is configured to provide a reference clock signal. The first interface circuit is configured to provide an address signal to the volatile memory module based on a first transition point of the reference clock signal. The second interface circuit is configured to provide a command signal to the volatile memory module based on a second transition point of the reference clock signal. The first transition point is one of a rising edge and a falling edge of the reference clock signal. The second transition point is the other one of the rising edge and the falling edge of the reference clock signal.

Abstract: A data access method, a memory control circuit unit and a memory storage device are provided. The method includes generating a first error correction code corresponding to received first data according to a first error correction encoding operation; and generating a second error correction code corresponding to received second data according to a second error correction encoding operation, wherein the second error correction code includes a first and a second partial error correction code. The method further includes writing the first data, the first error correction code and the second partial error correction code to a data bit area and a redundant bit area of a first physical programming unit respectively; and writing the second data and the first partial error correction code to the data bit area and the redundant bit area of a second physical programming unit respectively.

Abstract: The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 9/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.