Abstract: The present invention provides a methods, apparatus and systems for improving a systems-level data rate on a communications link such the orthogonal frequency division multiplexed multiple access (OFDMA) downlink used in used in WiFi and LTE cellular/wireless mobile data applications. The present invention preferably uses a form of multilevel coding and decoding known as tiled-building-block encoding/decoding. With the present invention, different receivers coupled to different parallel downlink channels with different channel qualities decode different received signal constellations at different levels of resolution. This allows the downlink of the OFDMA system to operate with a significantly higher data rate, thus eliminating existing inefficiencies in the downlink and significantly increasing system level bandwidth efficiency.

Abstract: The described technology is generally directed towards adaptive interleaving in network communications systems based on one or more conditions with respect to user equipment. When conditions such as the speed of the user equipment indicate that performance can be increased by interleaving the data traffic, data is transmitted to the user equipment using an adaptive interleaver in the coding chain of MIMO systems. The adaptive interleaver is not used when conditions indicate performance is unlikely to improve. Adaptive interleaving may be performed in the frequency domain, in the frequency and time domain, or the frequency time and space domain. Multiple interleavers with different interleaving patterns may be used in the frequency domain and in the frequency and time domain. Adaptive interleaving may be based on one or more various criteria corresponding to the condition data received from the user equipment.

Abstract: Systems and methods providing low-density parity-check (LDPC) decoder configurations capable of decoding multiple code blocks in parallel are described. Parallel LDPC decoders of embodiments can be reconfigured to simultaneously decode multiple codewords with reconfigurable size. In operation of embodiments of a parallel LDPC decoder, a plurality of active portions of the decoder logic are configured for parallel processing of a plurality of code blocks, wherein each active region processes a respective code block. The decoder logic active portions of embodiments are provided using a reconfigurable segmented scalable cyclic shifter supporting multiple instruction, multiple data (MIMD), wherein multiple individual different data shifts are implemented with respect to a plurality of code blocks in an instance of data shifting operation.

Abstract: A method for decoding a cyclic code is disclosed. The method includes: determining a plurality of syndromes for the cyclic code; determining, by a hardware processor, a first coefficient and a second coefficient based on the plurality of syndromes; determining, by the hardware processor, a third coefficient based on the second coefficient; and generating an error-locator polynomial based on the first coefficient, the second coefficient, and the third coefficient.

Abstract: Disclosed are a method for dividing a transport block of a low density parity check (LDPC) code and an apparatus therefor. A method for dividing a transport block of an LDPC code according to the present disclosure can improve the performance of the LDPC code by dividing the transport block using a minimum number of code blocks. In addition, it is possible to minimize shortening bits by making the size of some of the code blocks smaller than the size of the other code blocks. Further, it is possible to prevent performance degradation due to a minimum size code block by minimizing the number of the code blocks and performing shortening on a large size code block.

Abstract: Disclosed are an encoder, a transmitting device, a coding method and a transmission method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block coding is used. A puncture pattern setting unit searches for a puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of a sub block matrix that forms a check matrix (H) of a QC-LDPC code, and a puncture unit (data reduction unit) switches the puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of the sub block matrix that forms the check matrix of the QC-LDPC code.

Abstract: A control circuit configured to associate a plurality of memory with an error correction scheme. The control circuit including an internal operation circuit configured to generate an internal command based on an access unit of the plurality of memory. The control circuit including a storage circuit configured to store information on the access unit of the plurality of memory.

Abstract: An example apparatus includes a non-volatile memory including a first memory having a first write rate and a second memory having a second write rate, the first write rate greater than the second write rate An example controller is to determine, based on a ratio, a first portion of the data to be written to the first memory, and a second portion of the data to be written to the second memory type, the second portion of the data not included in the first portion of the data.

Abstract: The present technique relates to a transmission apparatus, a transmission method, a reception apparatus, and a reception method that can ensure favorable communication quality in data transmission using an LDPC code. LDPC coding is performed based on a check matrix of an LDPC code with a code length N of 69120 bits and a code rate r of 7/16 or 8/16. The LDPC code includes information bits and parity bits, and the check matrix includes an information matrix corresponding to the information bits and a parity matrix corresponding to the parity bits. The information matrix is represented by a check matrix initial value table. The check matrix initial value table is a table indicating positions of elements of 1 in the information matrix on the basis of 360 columns and is a predetermined table. The present technique can be applied to, for example, data transmission using the LDPC code.

Abstract: An encoder of a flash memory controller is provided, which includes a barrel shifter module, an inverse matrix calculating circuit and a calculating circuit. The barrel shifter module processes multiple data blocks to generate multiple partial parity blocks including a first portion, a second portion and a third portion. The inverse matrix calculating circuit performs inverse matrix calculating operations on the first portion to generate a first portion of parity blocks. The calculating circuit performs inverse matrix calculating operations on the second portion and the third portion according to the first portion of the parity blocks, to generate a second portion of the parity blocks and a third portion of the parity blocks. The first portion of the parity blocks, the second portion of the parity blocks, and the third portion of the parity blocks serve as multiple parity blocks generated in response to encoding the data blocks.

Abstract: A memory system includes an error correction code (“ECC”) generation circuit using write data to generate an ECC to be stored together with the write data; a memory device, during a write operation, storing received data and a received ECC in a memory core, and, during a read operation, checking for an error in data read from the memory core, correcting the error in read data using the ECC and outputting error-corrected data and the ECC, when the error in the read data is between one bit and N bits inclusive, and outputting the read data and the ECC when no error is present in the read data or the error in the read data exceeds N bits; and an error correction circuit correcting, when an error is present in data outputted from the memory device, the error in the data outputted using an ECC outputted from the memory device.

Abstract: A device for supporting a test mode for memory testing according to an example embodiment of the inventive concepts may include a memory configured to receive and store writing data and output reading data from the stored writing data; an error correction code (ECC) engine configured to generate the writing data by encoding input data and to generate output data by correcting error bits of N bits or less included in receiving data when N is a positive integer; and an error insertion circuit configured to provide the reading data to the ECC engine as the receiving data in a normal mode and to provide data obtained by inverting at least one bit of less than N bits of the reading data to the ECC engine as the receiving data in the test mode.

Abstract: A decoder circuit includes a low-density parity-check (LDPC) repository to store parity-check information associated with one or more LDPC codes and an LDPC code configurator to receive a first LDPC configuration describing a parity-check matrix for a first LDPC code and to update the parity-check information in the LDPC repository to reflect the parity-check matrix for the first LDPC code. The decoder circuit further includes an LDPC decoder circuitry configurable, based on control signals, to perform LDPC decoding of codewords or LDPC encoding of information using the parity-check information from the LDPC repository.

Abstract: Disclosed are devices, systems and methods for error correction decoding using an iterative decoding scheme. An error correction circuit includes a node processor to perform a plurality of iterations for updating values of one or more variable nodes and one or more check nodes using initial values assigned to the one or more variable nodes, respectively, a trapping set detector to detect a trapping set in at least one of the plurality of iterations by applying a predetermined trapping set determination policy, and a post processor to reduce at least one of the initial values or invert at least one of values of the variable nodes corresponding to an iteration in which the trapping set is detected, upon detection of the trapping set.

Abstract: The data storage device including a buffer configured to receive first information including first data and a first stream class number identifying characteristics of the first data and second information including second data and a second stream class number identifying characteristics of the second data and store the first and second information therein, the second stream class number being different from the first stream class number, a non-volatile memory including a shared memory area and a dedicated memory area different from the shared memory area and configured to store the first and second data stored in the buffer, the non-volatile memory, and a controller configured to control the buffer and the non-volatile memory, the controller configured to store the first and second data stored in the shared memory area, and then migrate the first data stored in the shared memory area to the dedicated memory area may be provided.

Abstract: Certain aspects of the present disclosure provide techniques for an improved encoder for reducing repetition in polar codewords. An apparatus for wireless communication is provided. The apparatus includes at least one processor. The at least one processor is coupled with a memory. The at least one processor includes at least one encoder circuit configured to encode a set of information bits based on a cyclic redundancy check (CRC)-aided polar code to produce a codeword including polar encoded information bits and CRC bits. The at least one encoder circuit is configured to place one or more of the CRC bits at a start of the codeword and to set a value of the one or more CRC bits to a non-zero value. The apparatus includes a transmitter configured to transmit the codeword in accordance with a wireless technology across a channel via one or more antenna elements situated proximate the transmitter.

Abstract: A solution is disclosed for using low-density parity check codes in connection with a retransmission scheme. A first apparatus encodes a data bit set by using a first parity check matrix in a low-density parity check encoder. The first apparatus transmits the encoded data bit set and some parity bits of the set to a second apparatus in a message, and determines that the second apparatus was not capable of decoding the data bit set. The first apparatus modifies the first parity check matrix by using an overlapping matrix where overlapping elements of the first parity check matrix and the overlapping matrix are combined into a second parity check matrix. The first apparatus encodes the data bit set by using the second parity check matrix to provide a second parity bit set, and transmits at least some parity bits of the second parity bit set to the second apparatus.

Abstract: A method and system for controlling application of MU-MIMO. The disclosure provides for considering a device's block error rate (BLER) as a basis to decide whether to provide the device with MU-MIMO service. For instance, a base station could determine which of the base station's served devices each have threshold low BLER. And on at least that basis, the base station could select each such device to receive MU-MIMO service. Or faced with a choice between devices to receive MU-MIMO service, the base station could compare the devices' levels of BLER and could select the devices that have lower BLER to receive MU-MIMO service.

Abstract: Disclosed are a method for dividing a carrying block of a Low Density Parity Check (LDPC) code and an apparatus therefor. The method for dividing a LDPC code of the present disclosure can obtain a high throughput by using a limited size of shifting network. Moreover, it is possible to prevent degradation in performance due to a minimum size of code block by performing shortening for a large size of code block while minimizing the number of code blocks. Furthermore, in selection of a minimum size of code block, since a minimum size of code block is selected on the basis of shortening for a relatively large size of code block, it is possible to increase the size of the minimum size of code block.

Abstract: Aspect for storage device with fault tolerance capability for neural networks are described herein. The aspects may include a first storage unit of a storage device. The first storage unit is configured to store one or more first bits of data and the data includes floating point type data and fixed point type data. The first bits include one or more sign bits of the floating point type data and the fixed point type data. The aspect may further include a second storage unit of the storage device. The second storage unit may be configured to store one or more second bits of the data. In some examples, the first storage unit may include an ECC memory and the second storage unit may include a non-ECC memory. The ECC memory may include an ECC check Dynamic Random Access Memory and an ECC check Static Random Access Memory.

Abstract: An apparatus for smart integrated cyclic data transport is provided. The apparatus may preserve the consistency and integrity of a file during the transfer of the file from a source system to a target system. The apparatus includes an orchestration subsystem. The orchestration subsystem includes an analyzer/generator module. The analyzer/generator module executes an algorithm on the file at the source location. An output is generated from the executed algorithm. The apparatus includes a consistency module. The consistency module pre-checks the output at the source location for pretransfer validation and creates a copy of the output. The copy may preserve the consistency and the integrity of the file. The apparatus includes a data transfer subsystem which transfers the file and the output from the source system to the target system. The apparatus may also include a validation subsystem for validating the integrity and consistency of the file.

Abstract: Polar codes may be generated with a variable block length utilizing puncturing. Some puncturing schemes consider punctured bits as unknown bits, and set the log likelihood ratio (LLR) for those bits to zero; while other puncturing schemes consider punctured bits as known bits, and set the LLR for those bits to infinity. Each of these puncturing schemes has been observed to provide benefits over the other under different circumstances, especially corresponding to different coding rates or different signal to noise ratio (SNR). According to aspects of the present disclosure, both puncturing schemes are compared, and the puncturing scheme resulting in the better performance is utilized for transmission.

Abstract: A method for generating and processing a broadcast signal according to an embodiment of the present invention includes encoding broadcast data for one or more broadcast services, encoding first level signaling information including information describing properties of the one or more broadcast services, encoding second level signaling information including information for scanning the one or more broadcast services and generating a broadcast signal including the broadcast data, the first level signaling information and the second level signaling information, wherein the first level signaling information includes user service description (USD) information describing service layer properties with respect to the broadcast services, wherein the USD information includes capability information specifying capabilities necessary to present broadcast content of the broadcast services.

Abstract: A method and circuit are disclosed to calculate an error correction code (ECC) and perform a decryption in parallel when reading memory data. There are multiple modes of operation. In a normal parallel mode of operation, the data passes through a decryption engine. Simultaneously, the same data passes through an ECC decode engine. However, if no error is detected, the output of the decode engine is discarded. If there is an ECC error, an error indication is made so that the corresponding data exiting the decryption engine is discarded. The circuit then switches to a serial mode of operation, wherein the ECC decode engine corrects the data and resends the corrected data again through the decryption engine. The circuit is maintained in the serial mode until a decision is made to switch back to the parallel mode, such as when a pipeline of the ECC engine becomes empty.

Abstract: A disclosed method may include (1) detecting, at a network stack of a network device, a packet that (A) is destined at least intermediately for a network interface of the network device and (B) has been flagged by the network stack to be dropped instead of forwarded to the network interface based on at least one characteristic of the packet, (2) instead of dropping the packet, forwarding the packet to an alternative network interface of the network device that analyzes content of packets, (3) identifying, at the alternative network interface, the characteristic of the packet, and then (4) executing, based on the characteristic of the packet, at least one action in connection with the packet that improves the performance of the network device. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A method is provided for protecting a vehicle network of a vehicle against manipulated data transmission. The vehicle network includes multiple network nodes. At least one first network node in the vehicle network compares received messages with messages assigned to the first network node and detects the manipulated data transmission if one of the received messages coincides with a message assigned to the first network node, but the first network node did not send the message. At the same time, the first network node compares only selected messages of the received messages with the messages assigned to the first network node or compares the received messages only with selected messages assigned to the first network node.

Abstract: There is provided a radio communication system provided with a first base station, a second base station that communicates with the first base station, and user equipment that communicates with the first base station, the radio communication system including a determiner that determines, based on a predetermined reference value, sharing between signal processing that is to be performed by the first base station and signal processing that is to be performed by the second base station; a first signal processor for the first base station to perform the signal processing in accordance with the sharing determined by the determiner; and a second signal processor for the second base station to perform the signal processing in accordance with the sharing determined by the determiner.

Abstract: An encoding method changes an encoding rate of an erasure correcting code. One cycle is defined as 12k bits (wherein k represents a natural number) which is an encoding output using LDPC-CC with an encoding rate of 1/2, and includes information and parity. From the one cycle, only the information is arranged in the output order of the encoding output to obtain 6k bit information X6i, X6i+1, X6i+2, X6i+3, X6i+4, X6i+5, . . . , X6(i+k?1) X6(i+k?1)+1, X6(i+k?1)+2, X6(i+k?1)+3, X6(i+k?1)+4, and X6(i+k?1)+5. Known information is inserted in 3k pieces of information (Xj) among the 6k bit information, so that when 3k pieces of mutually different j is divided by 3, there is a remainder of 0 regarding k pieces, there is a remainder of 1 regarding k pieces, and there is a remainder of 2 regarding k pieces, to thereby obtain the parity from the information containing the known information.

Abstract: Techniques are described for memory writes and reads according to a chip-kill scheme that allows recovery of multiple failed wordlines. In an example, when reading data from a superblock of the memory, where the decoding of multiple wordlines failed, a computer system schedules the decoding of failed wordlines based on quantity of bit errors and updates soft information based on convergence or divergence of the scheduled decoding. Such a computer system significantly reduces decoding failures associated with data reads from the memory and allows improved data retention in the memory.

Abstract: The present disclosure enables a base station to group UEs based on similar PMIs for a combined transmission. The apparatus may receive a plurality of PMIs from a plurality of UEs. In one aspect, each PMI in the plurality of PMIs may be received from a different UE. The apparatus may also assign each UE of the plurality of UEs to a UE group. In another aspect, each UE group may be associated with a different PMI set in a plurality of PMI sets. The apparatus may further assign a transmission scheme to each UE group. In one configuration, the apparatus may determine one or more preferred spatial layers for each UE (e.g., based on the PMIs) assigned to a UE group, and schedule a combined transmission for the UE group based on the determined one or more spatial layers.

Abstract: A digital broadcasting system and method of processing data are disclosed. Herein, a method of processing data in a transmitting system includes creating a data group including a plurality of mobile service data packets, re-adjusting a relative position of at least one main service data packet of a main service data section, the main service data section including a plurality of main service data packets, and multiplexing the mobile service data of the data group and the main service data of the main service data section in burst units. Herein, a position of an audio data packet among the main service data packets of the main service data section may be re-adjusted. Also, a position of an audio data packet included in the main service data section may be re-adjusted based upon a multiplexing position of the main service data section.

Abstract: Size ambiguity and false alarm rate reduction for polar codes. A user equipment (UE) may determine a decoding candidate bit sequence for a polar-encoded codeword having a codeword size based on a decoding hypothesis for control information having a particular bit length of multiple different bit lengths for the codeword size. The UE may calculate an error detection code (EDC) value for a payload portion of the decoding candidate bit sequence using an EDC algorithm, and may initialize an EDC variable state with at least one non-zero bit value. Scrambling or interleaving of bits may also be performed prior to, or after, polar encoding and may depend on the bit length. In examples, information bits may be bit-reversed prior to generating an EDC value. In examples, the encoded bits may include multiple EDC values to assist the UE in performing early termination and to reduce a false alarm rate.

Abstract: A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

Abstract: An apparatus includes an interface and a control circuit. The interface may be configured to process transfers to/from a medium. The control circuit may be configured to generate a trapping set list of trapping sets of a low-density parity check code, classify bit positions of the trapping sets as belonging to either a user bits field or a parity bits field of a codeword, encode data using the low-density parity check code to generate the codeword, and present the codeword to the interface to transfer the codeword to the medium. The generation of the codeword may include at least one of a shortening or a puncturing of bit locations in the codeword in response to the classifying of the bit positions of the trapping sets. All of the data may be held in the bit locations of the codeword other than the bit locations that are shortened or punctured.

Abstract: One coding method is selected from a plurality of coding methods per data symbol group, an information sequence is encoded by using the selected coding method. The plurality of coding methods includes at least a first coding method and a second coding method. The first coding method is a coding method with a first coding rate for generating a first codeword as a first encoded sequence by using a first parity check matrix. The second coding method is a coding method with a second coding rate different from the first coding rate and obtained after puncturing processing, where a second encoded sequence is generated by performing the puncturing processing on a second codeword by using a second parity check matrix different from the first parity check matrix. A number of bits of the first encoded sequence is equal to a number of bits of the second encoded sequence.

Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

Abstract: A method of receiving a broadcast signal is disclosed. A method of receiving a broadcast signal according to an embodiment of the present invention includes synchronizing and orthogonal frequency division multiplexing (OFDM) demodulating a received broadcast signal, parsing a signal frame of the received broadcast signal, time deinterleaving broadcast data of the signal frame, forward error correction (FEC) decoding the broadcast data, and output formatting the broadcast data and outputting a data stream.

Abstract: An in-between layer partial syndrome stopping (IBL-PS) criterion for a layered LDPC decoder. The IBL-PS syndrome is obtained by applying the parity checks (Hr,r+1) of a couple of a first layer (r) and a second layer (r+1) on the variables after the first layer has been processed and before the second layer is processed by the decoder, the decoding being stopped if said in-between layer syndrome (sr,r+1) is satisfied for at least a couple of consecutive layers.

Abstract: An error correction circuit of a semiconductor memory device including a memory cell array includes an error correction code (ECC) memory that stores an ECC and an ECC engine. The ECC is represented by a generation matrix. The ECC engine generates first parity data based on main data using the ECC, and corrects at least one error bit in the main data read from the memory cell array using the first parity data. The main data includes a plurality of data bits divided into a plurality of sub codeword groups. The ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub codeword groups. The column vectors have elements configured to restrict a location of a sub codeword group in which a mis-corrected bit occurs, in which the mis-corrected bit is generated due to error bits in the main data.

Abstract: An apparatus and method for transmitting/receiving a Forward Error Correction (FEC) packet in a mobile communication system are provided. In the FEC packet transmission method, an FEC packet transmission apparatus transmits an FEC delivery block to an FEC packet reception apparatus. The FEC delivery block includes N payloads. Each of the N payloads includes a payload header. Each payload header included in each of C payloads among the N payloads includes packet oriented header information and an FEC delivery block oriented header information fragment. The packet oriented header information is applied to a related payload, and the FEC delivery block oriented header information fragment is generated by fragmenting FEC delivery block oriented header information applied to the N payloads.

Abstract: A transmission apparatus includes, a receiving circuit that receives a reception signal indicating a coded bit string, a decoding circuit that decodes and corrects the bit string by using a spatially-coupled low density parity check code constituted by arranging element matrixes stepwise in a diagonal direction, a parity check matrix of the spatially-coupled low density parity check code including at least one element matrix having at least one of a number of rows and a number of columns different from a number of rows and a number of columns of other element matrixes when each sparse matrix constituting the parity check matrix is regarded as an element matrix, and outputs the corrected bit string.

Abstract: This disclosure relates to the mobile communications field, and in particular, to data transmission technologies in the mobile communications field. In a data transmission method, a base station allocates, to a terminal, some of time domain symbols that are used for data transmission and that are in a scheduling period of the terminal, and the terminal performs data transmission based on the allocated time domain symbols. According to the method, time domain symbols in the scheduling period that originally belong to the terminal are punctured, a resource waste caused when the terminal occupies all time domain symbols that are used for data transmission and that are in the scheduling period during scheduling each time can be avoided, so that radio resources can be flexibly allocated based on requirements on delays and bandwidth, thereby improving resource utilization.

Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

Abstract: A memory device includes: a non-volatile memory circuit suitable for storing defective column information; a defective latch circuit suitable for receiving and storing the defective column information from the non-volatile memory circuit during a boot-up operation; an error correction code generation circuit suitable for generating an error correction code for correcting an error of the defective column information based on the defective column information; an error correction code latch circuit suitable for storing the error correction code; an error correction circuit suitable for correcting an error of the defective column information transferred from the defective latch circuit based on the error correction code which is transferred from the error correction code latch circuit so as to produce an error-corrected defective column information; and a memory bank suitable for performing a column repair operation based on the error-corrected defective column information.

Abstract: This application provides an encoding method and apparatus in wireless communications between a network device and a terminal. The method includes: performing CRC encoding on A to-be-encoded information bits based on a CRC polynomial, to obtain a first bit sequence, where the first bit sequence includes L CRC bits and A information bits, L=11; and performing polar encoding on the first bit sequence. Based on an improved CRC polynomial, encoding satisfying an FAR requirement is implemented.

Abstract: An aspect includes a method for auto-disabling dynamic random access memory (DRAM) error checking based on a threshold. A method includes receiving data at a DRAM and executing error checking logic based on the data. The error checking logic detects an error condition in the data and it is determined, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached. The error checking logic is disabled at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached.

Abstract: Log likelihood ratio (LLR) values that are computed in a flash memory controller during read retries change over time as the number of program-and-erase cycles (PECs) that the flash memory die has been subjected to increases. Therefore, in cases where an LLR table is used to provide pre-defined, fixed LLR values to the error-correcting code (ECC) decoding logic of the controller, decoding success and the resulting BER will degrade over time as the number of PECs to which the die has been subjected increases. In accordance with embodiments, a storage system, a flash memory controller for use in the storage system and method are provided that periodically measure the LLR values and update the LLR table with new LLR values. Periodically measuring the LLR values and updating the LLR table with new LLR values ensures high decoding success and a low BER over the life of the flash memory die.

Abstract: A method of processing transmission of a broadcast signal includes generating broadcast data for one or more broadcast services, generating first level signaling information including information for describing attribute for the one or more broadcast services, generating second level signaling information including information for listing the one or more broadcast services, generating link layer packets including the encoded broadcast data, the first level signaling information, and the second level signaling information, and generating a broadcast signal including the generated link layer packets.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for managing cyclic redundancy check field lengths in wireless communications. An exemplary method generally includes determining a size of a cyclic redundancy check (CRC) field, from a plurality of possible sizes for a given type of physical wireless channel, to be used for a transmission to be sent on the physical wireless channel, and performing communication based on the transmission on the physical wireless channel with the CRC field of the determined size.

Abstract: An adaptive cyclic redundancy check process for uplink control information signaling is provided to allow a number of cyclic redundancy check bits to be adjusted based on the likelihood of data being corrupted during transmission. In an embodiment, a base station device can send a cyclic redundancy check length map to a mobile device that indicates to the mobile device to use a specific number of cyclic redundancy bits to use per a specified payload size of uplink control information. Optionally, the mobile device can determine a number of cyclic redundancy bits to include in the uplink control information, and use two stage uplink control information signaling to indicate to the base station how many cyclic redundancy check bits there are in the succeeding stage.