Abstract: Provided are a partial pseudo-randomization processing method, a corresponding apparatus, a device and a storage medium. The method includes performing pseudo-randomization processing on part of N bits b1, b2, . . . , bN to generate new N bits d1, d2, . . . , dN; and encoding the d1, d2, . . . , dN.

Abstract: The present embodiment relates to a method and a system for data transmission and reception of a display device and, more specifically, to a method and a system for repeatedly checking whether an error has occurred in a data driving device configuration for high-speed communication when driving the display device to prevent the image quality degradation due to the configuration error.

Abstract: A memory controller that includes, in one implementation, a memory interface and a controller circuit. The memory interface is configured to interface with a non-volatile memory. The controller circuit is configured to receive a skewed codeword read from the non-volatile memory. The controller circuit is also configured to scan the skewed codeword by inserting or removing a quantity of bits at different locations in the skewed codeword and determining resulting syndrome weights of the skewed codeword. The controller circuit is further configured to determine an adjusted codeword by inserting or removing the quantity of bits at one of the different locations in the skewed codeword which results in a smallest syndrome weight. The controller circuit is also configured to decode the adjusted codeword.

Abstract: A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a connection destination of an input of the convolutional interleaver to one end of one of a plurality of branches; a FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a connection destination of an output of the convolutional interleaver to another end of one of the plurality of branches. The first and second switches switch the connection destination when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the connection destination sequentially and repeatedly among the plurality of branches.

Abstract: A communication device communicating with a base station, where the communication device includes: communication circuitry for performing wireless communication; and control circuitry for selectively switching between a first Physical Uplink Control CHannel (PUCCH) and a second PUCCH, each of the first PUCCH and second PUCCH for transmitting control information from the communication device to the base station. Here, a number of first symbols and a number of first resource blocks of the first PUCCH are different from a number of second symbols and a second number of resource blocks of the second PUCCH, and the first PUCCH and second PUCCH are allocated by the base station for use by the communication device during one or more predetermined periods.

Abstract: Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include performing a first error code correction (ECC) operation on a portion of data, performing a second ECC operation on the portion of data in response to the first ECC operation failing, and performing a third ECC operation on the portion of data in response to the second ECC operation failing.

Abstract: A system for generating a parity check matrix for low-density parity-check (LDPC) codes includes a memory and a processing circuitry that retrieves a base matrix from the memory. The base matrix represents sets of valid and invalid positions for a set of circulant matrices. The processing circuitry determines a value for each valid position based on a heuristic function. The value for each valid position indicates a corresponding circulant matrix of the set of circulant matrices. The processing circuitry replaces each valid position with the corresponding circulant matrix based on the determined value, and each invalid position with a null matrix, to generate the parity check matrix. The parity check matrix thus generated has a high girth and equal distribution of cycles within the parity check matrix.

Abstract: An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a first memory, a second memory, and a controller coupled to the first and second memories. The controller is configured to receive a transaction from a master, the transaction directed to the first memory and comprising an address; re-calculate an error correcting code (ECC) for a line of data in the second memory associated with the address; determine that a non-correctable error is present in the line of data in the second memory based on a comparison of the re-calculated ECC and a stored ECC for the line of data; and in response to the determination that a non-correctable error is present in the line of data in the second memory, terminate the transaction without accessing the first memory.

Abstract: Systems, apparatuses, and methods related to memory device protection are described. A quantity of errors within a memory device can be determined and the determined quantity can be used to further determine whether to utilize single or multiple memory devices for an error correction and/or detection operation. Multiple memory devices need not be utilized for the error correction and/or detection operation unless a quantity of errors within the memory device exceeds a threshold quantity.

Abstract: A computer-implemented method of storing an item of data across a plurality of storage media, the method comprising the steps of: receiving an item of data to be stored; splitting the item of data into N pieces of data; generating M redundancy pieces of data, usable to rebuild the item of data; storing each of the N pieces of data and M redundancy pieces of data on separate storage media of the plurality of storage media at a same offset within a file of the respective storage medium, the files of the storage media containing the N pieces of data and the M redundancy pieces of data being associated as a file set; and storing, separately to the N pieces of data and M redundancy pieces of data, the offset and the file set.

Abstract: An operation method of a storage controller which includes a nonvolatile memory device, the method including: collecting a first parameter indicating a degradation factor of a first memory area of the nonvolatile memory device and a second parameter indicating a degree of degradation occurring at the first memory area, in an initial driving period; selecting a first function model of a plurality of function models based on the first parameter and the second parameter and predicting a first error tendency of the first memory area based on the first function model; determining a first reliability interval based on the first error tendency; and performing a first reliability operation on the first memory area of the nonvolatile memory device based on the first reliability interval.

Abstract: Systems, methods, and apparatus related to data recovery in memory devices. In one approach, a memory device encodes stored data. The memory device reads a codeword from a storage media and determines that a number errors in the codeword exceeds an error correction capability of the memory device. The errors are due, for example, to one or more stuck bits. In response to this determination, one or more data patterns are written to the storage media at the same address from which the codeword is read. The data patterns are read to identify bit locations of the stuck bits. The identified locations are used to correct bit errors of the read codeword that correspond to the identified locations. The corrected code word is sent to a host device (e.g., which requested data from the memory device using a read command).

Abstract: Sub bands can be scheduled with optimal modulation and coding scheme (MCS) when the user equipment reports the sub band channel quality indicator (CQI) and sub band pre-coding matrix index (PMI). The network can use multiple downlink control channels to indicate the sub band resources and the corresponding MCS for that resource allocation. By using multiple downlink control channels to indicate the sub band MCS, the network can use resources more efficiently.

Abstract: Various implementations are directed to systems and methods for maintaining integrity and reliability of data in an SSD device using error correction coding. According to certain aspects, for frames of data having an ECC code with two or more sub-codes, while one sub-decoder is not in use it could be used to start a decode of another frame. By “interleaving” and alternating the frames between sub-decoders, two or more frames can be decoded simultaneously in an efficient manner. This can clearly be extended to more sub-codes (i.e. dimensions greater than two).

Abstract: Methods, systems, and devices for adaptive parity techniques for a memory device are described. An apparatus, such as a memory device, may use one or more error correction code (ECC) schemes, an error cache, or both to support access operations. The memory device may receive a command from a host device to read or write data. If the error cache includes an entry for the data, the memory device may read or write the data using a first ECC scheme. If the error cache does not include an entry for the data, the memory device may read or write the data without using an ECC scheme or using a second ECC scheme different than the first ECC scheme.

Abstract: According to one embodiment, a controller executes a first operation. The first operation includes reading a plurality of data units from a nonvolatile memory and executing a process on the read plurality of data units. The process includes an inverse conversion of a conversion applied to the plurality of data units and first decoding using the plurality of data units that has executed the inverse conversion. The controller acquires first information from one of the plurality of data units that has executed the first operation. The controller compares the acquired first information with an expected value of the first information and re-executes the first operation when the acquired first information and the expected value are not equal to each other.

Abstract: This invention presents a method and apparatus for vertical layered finite alphabet iterative decoding of low-density parity-check codes (LDPC) which operate on parity check matrices that consist of blocks of sub-matrices. The iterative decoding involves passing messages between variable nodes and check nodes of the Tanner graph that associated with one or more sub-matrices constitute decoding blocks, and the messages belong to a finite alphabet. Various embodiments for the method and apparatus of the invention are presented that can achieve very high throughputs with low hardware resource usage and power.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the method comprises: receiving data and a corresponding metadata from a host device; performing a CRC operation upon the data to generate a CRC code; encoding the metadata and the CRC code to generate an adjusted parity code; encoding the data and the adjusted parity code to generate encoded data, wherein the encoded data comprises the data, the adjusted parity code and an error correction code corresponding to the data and the adjusted parity code; and writing the encoded data and the metadata to a page of a block of a flash memory module.

Abstract: This application relates to communicating information between communication devices. A channel coding method is disclosed. A communication device obtains an input sequence of K bits. The communication device encodes the input sequence using a low density parity check (LDPC) matrix H, to obtain an encoded sequence. The LDPC matrix H is determined according to a base matrix and a lifting factor Z. The base matrix includes m rows and n columns, m is greater than or equal to 5, and n is greater than or equal to 27. The lifting factor Z satisfies a relationship of 22*Z?K. According to the encoding method provided in the embodiments, information bit sequences of a plurality of lengths can be encoded for transmission between the communication devices.

Abstract: Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.

Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

Abstract: Provided is a coding unit to determine the number of code block groups, divide an input bit sequence to code block segmentation into code block groups of the number of the code block groups, determine the number of code blocks for each of the code block groups, divide each of the code block groups into code blocks of the number of the code blocks, and apply channel coding to each of the code blocks.

Abstract: A control unit of a multipath data transportation system that optimizes the load of the multiple communication paths of this system when the system transmits a data segment over these paths in parallel with forward error correction. The control unit determines an optimized number of packets to send over each path based on a prediction of quality for each path. The transmitted packets include systematic packets and coded packets.

Abstract: A method for generating and processing a broadcast signal according to an embodiment of the present invention includes encoding broadcast data for one or more broadcast services, encoding first level signaling information including information describing properties of the one or more broadcast services, encoding second level signaling information including information for scanning the one or more broadcast services and generating a broadcast signal including the broadcast data, the first level signaling information and the second level signaling information, wherein the first level signaling information includes user service description (USD) information describing service layer properties with respect to the broadcast services, wherein the USD information includes capability information specifying capabilities necessary to present broadcast content of the broadcast services.

Abstract: A technique for communicating protocol data units, PDUs, in a radio communication from a transmitter (100) to a receiver (200) is described. As to a method aspect of the technique, one or more control messages indicative of Quality of Service, QoS, requirements for the radio communication are received. The QoS requirements include a control command for a reliability of the radio communication and a control command for a latency of the radio communication. A batch of redundant PDUs is transmitted from the transmitter (100) to the receiver (200). A number of the redundant PDUs per batch depends on the control command for the reliability and a temporal spread of the redundant PDUs per batch depends on the control command for the latency.

Abstract: The invention relates to providing atmospheric correction data in a GNSS network-RTK system for correcting GNSS data, wherein a base triangulation that encloses at least part of the reference stations of the GNSS network-RTK system is subdivided into child triangles by means of a recursive division of parent triangles into four child triangles, synthetic data are determined for each of the child triangles based on a triangulation algorithm applied to basic data of the reference stations such that the synthetic data represent a gridded representation of the basic data, and access to correction data is provided, wherein the correction data comprise at least part of the synthetic data arranged in a quad-tree hierarchy.

Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode outer-encoded bits to generate an LDPC codeword including LDPC information bits and parity bits; a puncturer configured to puncture some of the parity bits included in the LDPC codeword; and a mapper configured to map the LDPC codeword except the punctured parity bits to symbols for transmission to a receiver, wherein the puncturer calculates a number of parity bits to be punctured among the parity bits included in the LDPC codeword based on a number of the outer-encoded bits, a number of the LDPC information bits, and a minimum number of parity bits to be punctured among the parity bits included in the LDPC codeword.

Abstract: Provided is an encoding method and device and a decoding method and device for structured LDPC. The encoding method includes: determining a base matrix used for encoding and performing an LDPC encoding operation on a source information bit sequence according to the base matrix and an expansion factor Z corresponding to the base matrix to obtain a codeword sequence, where Z is a positive integer. The base matrix includes multiple submatrices and the submatrices include an upper-left submatrix Hb1 and an upper-left submatrix Hb2, and the upper-left submatrix Hb1 is an upper-left submatrix of the upper-left submatrix Hb2.

Abstract: A method of decoding polar codes based on belief propagation includes conventional belief propagation to decode the polar codes first; when a number of iterations exceeds a predefined upper limit and a cyclic redundancy check fails, the method selects log-likelihood ratio vectors of a plurality of R or L messages from a plurality of log-likelihood ratio vectors generated in each of the iterations and generates another set of log-likelihood ratio vectors (referred to as candidate vector group) to be used as initial values of the R or L messages for a subsequent belief propagation to perform belief propagation decoding iterations and cyclic redundancy check again. Whenever a decoding result passes the cyclic redundancy check, the method exits; otherwise, the method iterates the above procedure until a maximum number of candidate vector groups has been reached.

Abstract: Devices, systems and methods for improving decoding operations of a decoder are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising N columns, wherein each of at least B columns of the parity matrix has a column weight that exceeds a predetermined column weight, processing the N columns based on a message passing algorithm, and determining, based on the processing, a candidate version of the transmitted codeword, wherein the processing for each of the N columns comprises performing a read operation, a variable node update (VNU) operation, and a check node update (CNU) operation on the first set and the second set, the read operation and the CNU operation on each of the at least B columns spanning two or more time-steps.

Abstract: Mapping information management for data storage. A mapping information format without any uncorrectable flag bits (UNC bits) is shown. A controller provides a cyclic redundancy check (CRC) engine. In response to an uncorrectable marking command issued by a host, the controller operates the cyclic redundancy check engine to encode a data pattern with a biased encoding seed to generate biased cyclic redundancy check code. The controller programs the data pattern and the biased cyclic redundancy check code to the non-volatile memory. The data pattern, therefore, will not pass CRC. The uncorrectable marking command works.

Abstract: A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.

Abstract: Polar codes may be generated with a variable block length utilizing puncturing. Some puncturing schemes consider punctured bits as unknown bits, and set the log likelihood ratio (LLR) for those bits to zero; while other puncturing schemes consider punctured bits as known bits, and set the LLR for those bits to infinity. Each of these puncturing schemes has been observed to provide benefits over the other under different circumstances, especially corresponding to different coding rates or different signal to noise ratio (SNR). According to aspects of the present disclosure, both puncturing schemes are compared, and the puncturing scheme resulting in the better performance is utilized for transmission.

Abstract: There are provided a memory controller and a memory system having the same. A memory controller includes: an internal memory for storing error injection information for an error test operation and error test information that is a result of the error test operation; and a central processing unit for receiving first sector data from a host, and performing an error test operation on a memory device according to the error injection information, when the error injection information is included in the first sector data.

Abstract: Multi-gate NOR flash thin-film transistor (TFT) string arrays are organized as three dimensional stacks of active strips. Each active strip includes a shared source sublayer and a shared drain sublayer that is connected to substrate circuits. Data storage in the active strip is provided by charge-storage elements between the active strip and a multiplicity of control gates provided by adjacent local word-lines. The parasitic capacitance of each active strip is used to eliminate hard-wire ground connection to the shared source making it a semi-floating, or virtual source. Pre-charge voltages temporarily supplied from the substrate through a single port per active strip provide the appropriate voltages on the source and drain required during read, program, program-inhibit and erase operations. TFTs on multiple active strips can be pre-charged separately and then read, programmed or erased together in a massively parallel operation.

Abstract: An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises: performing first bit interleaving on a parity bits part of the LDPC codeword to obtain interleaved parity bits; splicing an information bit part of the codeword and the interleaved parity bits into a codeword after the first bit interleaving; dividing the codeword after the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding permutation order (bit-swapping pattern) to form a codeword after second bit interleaving; dividing the codeword after the second bit interleaving into two parts, and writing the two parts into storage space in a column order respectively and reading the two parts from the storage space in a row order respectively to obtain a codeword after third bit interleaving.

Abstract: A bit-interleaved coded modulation (BICM) reception device and a BICM reception method are disclosed herein. The BICM reception device includes a demodulator, a bit deinterleaver, and a decoder. The demodulator performs demodulation corresponding to 1024-symbol mapping. The bit deinterleaver performs group-unit deinterleaving on interleaved values. The interleaved values are generated after the demodulation. The decoder restores information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving. The deinterleaved values corresponds to a LDPC codeword having a length of 64800 and a code rate of 2/15.

Abstract: An encoding circuit includes an allocator to allocate a symbol to bit-strings within a first frame, a converter to convert values of target-bit-strings that exclude a predetermined-bit-string so that, as a region within the constellation is closer to a center of the constellation, a number of symbols allocated in the region is larger, a generator to generate an error-correction-code of the bit-strings, and an insertion circuit to delay the error-correction-code and insert the error-correction-code in the predetermined-bit-string within a second frame that succeeds the first frame, wherein the allocator allocates, to the bit-strings, one symbol that corresponds to the values of the target-bit-strings, the one symbol being within a quadrant that corresponds to a value of the predetermined bit-string, and wherein the converter switches, based on the value of the predetermined-bit-string, association relationships between the values of the target-bit-strings before and after the conversion.

Abstract: A memory controller controls a memory module including data chips and first and second parity chips. The memory controller includes an error correction code (ECC) engine. The ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder receives error information signals associated with the data chips, performs an ECC decoding on a codeword set from the memory module using the parity check matrix to generate a first syndrome and a second syndrome, and corrects bit errors in a user data set based on the error information signals and the second syndrome. The bit errors are generated by a row fault and uncorrectable using the first syndrome and the second syndrome. Each of the error information signals includes row fault information indicating whether the row fault occurs in at least one of memory cell rows in corresponding one of the data chips.

Abstract: A transmitting device is described for a communication system. The transmitting device obtains an information message comprising information bits addressed for a receiving device and encodes the information message to obtain a codeword. The transmitting device rate-matches the codeword to produce a rate-matched codeword comprising systematic bits and parity-check bits. Furthermore, the transmitting device jointly interleaves the systematic bits and parity-check bits of the rate-matched codeword to obtain an interleaved codeword. The systematic bits of the interleaved codeword are mapped to modulation label positions of a modulation constellation with first reliabilities, and the parity-check bits of the interleaved codeword are mapped to modulation label positions of the modulation constellation with second reliabilities.

Abstract: A transmitter is provided. The transmitter includes: a segmenter configured to segment information bits into a plurality of blocks based on one of a plurality of preset reference values; an outer encoder configured to encode each of the plurality of blocks to generate first parity bits; and a Low Density Parity Check (LDPC) encoder configured to encode each of the plurality of blocks and the first parity bits to generate an LDPC codeword including second parity bits, wherein the one of the preset reference values is determined depending on at least one of a code rate used to encode each of the plurality of blocks and the first parity bits and whether to perform repetition of at least a part of the LDPC codeword in the LDPC codeword.

Abstract: Embodiments of this application provide a method for processing information bits in a wireless communication network. A device obtains a Polar encoded bit sequence, then divide the Polar encoded bit sequence into g groups that are of equal length N/g, wherein g is 32. The device block interleaves the g groups to obtain an interleaved bit sequence according to a sequence S, wherein the sequence S comprises: group numbers of the g groups, wherein a group whose number is 0 is the first element in the sequence S, wherein a group whose number is 12 is the 17th element in the sequence S, wherein a group whose number is 31 is the 32nd element in the sequence S, wherein the S is an integer and output the interleaved bit sequence.

Abstract: The disclosed systems, structures, and methods are directed to encoding and decoding information for transmission across a communication channel. The method includes dividing the information between m parallel polar codes such that each of the m parallel polar codes includes a plurality of information bits, and splitting the information bits in each of the m parallel polar codes into a private part and a public part. The public part includes an information section and a repetition section, wherein the information bits of the public part are arranged in the information section. Bits in the information section of the public part of each of the m parallel polar codes are repeated in the repetition section of the public part of at least a second one of the m parallel polar codes.

Abstract: Several embodiments of systems incorporating memory sub-systems are disclosed herein. In one embodiment, a memory sub-system can include a memory component and a processing device configured to perform a background scan on a memory region of the memory component. In some embodiments, the background scan includes generating a bit error count (BEC) of a codeword saved on the memory region and saving statistical information corresponding to the BEC of the codeword to a histogram statistics log. In some embodiments, when the BEC of the codeword is greater than a BEC threshold, a refresh operation is scheduled for the memory region and/or logged. In these and other embodiments, when one or more error recovery error correction code (ECC) operations do not correct bit errors in the codeword, a refresh and/or retirement operation is schedule for the memory region and/or is logged.

Abstract: Technologies for performing encoding of data symbols for column read operations include a device having a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to obtain a data set to encode. The data set is defined by a set of data symbols. The circuitry is also configured to determine a set of codewords to encode the data symbols of the data set, including defining each codeword with a set bit distance of at least two from every other codeword in the set of codewords. Additionally, the circuitry is configured to write the data set to the memory as a function of the determined set of codewords.

Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver includes a block interleaver formed of a plurality of columns each comprising a plurality of rows, and the block interleaver is configured to divide the plurality of columns into at least two parts and interleave the LDPC codeword.

Abstract: Apparatuses and methods related to correcting errors can include using FD decoders and AD decoders. Correcting errors can include receiving input data from the memory array, performing a plurality of operations associated with an error detection on the input data, and providing, based on processing the input data, output data, a validation flag, and a plurality of parity bits to a second decoder hosted by a controller coupled to the memory device.

Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder which encodes input bits including outer encoded bits to generate an LDPC codeword including the input bits and parity bits to be transmitted to a receiver in a current frame; a puncturer which punctures a part of the parity bits which is not transmitted in the current frame; and an additional parity generator which selects at least a part of the parity bits to generate additional parity bits transmitted to the receiver in a previous frame of the current frame, wherein a number of the additional parity bits is determined based on a number of the outer encoded bits and a number of the parity bits left after the puncturing.

Abstract: Disclosed are devices, systems and methods for error correction decoding using an iterative decoding scheme. An error correction circuit includes a node processor to perform a plurality of iterations for updating values of one or more variable nodes and one or more check nodes using initial values assigned to the one or more variable nodes, respectively, a trapping set detector to detect a trapping set in at least one of the plurality of iterations by applying a predetermined trapping set determination policy, and a post processor to reduce at least one of the initial values or invert at least one of values of the variable nodes corresponding to an iteration in which the trapping set is detected, upon detection of the trapping set.

Abstract: Methods, systems, and computer readable media for using variable metadata tags. A method occurs at a metadata processing system for enforcing security policies in a processor architecture. The method comprises: receiving, at the metadata processing system, a tag associated with a word in memory, wherein the tag indicates a memory location containing metadata associated with the word and wherein the tag length is at least in part determined using tag usage frequency; obtaining the metadata from the memory location, and determining, using the metadata, whether the word or a related instruction violates a security policy.