Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

Abstract: An apparatus for smart integrated cyclic data transport is provided. The apparatus may preserve the consistency and integrity of a file during the transfer of the file from a source system to a target system. The apparatus includes an orchestration subsystem. The orchestration subsystem includes an analyzer/generator module. The analyzer/generator module executes an algorithm on the file at the source location. An output is generated from the executed algorithm. The apparatus includes a consistency module. The consistency module pre-checks the output at the source location for pretransfer validation and creates a copy of the output. The copy may preserve the consistency and the integrity of the file. The apparatus includes a data transfer subsystem which transfers the file and the output from the source system to the target system. The apparatus may also include a validation subsystem for validating the integrity and consistency of the file.

Abstract: The present disclosure includes apparatuses and methods for monitoring error correction operations performed in memory. A number of embodiments include a memory and circuitry configured to determine a quantity of erroneous data corrected during an error correction operation performed on soft data associated with a sensed data state of a number of memory cells of the memory, determine a quality of soft information associated with the erroneous data corrected during the error correction operation performed on the soft data, and determine whether to take a corrective action on the sensed data based on the quantity of the erroneous data corrected during the error correction operation and the quality of the soft information associated with the erroneous data corrected during the error correction operation.

Abstract: The present invention relates to a method for generating, by a transmission device, a packet in a broadcasting and/or communication system, the method comprising the steps of: generating a first source symbol block consisting of one or more source symbols with the same length using a source packet block consisting of one or more source packets; performing a forward error correction (FEC) coding operation on the first source symbol block; generating a second source symbol block containing information about each source packet constituting the source packet block; and generating a second recovery symbol block with one or more recovery symbols by performing an FEC coding operation on the second source symbol block.

Abstract: A pipelined decoder for storaging of soft bits and hard bits associated with code blocks of a transmission. The proposed circuit reduces the amount of memory needed at the receiver level for soft bits and hard bits, in a pipelined decoder. Namely, with the solution of the subject application, both the LLRs and hard bits associated with a given code block are available when the CRC value is determined. Hence, the effect obtained non-pipelined decoder is achieved by the pipelined decoder of the subject application. A receiver for a wireless communication system, a method and a computer program are also disclosed.

Abstract: Systems, methods, and computer readable media for media management provide a derived quantitative data of quality for video media files. The method embodiment comprises receiving a request for a video media file, identifying one or more video media files associated with the request, measuring at least one audio or visual quality associated with each video media file by analyzing at least one of: compression artifacts or grading for the each video media file, generating quantitative data based on the measured at least one audio or visual quality for the each video media file, and returning the quantitative data associated with the each video media file. Other features include the ability to compare, archive, filter, sort and select video media files based on the quantitative data.

Abstract: A method for accessing a flash memory module includes: sequentially writing Nth?(N+K)th data to a plurality of flash memory chips of the flash memory module, and encoding the Nth?(N+K)th data to generate Nth?(N+K)th ECCs, respectively, where the Nth?(N+K)th ECCs are used to correct errors of the Nth?(N+K)th data, respectively, and N and K are positive integers; and writing the (N+K+1)th data to the plurality of flash memory chips of the flash memory module, and encoding the (N+K+1)th data with at least one of the Nth?(N+K)th ECCs to generate the (N+K+1)th ECC.

Abstract: A decoder includes a channel mapper configured to generate a plurality of channel reception values based on hard decision information and soft decision information, a strong error detector configured to determine whether a strong error has occurred using a plurality of check node messages and the channel reception values and to correct the channel reception values according to a determination result to produce corrected channel reception values, a variable node unit configured to generate a plurality of variable node messages using the check node messages and the corrected channel reception values, and a check node unit configured to generate the check node messages using the variable node messages. The variable node unit includes a plurality of variable nodes and the check node unit includes a plurality of check nodes.

Abstract: The present technology relates to a data processing device and a data processing method so that an LDPC code with a good bit error rate is provided. An LDPC encoder encodes by an LDPC code whose code length is 16200 bits and code rate is 8/15. The LDPC code includes information bits and parity bits. A parity check matrix H includes an information matrix part corresponding to the information bits of the LDPC code and a parity matrix part corresponding to the parity bits. The information matrix part of the parity check matrix H is represented by a parity check matrix initial value table that indicates a position of an element 1 of the information matrix part for each 360 columns. The present technology is applicable to a case in which LDPC encoding and LDPC decoding are performed.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for performing communications using a bonded channel across multiple channels.

Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to early termination techniques for low-density parity-check (LDPC) decoder architecture.

Abstract: A memory system includes memory modules having a number of sets of memory devices including data memory devices for data and error correction code (ECC). The ECC memory devices carry ECC symbols in order to facilitate Redundant Array of Independent Memory (RAIM) functionalities for the memory modules. A host receives and decodes the ECC symbols and executes RAIM operations. The host and the memory modules are coupled by a number of channels, one channel per each set of the memory devices.

Abstract: Disclosed is a method for transmitting a broadcast signal. A method for transmitting a broadcast signal according to an embodiment of the present invention comprises the steps of: delivery layer processing broadcasting service data and signaling information for the broadcasting service data; UDP/IP encapsulating the broadcasting service data and signaling information for the broadcasting service data; and physical layer processing the broadcasting service data and signaling information for the broadcasting service data.

Abstract: A plurality of units have a transmitter and a receiver. The transmitter puts the unit's own data string into a coding data array using first array information, and calculates an error-correcting code based on the data array in which 0 is put except for the data string. The receiver decodes a data array in which a data string is put into the coding data array based on second array information, using an error-correcting code. The transmitter adds the unit's own data string to a data string, puts the unit's own data string into the coding data array using the first array information on the data string, calculates an error-correcting code for the data array in which 0 is put except for the data string, and determines an error-correcting code of a transmission packet by addition of an error-correcting code of a received packet and the calculated error-correcting code.

Abstract: Techniques are described for decoding a first message. In one example, the techniques include obtaining a second message comprising reliability information corresponding to each bit in the first message, performing a soft decision decoding procedure on the second message to generate a decoded codeword, wherein the soft decision decoding procedure comprises a joint decoding and miscorrection avoidance procedure, and outputting the decoded codeword.

Abstract: A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.

Abstract: For decoding messages, a decoder exchanges single-bit messages for a data channel between a plurality of M parity nodes and a plurality of N symbol nodes. Each parity node has one or more adjacent symbol nodes with a plurality of edges between the parity node and each adjacent symbol node. An extrinsic decision and an extrinsic parity value are calculated based on a time-varying lookup table. The lookup table stores the locally maximum-likelihood extrinsic decision for a quantized number of data channel states as a function of adjacent extrinsic parity values.

Abstract: A communication device in embodiments is a quantum key distribution device connectable to another quantum key distribution device through a quantum communication channel to share an encryption key therebetween, and includes a common processing unit, one or more individual processing units, and a distribution unit. The common processing unit outputs intermediate data based on bit information obtained by transmitting or receiving sequence of photons with the another quantum key distribution device through the quantum communication channel. Each individual processing unit generates or provides the encryption key in accordance with the intermediate data. The distribution unit distributes the intermediate data that is output from the common processing unit to two or more distribution destination that include the individual processing units.

Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.

Abstract: A method is provided of detecting packet error during a transmission of a flit along a path from a source node through one or more intermediate nodes to a destination node. The method includes identifying a stalled node, from among the source and intermediate nodes, which prevents the transmission of the flit. The method includes generating, by a transmitter of the stalled node, a CRC for the flit and placing the CRC in an IDLE pattern of the flit. The method includes checking, by a receiver of an intermediate node subsequent to the stalled node, the CRC for the flit. The method includes sending, by a transmitter of the intermediate node, an error code to the destination node, and releasing the nodes from the intermediate node to and including the destination node, responsive to a detection, by the intermediate node, of an error in the CRC for the flit.

Abstract: A method is provided of detecting packet error during a transmission of a flit along a path from a source node through one or more intermediate nodes to a destination node. The method includes identifying a stalled node, from among the source and intermediate nodes, which prevents the transmission of the flit. The method includes generating, by a transmitter of the stalled node, a CRC for the flit and placing the CRC in an IDLE pattern of the flit. The method includes checking, by a receiver of an intermediate node subsequent to the stalled node, the CRC for the flit. The method includes sending, by a transmitter of the intermediate node, an error code to the destination node, and releasing the nodes from the intermediate node to and including the destination node, responsive to a detection, by the intermediate node, of an error in the CRC for the flit.

Abstract: In some examples, an interactive audio system includes a receiver for receiving a broadcasted radio frequency (RF) carrier signal. The system may demodulate a portion of the RF carrier signal to receive a demodulated output signal. For example, the demodulated output signal may include a demodulated audio program having embedded data contained within the demodulated audio signal. The system may extract the embedded data from the demodulated audio program. The system may present information related to the extracted embedded data on a display and/or may send at least a portion of the extracted embedded data to another device.

Abstract: A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

Abstract: Receivers including estimation unit (EU) circuits and related processing techniques for wireless systems are provided. Efficient expressions for quadrature amplitude modulation (QAM) symbol mean and variance calculations are utilized with efficient expressions and implementations that are adaptive to different orders of QAM formats. An EU circuit includes a mean estimation unit (MEU) circuit and/or second moment estimation unit (SEU) circuit. Each estimation unit circuit is configured to receive a variable QAM normalization factor so that the circuit can be adapted to different QAM orders. Each MEU or SEU circuit can be configured for sequential and/or parallel processing. A pool including multiple MEU circuits and/or a pool including multiple SEU circuits is provided in one embodiment, with a control unit for configuring and reconfiguring the pools of circuits for mean and variance estimation for data streams of QAM symbols.

Abstract: Storing data is described herein, including: receiving a first data, wherein the first data comprises a portion of a data block; encoding at least a portion of the first data to generate a codeword; dividing the codeword into a plurality of codeword portions; storing a first codeword portion; and sending at least a subset of codeword portions other than the first codeword portion among the plurality of the codeword portions to a plurality of nodes. Receiving acknowledgement of storage of data is also described herein, including: determining whether a first acknowledgement from a first node is received, wherein the first data comprises a portion of a data block; determining whether a second acknowledgement from the first node is received; and in response to receipt of the first acknowledgement and receipt of the second acknowledgment, determining that the first data has been stored.

Abstract: A first set of data is encoded using a first code to obtain a first-code codeword which includes the first set of data and first-code parity information. The first set of data is stored on a plurality of drives, wherein the first set of data is distributed amongst the plurality of drives. A second set of data is encoded using a second code to obtain a second-code codeword which includes the second set of data and second-code parity information. The second-code codeword is stored on the plurality of drives, wherein the second set of data and second-code parity information are distributed amongst the plurality of drives.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array with a plurality of memory cells, an ECC circuit with an encoder for generating error correcting codes and a decoder for performing correcting processing, a page buffer capable of storing the write data, corrected data, and the error correcting codes, and a multiplexer having a first input terminal coupled to the encoder, a second input terminal coupled to the page buffer, and an output terminal coupled to the memory cell array, in which the first input terminal is selected when writing the write data in the plurality of memory cells and the second input terminal is selected when writing the corrected data in the plurality of memory cells.

Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.

Abstract: The present invention relates to an optical transceiver using FEC, an optical transceiving system comprising the same, and a remote optical wavelength control method and, specifically, to an optical transceiver using FEC, the optical transceiver comprising: a laser diode driver (LDD) for driving a laser diode (LD) for outputting light; a transmitter optical sub-assembly (TOSA) for transmitting an optical signal received from the LD driver; a receiver optical sub-assembly (ROSA) for receiving the optical signal from the transmitter optical sub-assembly; a micro controller unit (MCU) for controlling the transmitter optical sub-assembly and the receiver optical sub-assembly and analyzing the optical signal; and a forward error correction (FEC) which is controlled by the micro controller unit and generates the optical signal by including, in an overhead excess data frame, control or monitoring request information of a subscriber-side base station.

Abstract: A message-passing iterative decoding method of an associated LFSR sequence (or M-sequence) as a simplex code, to a parity matrix H. The method includes determining a set of parity polynomials with a low weight obtained by combining the parity equations of the matrix H. For each combination of K such polynomials of this set, an extended parity matrix Hext is built by concatenating elementary parity matrices associated with the parity polynomials of said combination. The combination of parity polynomials leading to a bipartite graph not having cycles with a length 4 and having a minimum number of cycles with lengths 6 and 8 is selected. Then, the LFSR sequence is decoded using the bipartite graph corresponding to the selected combination. This decoding method enables the false-alarm rate to be substantially reduced.

Abstract: A first communication device calculates a plurality of data error codes for detecting an error in a plurality of data fields by using the plurality of data fields. The first communication device generates a packet comprising the plurality of data fields and the plurality of data error codes, and then transmits the packet which is generated to a second communication device.

Abstract: A CRC calculation method and apparatus are provided. According to technical solutions provided in embodiments of the present invention, a binary sequence of a first pulse includes the first packet and the second packet. The number of bits in the first packet is unequal to the number of bits in the second packet. The first packet is distributed to a first CRC calculation circuit. The second packet is distributed to a second CRC calculation circuit. CRC of the first packet is obtained by calculation by using the first CRC calculation circuit. CRC of the second packet is obtained by using the second CRC calculation circuit. If the foregoing technical solutions are applied to the foregoing application scenario of flexible Ethernet, CRC of packets with different lengths and from different transmitters may be separately calculated. Therefore, the foregoing technical solutions may be better applied to the scenario of flexible Ethernet.

Abstract: An apparatus for decoding is disclosed. The apparatus includes a memory and a processor coupled to the memory. The processor is configured to obtain a first codeword comprising one or more information bits and one or more parity bits, obtain a first parameter corresponding to a code rate of the first codeword, and decode the first codeword using a multi-rate decoder to generate a decoded codeword. The multi rate decoder performs a code reconstruction procedure on the first codeword to generate a reconstructed codeword, and decodes the reconstructed codeword. The processor is further configured to output the decoded codeword.

Abstract: An apparatus includes an interface, main and secondary processing modules, and circuitry. The interface is configured to receive input data to be processed in accordance with a GLDPC code defined by a parity-check-matrix including multiple sub-matrices, each sub-matrix including a main diagonal and one or more secondary diagonals, and each of the main and secondary diagonals includes N respective block matrices. The main processing module is configured to calculate N first partial syndromes based on the input data and on the block matrices of the main diagonals. The secondary processing module is configured to calculate N second partial syndromes based on the input data and on the block matrices of the secondary diagonals. The circuitry is configured to produce N syndromes by respectively combining the N first partial syndromes with the N second partial syndromes, and to encode or decode the input data, based on the N syndromes.

Abstract: A data storage system can consist of a number of data storage devices each having a non-volatile memory, a memory buffer, and an error detection module. The memory buffer may store a first data block comprising a front-end first-level error detection code assigned by the error detection module. The non-volatile memory can consist of a second data block having a back-end first-level error detection code and a second-level error detection code each assigned by the error detection module.

Abstract: Disclosed is a fast encoding method suitable for Reed-Solomon codes with a small number of redundancies including a step of setting parity-check matrices including presetting parity-check matrices H2 and H3 in which the number of redundant symbols s in the Reed-Solomon codes is 2 or 3. The method also includes a step of constructing the shortened Reed-Solomon codes including constructing (k, s) Reed-Solomon codes over a finite field GF(2m) that conform to the preset parity-check matrix; using k points {oi}i=1k in the R-points input {oi}i=0R?1 as message symbols, and setting the remaining points to zero; a step of encoding including recursively processing the R-points input to obatin s redundant symbols, achieving the encoding of Reed-Solomon codes with a small number of redundancies. Embodiments of the present invention further include an electronic device and a computer-readable storage medium.

Abstract: The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 64800 bits and an encoding rate r is 7/15, 9/15, 11/15, or 13/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.

Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

Abstract: The present disclosure relates to a method and a device for transmitting and receiving a packet in a communication system. A method for transmitting a packet according to the present disclosure comprises the steps of: generating at least one source block including source packets for transmitting contents; performing forward error correction (FEC) encoding and generating at least one reconstructed block including reconstructed packets for restoring the source packets; and transmitting signaling information including packet identification information on the at least one source block and a packet stream including the source packets and the reconstructed packets, wherein header information of the reconstructed packets includes the number of source packets included in each source block according to the packet identification information, and information indicating the start numbers of the source packets included in the each source block.

Abstract: Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors.

Abstract: In a transmission method according to one aspect of the present disclosure, a cyclic shift is applied to each row of an interleaver matrix in which each of a plurality of rotation components of each section is replaced with a cell, in which two rotation components are set to a real component and an imaginary component, by using (cyclic shift value k×floor(Q/max{D,(NRF×NC)}/2)) cells allocated to the row, and a value of k mod NRF varies in at least two rows of one section portion of a combined complex interleaver matrix in the cyclic shift.

Abstract: Polar encoding using two or more concatenated cyclic redundancy check (CRC) data values may enhance CRC-aided successive cancellation list decoding in a communication system. A polar encoding method may include determining first CRC data from source data, combining the source data and the first CRC data to form first combined data, determining second CRC data from the first combined data, and combining the source data, the first CRC data, and the second CRC data to form second combined data.

Abstract: A low-density parity-check (LDPC) apparatus and a matrix trapping set breaking method are provided. The LDPC apparatus includes a logarithm likelihood ratio (LLR) mapping circuit, a variable node (VN) calculation circuit, an adjustment circuit, a check nodes (CN) calculation circuit and a controller. The LLR mapping circuit converts an original codeword into a LLR vector. The VN calculation circuit calculates original V2C information by using the LLR vector and C2V information. The adjustment circuit adjusts the original V2C information to get adjusted V2C information in accordance with a factor. The CN calculation circuit calculates the C2V information by using the adjusted V2C information, and provides the C2V information to the VN calculation circuit. The controller determines whether to adjust the factor. When LDPC iteration operation falls into matrix trap set, the controller decides to adjust the factor so that the iteration operation breaks away from the matrix trap set.

Abstract: A method for a first communication device transmitting data to a second communication device, according to one embodiment of the present invention, comprises the steps of: the first communication device generating a safety unique identifier by using a unique identifier of the first communication device and a unique identifier of the second communication device, in order to confirm the validity of connection between the first communication device and the second communication device; the first communication device calculating a data error detection code for detecting an error by using the safety unique identifier and the data; the first communication device generating a packet comprising the data and the data error detection code; and the first communication device transmitting the packet to the second communication device.

Abstract: A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.

Abstract: Disclosed is a broadcast signal transmitting apparatus, a broadcast signal receiving apparatus, and a broadcast signal transceiving method in a broadcast signal transceiving apparatus.

Abstract: Provided is a data transmitting and receiving apparatus that may process a signal to be transmitted using a faster-than-Nyquist (FTN) method. The data transmitting and receiving apparatus may perform low-density parity-check (LDPC) encoding on data to be transmitted using a first matrix having a first degree based on a preset reference and a second matrix having a single diagonal matrix structure, independently perform interleaving and symbol mapping on each of an information bit and a parity bit of the data, accelerate an output signal by a transmission rate based on the FTN method, and transmit the data.

Abstract: A control circuit configured to associate a plurality of memory with an error correction scheme. The control circuit including an internal operation circuit configured to generate an internal command based on an access unit of the plurality of memory. The control circuit including a storage circuit configured to store information on the access unit of the plurality of memory.

Abstract: A method for transmitting information in a transmission time interval by a device in a wireless communication system is provided. The method includes fragmenting the information into two or more information fragments, if a size of the information is greater than a transportable size of unit transmission resource used for transmission of the information; generating a protocol data unit (PDU) including fragmentation information and one of unfragmented information and a fragmented information fragment; and transmitting the PDU through the unit transmission resource. The fragmentation information includes an identity of a specific unit transmission resource within the at least one transmission time interval and fragmentation control (FC) information indicating at least one of whether the information is fragmented or not and a position of the fragmented information fragment within the two or more information fragments.