Abstract: A memory system includes a nonvolatile memory and a memory controller configured to perform reading of a concatenation code from the nonvolatile memory in response to an external command, the memory controller including a decoder circuit which decodes a reception word in the concatenation code. The decoder circuit includes a first external code decoder that performs decoding on an external code portion, an internal code in-error bit estimation unit that performs estimation of an in-error bit on a bit sequence from the first external code decoder, based on a rule for an internal code in the concatenation code, and outputs a set of in-error bits that is obtained by the estimation, and a second external code decoder that performs decoding which uses the set of in-error bits that is output from the internal code in-error bit estimation unit, on the bit sequence from the first external code decoder.

Abstract: A method and system for storing hints in poisoned data of a computer system memory includes receiving poisoned data in a component of the system; forwarding the poisoned data to a memory controller of the system; and forwarding additional data regarding the poisoned data to a memory controller. The memory controller writes the poisoned data to the system memory wherein the written poisoned data includes a poison signature and a hint based on the additional data regarding the poisoned data; and when the written poisoned data is read signaling a system error and returning the poison signature and the hint to a system software of the system.

Abstract: Aspects of the present disclosure relate to low density parity check (LDPC) coding utilizing LDPC base graphs. Two or more LDPC base graphs may be maintained that are associated with different ranges of overlapping information block lengths. A particular LDPC base graph may be selected for an information block based on the information block length of the information block. Additional metrics that may be considered when selecting the LDPC base graph may include the code rate utilized to encode the information block and/or the lift size applied to each LDPC base graph to produce the information block length of the information block.

Abstract: Systems, apparatuses, and methods for reliably transmitting data over voltage scaled links are disclosed. A computing system includes at least first and second devices connected via a link. In one implementation, if a data block can be compressed to less than or equal to half the original size of the data block, then the data block is compressed and sent on the link in a single clock cycle rather than two clock cycles. If the data block cannot be compressed to half the original size, but if the data block can be compressed enough to include error correction code (ECC) bits without exceeding the original size, then ECC bits are added to the compressed block which is sent on the link at a reduced voltage. The ECC bits help to correct for any errors that are generated as a result of operating the link at the reduced voltage.

Abstract: Input bits are encoded into codewords that include coded bits. Encoding involves applying a first set of polar encoding matrices GY of prime number dimension Y to the input bits to produce output bits, and applying a second set of polar encoding matrices GZ of prime number dimension Z to the output bits to produce the codeword. One or both of GX and GY could be non-2-by-2. Such kernel design and other aspects of code construction, including reliabilities and selection of sub-channels for code construction, non-CRC-aided error correction, and code shortening and puncturing, are discussed in further detail herein.

Abstract: A memory system, a reading method and a writing method are provided. The memory system includes a memory controller and a memory array electrically connected to the memory controller. A parity information is stored in the memory array. The memory array includes a plurality of memory devices. The reading method comprises the following steps: A reading command for requesting a user data stored in the memory array is received from a host interface. The user data is recovered according to the parity information when the user data is error at one of the memory devices. The user data, which is recovered, is transferred to the host interface and the user data is refreshed.

Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.

Abstract: This application provides a channel encoding method and apparatus in wireless communications. The method includes: performing CRC encoding on A to-be-encoded information bits, to obtain a first bit sequence, where the first bit sequence includes L CRC bits and A information bits; performing an interleaving operation on the first bit sequence, to obtain a second bit sequence, where a first interleaving sequence used for the interleaving operation is obtained based on a system-supported maximum-length interleaving sequence with the length of Kmax+L, and Kmax is a maximum information bit quantity corresponding to the maximum-length interleaving sequence and a preset rule, and a length of the first interleaving sequence is equal to A+L. Therefore, during distributed CRC encoding, when an information bit quantity is less than the maximum information bit quantity, an interleaving sequence required for completing an interleaving process is obtained based on the system-supported maximum-length interleaving sequence.

Abstract: Techniques and mechanisms to identify an error to a host that controls a memory component based on communications based on a Mobile Industry Processor Interface (MIPI) Unified Protocol specification. In an embodiment, the memory component detects an error based on a data frame sent to the memory component from the host. In response to detecting the error, the memory device sends to the host a negative acknowledgment control (NAC) message including a negative acknowledgment identifier and an error code identifying an error type of the detected error. The NAC message is based on a NAC frame structure defined by the MIPI Unified Protocol specification. In another embodiment, the host receives the NAC message and stores error information based on the error code of the NAC message. The stored error information is accessible for purposes such as performance evaluation of the host and debugging.

Abstract: A device includes a low density parity check (LDPC) decoder that is configured to receive a representation of a codeword. The LDPC decoder includes a circuit configured to set a message length of a decoding message at least partially based on an error metric associated with the representation of the codeword. The LDPC decoder also includes a processing unit including a first group of components and a second group of components. The processing unit configured to selectively couple the first group of components to the second group of components based on the message length of the decoding message.

Abstract: A method for generating encoded data includes: generating at least one local LDPC matrix and a global LDPC matrix, the global LDPC matrix relating to each of the at least one local LDPC matrix; repeatedly selecting one of the at least one local LDPC matrix as a target local LDPC matrix until a number t of the target local LDPC matrices are selected, where t is a user-defined number that is greater than one; generating a block matrix that includes the target local LDPC matrices; generating a primary LDPC matrix that includes a first primary matrix part relating to the block matrix, and a second primary matrix part relating to the global LDPC matrix; and encoding data based on the primary LDPC matrix.

Abstract: Embodiments of the present disclosure relate to method and apparatus for data protection. For example, there is provided a computer-implemented method. According to the computer-implemented method, it only needs to read the changed data to be protected rather than the entire data to be protected during the procedure of generating a redundant data portion for the changed data to be protected.

Abstract: Methods, apparatus, systems and articles of manufacture to determine and apply polarity-based error correction code are disclosed. In some examples, the methods and apparatus create an array by setting a first set of bit locations of a code word to have a first value and setting a second set of bit locations of the code word to have a second value different from the first value. In some examples, when the array satisfies a parity check, the methods and apparatus determine that bit locations having the first value from the array form a polarity-based error correction code.

Abstract: Systems and methods for detection of security breaches in intravehicular communication systems are disclosed. In some embodiments, this may include intravehicular communication using messages sent with a checksum and a dynamic mathematical operator field. Errors in the checksum may be interpreted as ordinary transmission errors, whereas errors in the dynamic mathematical operator field may be interpreted as potential threats. Repeated errors in the dynamic mathematical operator, and/or unexpected messages in the intravehicular communications, may be interpreted as confirmed hacking. Upon confirmation of hacking, a warning may be issued to an operator and a vehicle safe mode may be entered, including restricting vehicle functionality.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). Disclosed is an apparatus for performing an iteration decoding scheme for a Low Density Parity Check (LDPC) code. The apparatus includes a receiver configured to receive an encoded signal based on a parity matrix set for a plurality of variable nodes including a first variable node with a first degree and a second variable node with a second degree. The apparatus further includes a processor configured to determine at least one variable node based on a first threshold determined according to the first degree and a second threshold determined according to the second degree among the plurality of variable nodes and to generate decoded data from the signal based on the at least one determined variable node.

Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to an efficient list decoder for list decoding low density parity check (LDPC) codes.

Abstract: A system for performing an integrity verification based on a distributed delegator and verifying an integrity of a plurality of individual devices based on a network includes: a first individual device which is an integrity verification target of the plurality of individual devices; a second individual device configured to vicariously verify the verification target device of the plurality of individual devices; and a remote device management server configured to select the second individual device of the plurality of individual devices as a verification delegator, and to receive a result of integrity verification of the first individual device by the second individual device.

Abstract: Disclosed in embodiments of the present disclosure are a polar code encoding method and device. The method includes: utilizing a common information bit set to represent each of m polar code blocks, the polar codes in each polar code block having the same code length and different code rates, and m being greater than or equal to 2; according to the common information bit set corresponding to the polar code block, acquiring an information bit set corresponding to each polar code in the polar code block; and according to the information bit set corresponding to each polar code in the polar code block, conducting polar code encoding on information to be encoded, thus reducing polar code representation overhead, and solving the problem in the prior art of excessively high polar code representation overhead.

Abstract: A system for register error detection is described, the system comprising: a plurality of addressable registers comprising sets of registers, the registers in each set having contiguous addresses; a cyclic redundancy check generator coupled to the addressable registers and configured to determine a cyclic-redundancy-check result for each set of registers from the values of each of the respective set of registers; a controller coupled to the registers and the cyclic-redundancy-check generator.

Abstract: Examples described herein generally relate to a computer device including a memory and at least one processor configured to execute a process and manage the memory for the process. The processor is configured to receive a registration from the process for notifications regarding errors in the memory. The processor is configured to create first metadata regarding content of a portion of the memory allocated to the process when a physical memory address associated with a virtual address for the portion of memory is made non-writable to the process. The processor is configured to detect an error in the memory by comparing second metadata for current contents of the portion of memory to the first metadata. The processor is configured to provide a notification to the process in response to detecting the error. In some implementations, the processor is configured to determine whether the error is correctable based on the metadata.

Abstract: Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a hard decision decoding on a codeword, determining which check nodes are satisfied and which check nodes are unsatisfied after the hard decision decoding, scheduling a check node processing order by moving at least one unsatisfied check node to be processed ahead of at least one satisfied check node and performing a soft decision decoding on the codeword according to the check node processing order.

Abstract: A memory system includes a memory device, a command clock (CK_t clock) that provides a first clock signal at a first frequency, and a data path clock (WCK_t clock) that provides a second clock signal at a second frequency different than the first frequency. Data path circuitry is synchronized with the WCK_t clock and provides an error detection code (EDC) hold pattern during an idle state. EDC hold pattern synchronization logic synchronizes a start of transmission of the EDC hold pattern synchronous to the CK_t clock.

Abstract: A method and apparatus is described for assigning columns of an LDPC H matrix to a plurality of decoding logics for efficient decoding of codewords. The rows of the LDPC H matrix are evaluated in a number of different orderings, and for each row in each ordering, a number of columns containing non-zero circulants are determined that cannot be evenly distributed to a plurality of decoding logics. As each row is evaluated, one or more columns of the LDPC H matrix are assigned to temporary bins for storage. After the LDPC H matrix has been evaluated a plurality of times, the arrangement that resulted in the fewest number of “mismatched” columns is selected, and the columns of the LDPC H matrix that were assigned to the temporary storage bins for that particular row arrangement is used to assign the columns in the bins to the plurality of decoding logics.

Abstract: A transmission device is implemented in a first node in an optical transmission system in which a frame is transmitted from the first node to a second node via an optical interface. The transmission device includes a decision unit that decides whether a type of a first error correction code used in the first node is the same as a type of a second error correction code used in the second node. When a type of the first error correction code is the same as a type of the second error correction code, the transmission device transmits the frame to which an error correction code used in the first node is added to the second node without terminating the error correction code.

Abstract: An information processing apparatus, comprising: a matrix inversion calculating unit that includes a higher level matrix inversion processing block containing at least four lower level matrix inversion processing blocks and two assistant processing blocks and; a control unit that reconfigures an internal structure of the matrix inversion calculating unit depending on the input matrix size.

Abstract: The present disclosure, in various embodiments, describes technologies and techniques for detecting errors in a non-volatile memory (NVM) device prior to performing re-training/recalibration. A processing device in a NVM controller detects a cyclic redundancy check (CRC) condition for detecting error in the NVM device, and a re-training condition that is based on the CRC condition. A CRC circuit generates CRC code when a CRC condition is detected, and the processing is configured to compare CRC code received from the NVM controller with the generated CRC code to detect error. A calibration circuit then re-trains the NVM device if the CRC circuit detects error and the re-training condition has been met.

Abstract: Certain aspects of the present disclosure generally relate to techniques for enhanced puncturing and low-density parity-check (LDPC) code structure. A method for wireless communications by a transmitting device is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a base matrix having a first number of variable nodes and a second number of check nodes; puncturing the code word according to a puncturing pattern designed to puncture bits corresponding to at least two of the variable nodes to produce a punctured code word; adding at least one additional parity bit for the at least two punctured variable nodes; and transmitting the punctured code word.

Abstract: A method for use in a network communication system including a plurality of electronic controllers that communicate with each other via a bus in accordance with a Controller Area Network (CAN) protocol includes determining whether or not content of a predetermined field in a transmitted frame meets a predetermined condition indicating fraud, transmitting an error frame before an end of the frame is transmitted in a case where it is determined that the frame meets the predetermined condition, recording a number of times the error frame is transmitted, for each identifier (ID) represented by content of an ID field included in a plurality of frames which has been transmitted, and providing a notification in a case where the number of times recorded for an ID exceeds a predetermined count.

Abstract: According to an embodiment, a data generating device includes a first generator, an obtainer, a second generator, a verifier, and an operation selector. The first generator generates device-specific first data. The obtainer obtains second data from outside of the data generating device. The second generator generates third data based on the first data and the second data. The verifier verifies correctness of the third data. When the third data is determined to be incorrect, the operation selector selects at least one of regenerating the first data, re-obtaining the second data, and disabling the data generating device according to a predetermined selection rule.

Abstract: Techniques for performing forward error correction of data to be transmitted over an optical communications channel. The techniques include: receiving data bits; organizing the data bits into an arrangement having a plurality of blocks organized into rows and columns and into a plurality of strands including a first strand of blocks that includes a back portion comprising a first row of the plurality of blocks, and a front portion comprising blocks from at least two different columns in at least two different rows other than the first row of blocks; and encoding at least some of the data bits in the arrangement using a first error correcting code at least in part by generating first parity bits by applying the first error correcting code to first data bits in the front portion of the first strands and second data bits in the back portion of the first strand.

Abstract: A memory device includes a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform coarse decoding and fine decoding. In coarse decoding, the decoder decodes in parallel two or more codewords, which share a common block of bits, to determine error information. Next, the decoder corrects errors in a first codeword based on the error information. Then, it is determined if the shared common block of data bits is corrected. If the shared common data block is updated, then error correction based on the error information is prohibited in codewords sharing the common block of data bits with the first codeword. In fine decoding, a single codeword is decoded at a time for error correction.

Abstract: A method for announcing impending critical events within a distributed storage environment is disclosed. In one embodiment, such a method analyzes, at a storage system, status of various storage system components to predict an impending critical event to occur at the storage system. Predicting the critical event may include calculating an amount of time before occurrence of the impending critical event. The method then communicates, from the storage system to a host system, over an in-band communication channel used to carry I/O traffic between the host system and the storage system, one or more of the impending critical event and the amount of time. This will ideally enable the host system to take mitigating actions before the critical event occurs. A corresponding system and computer program product are also disclosed.

Abstract: A method for data transfer includes transmitting a sequence of data packets, including at least a first packet and a second packet transmitted subsequently to the first packet, from a first computer over a network to a second computer in a single remote direct memory access (RDMA) data transfer transaction. Upon receipt of the second packet at the second computer without previously having received the first packet, a negative acknowledgment (NAK) packet is sent from the second computer over the network to the first computer, indicating that the first packet was not received. In response to the NAK packet, the first packet is retransmitted from the first computer to the second computer without retransmitting the second packet.

Abstract: A transmitting device includes a packet generator that generates k (k: an integer of 2 or more) number of data packets as transmission targets, a coder that generates n (>k) number of coded packets by coding the k number of data packets, a transmission controller that instructs that the coded packets are to be transmitted or the transmission of the coded packets is to be interrupted, and a first transmitter that sequentially transmits the coded packets in response to a transmission instruction from the transmission controller. A receiving device includes a receiver that receives the coded packets, a decoder that decodes the coded packets, and a second transmitter that transmits a transmission interruption request packet to the transmitting device in a case where a first condition in which the coded packets are able to be decoded is satisfied.

Abstract: A data write method for writing data is provided. The data writing method is adapted to a memory controller adopting an ECC scheme and includes: encoding the data to generate a codeword; writing the codeword into the memory array according to a first write condition; and performing a verify operation. The step of performing the verify operation includes: reading the codeword from the memory array; comparing the read codeword with the codeword and obtaining an error bit number of the read codeword; decoding the read codeword to generate a decoded data by an ECC decoder; comparing the decoded data with the data; and comparing the error bit number of the read codeword with a pass threshold if the decoded data is identical to the data. If the error bit number of the read codeword is greater than the pass threshold, the data write method further comprises writing the codeword into the memory array according to a second write condition, where the second write condition is different from the first write condition.

Abstract: Techniques for improving the latency or processing performance of an error correction system are described. In an example, the error correction system implements LDPC decoding and uses an early termination rule to determine whether the LDPC decoding should be terminated prior to reaching a maximum number of iterations. The early termination rule involves various parameters that relate to the syndrome of the decoded LDPC codeword at each iteration. These parameters include the number of the current decoding iteration and the weight of the syndrome at the current iteration. For example, the early termination rule specifies that the LDPC decoding should be terminated prior to the maximum number of iterations either when the weight of the syndrome is zero, or when the current number of iterations reaches an iteration number threshold and the weight of the syndrome equals or exceeds a checksum threshold.

Abstract: A method and apparatus for efficient data decoding is described. Data is encoded by an LDPC encoder using a G matrix. An LDPC decoder uses a modified H matrix to decode encoded blocks of data, the modified H matrix having at least two columns of its circulants swapped with each other. The encoded blocks of data are stored, decoded and reconstructed in an order that considers the circulants in the columns that have been swapped.

Abstract: An encoding apparatus is provided. The encoding includes a low density parity check (LDPC) encoder which performs LDPC encoding on input bits based on a parity-check matrix to generate an LDPC codeword formed of 64,800 bits, in which the parity-check matrix includes an information word sub-matrix and a parity sub-matrix, the information word sub-matrix is formed of a group of a plurality of column blocks each including 360 columns, and the parity-check matrix and the information word sub-matrix are defined by various tables which represent positions of value one (1) present in every 360-th column.

Abstract: System and methods described herein includes a method for iterative decoding. The method includes instantiating an iterative decoding procedure to decode a codeword. At each iteration of the iterative decoding procedure, the method further includes retrieving information relating to a plurality of current decoding variables at a current iteration, determining a first current decoding variable to be skipped for the current iteration based on the information, and processing a second decoding variable without processing the first decoding variable to update related decoding variables from the plurality of current decoding variables.

Abstract: In one implementation, storage system includes embedded storage devices, where each embedded storage device includes a direct-mapped solid state drive (SSD) storage portion and storage system controllers. The storage system controllers may be operatively coupled to the embedded storage devices via a bus. The storage system controllers may receive data to be written to the plurality embedded storage devices, select a plurality of available allocation units from the direct-mapped SSD storage portions of the plurality of embedded storage devices, respectively, and calculate a verification signature corresponding to the data. The storage system controllers may also write the data and the verification signature to a first subset of the plurality of available allocation units, calculate an erasure code corresponding to the data and the verification signature, and write the erasure code to a second subset of allocation units.

Abstract: A low-density parity-check decoder utilizes information about hard errors in a storage medium to identify bit locations to flip log-likelihood ratios while attempting to decode codewords. The decoder iteratively flips and saturates log-likelihood ratios for bits at hard error locations and re-decodes until a valid codeword is produced. The decoder also identifies variable nodes associated with trapping sets for iterative log-likelihood ratio bit flipping.

Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol.

Abstract: A method (500) of generating a cryptographic checksum for a message M(x) is provided. The method comprises pseudo-randomly selecting (502) at least two irreducible polynomials pi(x). Each irreducible polynomial pi(x) is selected based on a first cryptographic key from the set of irreducible polynomials of degree ni over a Galois Field. The method further comprises calculating (503) a generator polynomial p(x) of degree n=formula (I) as a product of the N irreducible polynomials formula (II), and calculating (505) the cryptographic checksum as a first function g of a division of a second function of M(x), ƒ(M(x)), modulo p(x), i.e., g(ƒ(M(x)) mod p(x)). By replacing a standard checksum, such as a Cyclic Redundancy Check (CRC), with a cryptographic checksum, an efficient message authentication is provided. The proposed cryptographic checksum may be used for providing integrity assurance on the message, i.e., for detecting random and intentional message changes, with a known level of security.

Abstract: A compressive sensing capturing device has circuitry, which is configured to obtain compressive sensing image data; and to set a device attribute based on image attribute data, wherein the image attribute data are based on a machine learning algorithm performed in the compressing domain on the obtained compressive sensing image data.

Abstract: Methods, systems, and devices for wireless communication are described that identify an uplink transmission time interval (TTI) length for uplink transmissions, and a downlink TTI length for downlink transmissions, in which the uplink TTI length and the downlink TTI length may be different. The downlink TTI length may be a shortened TTI (sTTI) length, and the uplink TTI length may be longer than the downlink sTTI length. Various parameters for transmissions may be determined based on one or more of the uplink TTI length or the downlink TTI length, such as one or more of a feedback process transmission timing, a timing advance (TA) value, a transport block size (TBS), a number of spatial layers, a number of component carriers (CCs), or a channel quality information (CQI) reporting type may be determined based on one or more of the uplink TTI length or the downlink TTI length.

Abstract: Memory systems may include an encoder suitable for arranging data in rows of data blocks as a plurality of codewords, and permuting the data block rows and constructing row parities on the permuted rows, and a decoder suitable for decoding the codewords, and correcting stuck error patterns when decoding of the codewords fails.

Abstract: The present technology relates to a coding device and a coding method that makes it possible to correspond to a DVB-Like LDPC code and an LDPC code in an ETRI format. A coding device includes: a first LDPC coding unit configured to generate an LDPC code of a predetermined information word by using a first parity check matrix; a first parity interleaving unit configured to interleave a parity bit of the LDPC code; and a second LDPC coding unit configured to generate an LDPC code in an ETRI format by using a second parity check matrix with respect to the LDPC code in which the parity bit is interleaved. The present technology can be applied, for example, to a coding device or the like.

Abstract: A semiconductor device may include a data storage region, a parity storage region and an error correction circuit. The data storage region may be configured to store first data and second data. The parity storage region may be configured to store a parity. The error correction circuit may be configured to correct an error of the first data or an error of the second data and the parity, based on a transmission selection signal.

Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.

Abstract: A communication apparatus includes circuitry configured to perform a process on a frame so that the frame has redundancy corresponding to first information indicating at least one of a first transmission period or a band used for transmission, or uses a modulation scheme corresponding to the first information.