Error Correct And Restore Patents (Class 714/764)
  • Patent number: 10665322
    Abstract: Remapping portions of a memory system having a plurality of non-volatile memory dice. A processing device performs a first error analysis of subslice elements to identify a first group of a predetermined number of subslice elements having highest error rates. The processing device determines which of the subslice elements are user subslice elements and remaps user subslice elements of the first group to spare subslice elements to remove subslice elements having the highest rates from a user space of the memory system. The processing device performs a second error analysis to identify a second group of subslice elements having the highest error rates and identifies user subslice elements of the first group that is/are not in the second group. For an identified user subslice element or elements of the first group not in the second group, the processing device reverses the remapping to reinstate removed subslice element(s) back into the user space.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: May 26, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Samuel E. Bradshaw, Justin Eno
  • Patent number: 10637653
    Abstract: A system for establishing a shared key in a computing-resource-asymmetric field. The system includes: a first communicating unit configured to transmit an interaction request and interaction information of a first user to a second user, and receive interaction information from the second user; a first random number generator configured to generate a random number; a first memory configured to store private key information and public key information of the first user and the interaction information; a first processor configured to complete a computing demand of the first user; a second communicating unit configured to receive the interaction request and the interaction information from the first user, and transmit the interaction information to the first user; a second random number generator configured to generate a random number; a second memory configured to store private key information of the second user and the interaction information; and a second processor.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: April 28, 2020
    Assignee: WUHAN UNIVERSITY
    Inventors: Houzhen Wang, Huanguo Zhang
  • Patent number: 10628258
    Abstract: Methods, apparatuses, and systems for error recovery in memory devices are described. A die-level redundancy scheme may be employed in which parity data associated with particular die may be stored. An example apparatus may include a printed circuit board that has memory devices each disposed on a planar surface of the printed circuit board. Each memory device may include two or more memory die, channels communicatively coupled the two or more memory die, and a memory controller communicatively coupled to the plurality of channels. The memory controller may deterministically maintain a die-level redundancy scheme via data transmission through the plurality of channels. The memory controller may also generate parity data associated with the two or more memory die in response to a data write event.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: April 21, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Reshmi Basu
  • Patent number: 10606696
    Abstract: An aspect includes generating, within a first memory device of a memory system, a plurality of event-based information associated with activity in the memory system. The event-based information is stored in a reserved portion of the first memory device. The event-based information is provided to a memory controller of the memory system corresponding with an access of a memory row across a plurality of memory devices of the memory system associated with the event-based information.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: March 31, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David D. Cadigan, Stephen Glancy, Frank LaPietra, Kevin McIlvain, Jeremy R. Neaton, Richard D. Wheeler
  • Patent number: 10599517
    Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N?1 groups and the plurality of parity bits form a first group different from the N?1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N?1 groups; and providing a second word comprising updated data bits that form a second one of the N?1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N?1 groups.
    Type: Grant
    Filed: April 28, 2018
    Date of Patent: March 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Yin Liu, Yu-Der Chih, Hsueh-Chih Yang, Jonathan Tehan Chen, Kuan-Chun Chen
  • Patent number: 10572341
    Abstract: A semiconductor device includes an error count signal generation circuit and a row error control circuit. The error count signal generation circuit generates an error count signal which is enabled if the number of erroneous data of cells selected to perform an error scrub operation is equal to a predetermined number. The row error control circuit stores information concerning the number of the erroneous data in response to the error count signal if the number of the erroneous data is greater than or equal to the predetermined number or stores information concerning the number of row paths exhibiting the erroneous data in response to the error count signal after more erroneous data than the predetermined number is detected.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: February 25, 2020
    Assignee: SK hynix Inc.
    Inventors: Kihun Kwon, Yong Mi Kim, Jaeil Kim
  • Patent number: 10558522
    Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: February 11, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jun Tao, Niang-Chu Chen, Mark Joseph Dancho, Xiaoheng Chen
  • Patent number: 10552259
    Abstract: The present disclosure, in various embodiments, describes technologies and techniques for use by a data storage controller for decoding codewords during an error correction read recovery process. In illustrative examples, an iterative procedure exploits artificial codewords generated using information obtained from a NAND or other non-volatile memory (NVM) in a previous sense operation. That is, procedures are described that use information obtained in one stage of read recovery to facilitate a subsequent stage to reduce the need to perform additional NAND senses. In one example, information obtained from a sense operation performed for an initial hard bit decode is used in subsequent soft bit decodes. Moreover, iterative decoding procedures are provided that progressively increase correction strength. The procedures may alternate between hard and soft reads while using syndrome weight to determine a failed bit code gradient for identifying the sensing voltage for a next hard sense.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: February 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Adam Noah Jacobvitz, Gulzar Ahmed Kathawala, Kroum Stanimirov Stoev, Bin Wu
  • Patent number: 10552262
    Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by an arbiter, is disclosed to include at least the following steps. After transmitting data to first storage units each connected to one of storage-unit access interfaces in a first batch, the arbiter issues a data write command to each first storage unit, thereby enabling each first storage unit to start a physical data programming. During the physical data programming of each first storage unit, data is transmitted to second storage units each connected to one of the storage-unit access interfaces in a second batch.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: February 4, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Yang-Chih Shen, Sheng-I Hsu
  • Patent number: 10521353
    Abstract: A data storage device includes a nonvolatile memory device and a controller configured to control an operation of the nonvolatile memory device. The controller includes an RAM in which a category table that categories with respect to LBAs are defined and a read voltage table that read voltages with respect to the categories are set are stored and a controller configured to, when a read request and an LBA to be read are received from a host apparatus, determine a category corresponding to the LBA with reference to the category table and perform a read operation on a read-requested memory cell of the nonvolatile memory device by applying a read voltage corresponding to the determined category to the memory cell with reference to the read voltage table.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: December 31, 2019
    Assignee: SK hynix Inc.
    Inventor: Su Jin Lim
  • Patent number: 10516504
    Abstract: A method for determining two bits errors in transmission of 256 bits and the device for realization of this method is provided. By the method and device, the two error bits transferred bits can be determined and corrected by using least bits in operation. Therefore, the amount of data in transmission is increased with a least quantity and thus the transmission quality is not affected.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: December 24, 2019
    Inventor: Chin Pen Chang
  • Patent number: 10505915
    Abstract: A method for execution by a computing device of a dispersed storage network (DSN) begins by receiving a data segment for dispersed storage error encoding. Prior to encoding, the method continues by determining whether to compress the data segment by predicting a first estimated processing cost (EPC) based on EPCs to dispersed storage error decode a compressed set of encoded data slices to recover a compressed data segment and EPCs to decompress the compressed data segment to recover the data segment and by predicting a second EPC based on EPCs to dispersed storage error decode the set of encoded data slices to recover the data segment. When the first EPC compares favorably to the second EPC, the method continues by compressing the data segment to produce the compressed data segment and dispersed storage error encoding the compressed data segment to produce the compressed set of encoded data slices.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: December 10, 2019
    Assignee: PURE STORAGE, INC.
    Inventors: Bart R. Cilfone, Wesley B. Leggette, Jason K. Resch
  • Patent number: 10489077
    Abstract: Systems and methods are disclosed for executing access commands for a data storage device. A data storage device receives first data to be written to a plurality of dies/non-volatile memory arrays. The data storage device transfers a first metapage of the first data to the plurality of dies/non-volatile memory arrays. The data storage device also programs the first metapage to a first metablock of the plurality of dies and programs the first metapage to a second metablock of the plurality of dies/non-volatile memory arrays. The data storage device further transfers a second metapage to the plurality of dies/non-volatile memory arrays. Programming the first metapage to the first metablock may be simultaneous with transferring the second metapage to the plurality of dies/non-volatile memory arrays.
    Type: Grant
    Filed: May 28, 2017
    Date of Patent: November 26, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Sourabh Sankule, Avinash Sharma, Mikhail Palityka
  • Patent number: 10481833
    Abstract: A method for transferring data encoding begins by receiving a data access request to access a data object that is based on a set of encoded data slices (EDSs) that is distributedly stored among a plurality of storage units (SUs) associated with a plurality of storage sites, and continues with a computing device selecting respective numbers of SUs at each of the plurality of storage sites to support the data access request. The method continues with the computing device selecting another computing device that is associated with a storage site of the plurality of storage sites to process the data access request, based on the respective numbers of SUs at each of the plurality of storage sites. The method continues with the computing device transmitting the data access request to the another computing device to for processing.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: November 19, 2019
    Assignee: PURE STORAGE, INC.
    Inventors: Wesley B. Leggette, Ravi V. Khadiwala, Bruno Hennig Cabral, Jason K. Resch
  • Patent number: 10452505
    Abstract: A memory system includes a non-volatile memory unit, a content-addressable memory unit coupled to the non-volatile memory unit, and an error injection logic unit coupled to the non-volatile memory unit and the content addressable memory unit. The non-volatile memory unit is programmed to allow a first error injection onto a first data word using the error injection logic unit. The error injection logic in combination with the content addressable memory unit replaces a bit cell in the memory system. The memory system performs an evaluation of various error detection and correction techniques.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 22, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Michael K. Ciraula
  • Patent number: 10440107
    Abstract: A method for execution within a dispersed storage network (DSN), where the method begins by calculating, utilizing a first integrity check value function, an integrity check value of a first type for each encoded data slice of a set of encoded data slices to produce a corresponding set of integrity check values. The method continues by issuing, via a network, one or more sets of write slice requests 1-n to a set of storage units 1-n within the DSN, where the one or more sets of write slice requests include a plurality of sets of the encoded data slices and a corresponding plurality of sets of the integrity check values. The method continues, when verifying integrity of a received encoded data slice, by a storage unit calculating, utilizing a second integrity check value function, an integrity check value of a second type for the encoded data slice.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: October 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Niall J. McShane, Jason K. Resch, Praveen Viraraghavan, Ilya Volvovski
  • Patent number: 10417087
    Abstract: A system and method for adaptive multiple read of NAND flash memory. A solid state drive may employ adaptive multiple-read to perform enhanced performance error correction using soft decisions without a performance penalty that otherwise might result from performing unnecessary reads. The soft decision error correcting algorithm may employ lookup tables containing log likelihood ratios. The method may include performing one or more read operations to obtain one or more raw data words for a code word, attempting to decode the code words using the one or more raw data words, and performing additional read operations when the decoding attempt fails. This process may be repeated until a decoding attempt succeeds.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: September 17, 2019
    Assignee: NGD Systems, Inc.
    Inventor: Guangming Lu
  • Patent number: 10387242
    Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: August 20, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Jungwon Suh, Alain Artieri, Dexter Tamio Chun, Deepti Vijayalakshmi Sriramagiri
  • Patent number: 10346068
    Abstract: A memory system includes a semiconductor storage device including a plurality of blocks of memory cells, each memory cell storing data in a non-volatile state, a controller configured to issue commands to the semiconductor storage device to perform various operations, including a read operation, a write operation, an erase operation, and a dummy operation. The read operation is an operation in which the semiconductor storage device reads data from a memory cell of a block in the semiconductor storage device, and outputs the read data to the controller, and the dummy operation is an operation in which the semiconductor storage device reads data from a memory cell of a block in the semiconductor storage device and does not output the read data to the controller and does not write the data to any of the memory cells of the blocks in the semiconductor storage device.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 9, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroyuki Ishii, Yuji Nagai, Yukihiro Utsuno, Katsuki Matsudera
  • Patent number: 10348337
    Abstract: A data read method for a memory storage device is provided. The data read method includes: receiving a first read command from a host system for reading first data; calculating an error bit number of the first data; and performing a correction of the first data. If the error bit number is not greater than a predetermined number, finishing the correction of the first data and returning the corrected first data at a pre-defined timing. If the error bit number is greater than a predetermined number, finishing the correction of the first data and returning the corrected first data after the pre-defined timing. In addition, a memory storage device using the data read method is also provided.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: July 9, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Chuen-Der Lien, Ming-Huei Shieh, Chi-Shun Lin
  • Patent number: 10340016
    Abstract: A memory device comprising a main memory and a controller operably connected to the main memory. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Renato C. Padilla, Jung Sheng Hoei, Michael G. Miller, Roland J. Awusie, Sampath K. Ratnam, Kishore Kumar Muchherla, Gary F. Besinga, Ashutosh Malshe, Harish R. Singidi
  • Patent number: 10332017
    Abstract: An information processing method and an electronic device are described where the method includes determining, based on coding combination in a memory cell, an M-th page among N pages in the memory cell; obtaining, based on N?1 inter-page relationships between the M-th page and N?1 pages among the N pages except the M-th page, a first parameter; and adjusting, based on the first parameter, a current probability value of probability of that each bit of L bits corresponding to L pages among the N?1 pages is represented as 0 or 1, as a first probability value, L being a positive integer not greater than N?1.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: June 25, 2019
    Assignee: LENOVO (BEIJING) CO., LTD.
    Inventor: Ying Jiang
  • Patent number: 10331570
    Abstract: A real time memory address translation device is described herein. The address translation device operates to change memory addresses from one address space that is used by system buses to another address space that is used by a main memory of the associated system. The translation device may be placed on the same chip as a corresponding processor core, for example, on a system on chip. The on-chip arrangement of the translation device enables predictable translation times to meet real-time requirement of time-sensitive subsystems.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: June 25, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventor: Flaviu Dorin Turean
  • Patent number: 10319447
    Abstract: A storage device includes a nonvolatile memory device and a controller. A nonvolatile memory device includes a plurality of memory blocks. Each of the plurality of memory blocks is divided into a plurality of zones and is formed on a substrate. Each of the plurality of zones comprises one or more word lines. A controller performs a reliability verification read operation on a first zone of the plurality of zones of a memory block selected from the plurality of memory blocks if a number of read operations performed on the first zone reaches a first threshold value and performs the reliability verification read operation on a second zone of the plurality of zones of the selected memory block if a number of read operations performed on the second zone reaches a second threshold value.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Seop Shim, Jaehong Kim
  • Patent number: 10283202
    Abstract: A memory device and associated techniques for reducing hot electron injection type of disturbs of memory cells. In one approach, after a pre-charge operation, voltages of a first group of adjacent word lines comprising a selected word line (WLn) and one or more drain-side word lines of WLn are increased after voltages of remaining word lines are increased. In another approach, after the pre-charge operation, voltages of the first group of adjacent word lines are increased in steps while voltages of remaining word lines are continuously increased. In another approach, voltages of the first group of adjacent word lines are increased from a negative voltage while voltages of remaining word lines are increased from 0 V. In another aspect, the disturb countermeasures can be implemented according to the position of WLn in a multi-tier stack.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: May 7, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Hong-Yan Chen, Yingda Dong
  • Patent number: 10275309
    Abstract: A multi-layer error correction coding (ECC) parity technique involves dividing a data band into sub-data bands, generating a respective 1st-layer sub-data band parity matrix for each associated sub-data band, and generating a respective (qth>1)-layer parity matrix for sets of associated adjacent sub-data bands. In the context of a data storage system, the parity generation may be performed at the system-side, and communicated and written to one or more associated data storage devices (DSDs) along with the corresponding data, whereby the DSDs may further associate track ECC information to the written data. In response to receiving at the system-side, location-identifying information about data errors that are not correctable by the DSD using track ECC information, the system may determine an amount of the multi-layer parity information needed to recover the corrupt data, and make a data/parity read request accordingly.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: April 30, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventor: Satoshi Yamamoto
  • Patent number: 10256844
    Abstract: A decoding method, a memory storage device, and a memory control circuit unit are provided. The decoding method includes: reading a codeword from a memory module and estimating error level information of the codeword; inputting the codeword and the error level information to an error checking and correcting circuit through a first message channel and a second message channel respectively; determining whether the error level information meets a default condition; if yes, inputting the codeword to a first decoding engine of the error checking and correcting circuit for decoding; otherwise, inputting the codeword to a second decoding engine of the error checking and correcting circuit for decoding, wherein a power consumption of the first decoding engine is lower than that of the second decoding engine, and a decoding success rate of the first decoding engine is lower than that of the second decoding engine. Therefore, an operating flexibility for decoding may be improved.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: April 9, 2019
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventors: Yu-Hua Hsiao, Heng-Lin Yen, Hung-Chi Chang
  • Patent number: 10241704
    Abstract: A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: March 26, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Daniel Tuers, Abhijeet Manohar, Jonathan Hsu
  • Patent number: 10229751
    Abstract: A storage system is provided comprising a controller and a memory. The controller is configured to identify at least two physical blocks of memory that are designated as bad blocks because of at least one defective wordline; identify which wordlines in the at least two physical blocks of memory are defective; and create a logical block of memory from non-defective wordlines in the at least two physical blocks of memory, wherein some portions of the logical block are mapped to one of the at least two physical blocks of memory, and wherein other portions of the logical block are mapped to another one of the at least two physical blocks of memory.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: March 12, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dudy Avraham, Ran Zamir, Idan Alrod, Eran Sharon
  • Patent number: 10176038
    Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Dhivya Jeganathan, Dung Q. Nguyen, Jose A. Paredes, David R. Terry, Brian W. Thompto
  • Patent number: 10176842
    Abstract: The present invention relates to a method for backing up digital cinematographic content, comprising the steps of: generating, from said content, a digital stream encoded in a compressed format, or having said digital stream already encoded in a compressed format; and recording said digital stream encoded in a compressed format onto a photographic film.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: January 8, 2019
    Assignee: ONO FILMS
    Inventor: Antoine Simkine
  • Patent number: 10169123
    Abstract: A distributed storage network (DSN) stores sets of encoded data slices in sets of storage units. A first storage unit assigned to store an encoded data slice included in a set of encoded data slices identifies a storage error associated with that encoded data slice. The first storage unit selects a second storage unit to generate a rebuilt encoded data slice to replace the encoded data slice with the error, and transmits a rebuild request associated with the storage error to the second storage unit. The second storage unit generates the rebuilt encoded data slice in response to the rebuild request, and transmits the rebuilt encoded data slice back to the first storage unit, which stores the rebuilt encoded data slice.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ravi V. Khadiwala, Ethan S. Wozniak, Jason K. Resch
  • Patent number: 10168913
    Abstract: The present invention provides a data storage device including a flash memory and a controller. The flash memory has a plurality of SLC-spare blocks, a plurality of TLC-data blocks and a plurality of TLC-spare blocks. The controller writes a first data sector into a first TLC-spare block, and determines whether a first TLC-data block corresponding to a first logical address has valid data. When the first TLC-data block has valid data, the controller performs a reverse-lookup to obtain a second logical address corresponding to the first TLC-data block, releases the first TLC-data block, a second TLC-data block and a third TLC-data block which are mapped to the second logical address, and maps the first TLC-spare block to the first logical address.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: January 1, 2019
    Assignee: SILICON MOTION, INC.
    Inventors: Chien-Cheng Lin, Jie-Hao Lee
  • Patent number: 10170195
    Abstract: A controller adapts read voltage thresholds of a non-volatile memory. In one embodiment, in response to selection of a block for adaptation of at least one read voltage threshold applicable to a physical page of the block, the controller issues a dummy read operation to the block to ensure the physical page is in a lower bit error rate (BER) state. The controller waits for a calibration read wait period following the dummy configuration read operation and, during the calibration read wait period, monitors for an interfering access to the non-volatile memory that would temporarily place the physical page in a higher BER state. In response to not detecting the interfering access during the calibration read wait period, the controller performs a calibration read operation for the physical page and adapts at least one read voltage threshold for the physical page based on results of the calibration read operation.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Nikolas Ioannou, Nikolaos Papandreou, Roman A. Pletka, Sasa Tomic
  • Patent number: 10162524
    Abstract: A method for execution by a computing device of a dispersed storage network (DSN). The method begins by receiving a data segment of a data object for dispersed storage error encoding. Prior to the dispersed storage error encoding, the method continues by determining whether to compress the data segment by predicting a first estimated processing cost based on estimated processing costs to compress the data segment to produce a compressed data segment and estimated processing costs to dispersed storage error encode the compressed data segment and predicting a second estimated processing cost based on estimated processing costs to dispersed storage error encode the data segment. When the first estimated processing cost compares favorably to the second estimated processing cost, the method continues by compressing the data segment to produce the compressed data segment and dispersed storage error encoding the compressed data segment to produce a set of encoded data slices.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: December 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bart R. Cilfone, Wesley B. Leggette, Jason K. Resch
  • Patent number: 10156995
    Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, and an error correction circuit. The control logic circuit generates control signals by decoding a command. The control logic circuit, in a write mode of the semiconductor memory device, controls the error correction circuit to read a first unit of data from a selected sub-page and to generate a first parity data based on one of the first sub unit of data and the second sub unit of data and a main data to be written into the sub-page while generating syndrome data by performing an error correction code decoding on the first unit of data. The error correction circuit, when a first sub unit of data includes at least one error bit, selectively modifies the first parity data based on a data mask signal associated with the main data.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: December 18, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Hoi-Ju Chung, Ye-Sin Ryu, Seong-Jin Cho
  • Patent number: 10146482
    Abstract: In a network storage device that includes a plurality of data storage drives, error correction and/or recovery of data stored on one of the plurality of data storage drives is performed cooperatively by the drive itself and by a storage host that is configured to manage storage in the plurality of data storage drives. When an error-correcting code (ECC) operation performed by the drive cannot correct corrupted data stored on the drive, the storage host can attempt to correct the corrupted data based on parity and user data stored on the remaining data storage drives. In some embodiments, data correction can be performed iteratively between the drive and the storage host. Furthermore, the storage host can control latency associated with error correction by selecting a particular error correction process.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: December 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Hashimoto, Hironori Uchikawa
  • Patent number: 10148293
    Abstract: Methods for decoding information stored on a memory may include performing a hard read at an initial threshold and determining a first distribution percentage, performing a hard read at a subsequent threshold and determining a second distribution percentage, generating a log-likelihood ratio (LLR) based on the hard reads performed at the initial and subsequent thresholds, and based on the first and second distribution percentages, and soft decoding the information based on the generated LLR.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: December 4, 2018
    Assignee: SK Hynix Inc.
    Inventors: Fan Zhang, David J. Pignatelli, June Lee
  • Patent number: 10146890
    Abstract: A method and apparatus of a device that updates rules for a plurality of entities in a simulation as the simulation is running is described. In an exemplary embodiment, the device receives configuration parameters for the simulation, where the configuration parameters include a plurality of rules that control the interactions of the plurality of entities in the simulation. In addition, the device performs the simulation for a first plurality of iterations. Furthermore, the device analyzes the simulation results to determine if there is an update for the plurality of rules. If there is an update for the plurality of rules, the device creates the rule update for the plurality of rules. The device additionally applies the rule update to the plurality of rules.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: December 4, 2018
    Assignee: Autodesk, Inc.
    Inventors: Carlos Edel Olguin Alvarez, Malte Sebastian Tinnus, Florencio German Mazzoldi
  • Patent number: 10083079
    Abstract: The invention pertains to semiconductor memories, and more particularly to enhancing the reliability of stacked memory devices. Apparatuses and methods are described for implementing RAID-style error correction to increase the reliability of the stacked memory devices.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 25, 2018
    Assignee: Invensas Corporation
    Inventor: William C. Plants
  • Patent number: 10073645
    Abstract: A method begins by detecting a recovery error when decoding a seemingly valid threshold number of existing encoded data slice. The method continues by sending a notice of the recovery error and a known integrity check value for the data segment to a rebuild module. The method continues by the rebuild module retrieving the set of existing encoded data slices and selectively decoding a different combination of a decode threshold number of existing encoded data slices of the set of existing encoded data slices until the data segment is successfully recovered. The method continues by dispersed storage error encoding the successfully recovered data segment to produce a set of new encoded data slices. The method continues by comparing the seemingly valid encoded data slices with corresponding new encoded data slices on an encoded data slice by encoded data slice basis to identify a corrupted encoded data slice.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Niall J. McShane, Jason K. Resch, Ilya Volvovski
  • Patent number: 10043573
    Abstract: Provided are a method and apparatus for endurance friendly programming using lower voltage thresholds. A non-volatile memory has storage cells organized as pages programmed using a first number of threshold voltage levels. The storage cells are organized into storage cell groups to which data is written. Each storage cell group is programmed to store a first number of bits of information. A memory controller selects a second number of bits of information from pages less than the first number of bits of information. The memory controller programs the storage cells of the storage cell group using threshold voltage levels from a second number of threshold voltage levels, wherein the second number of threshold voltage levels is less than the first number of threshold voltage levels and comprises a lowest of the first number of threshold voltage levels.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: August 7, 2018
    Assignee: INTEL CORPORATION
    Inventors: Wei Wu, Yi Zou, Jawad B. Khan, Xin Guo
  • Patent number: 10026488
    Abstract: A non-volatile memory system includes technology for detecting read disturb in open blocks. In one embodiment, the system determines whether a particular block of non-volatile memory cells has been subjected to a minimum number of open block read operations and performs sensing operations for memory cells connected to an open word line of the particular block. The number of errors in the sensed data is determined. If the number of errors is greater than a limit, then the system takes an action to mitigate the read disturb.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: July 17, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Phil Reusswig, Joanna Lai, Deepak Raghu, Grishma Shah, Nian Niles Yang
  • Patent number: 9998540
    Abstract: A method begins by a set of distributed storage and task (DST) execution units receiving a set of partial tasks and data, where a partial task of the set of partial tasks includes a common task and a unique partial sub-task. The method continues with the set of DST execution units executing the common task on the data to produce a set of preliminary partial results. The method continues with a first DST execution unit of the set of DST execution units generating first interim data based on the at least some of the set of preliminary partial results. The method continues with the first DST execution unit executing a first unique partial sub-task on at least one of a first portion of the data and the first interim data to produce a first partial result.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew Baptist, Greg Dhuse, Wesley Leggette, Jason K. Resch
  • Patent number: 9978020
    Abstract: A technique relates to quantum error correction. Code qubits are configured as target qubits, and the code qubits have a first dephasing time and a first anharmonicity. Syndrome qubits are configured as control qubits, and the syndrome qubits have a second dephasing time and a second anharmonicity. The target qubits and the control qubits are configured to form one or more controlled not (CNOT) gates. The first dephasing time is greater than the second dephasing time and the second anharmonicity is greater than the first anharmonicity.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: May 22, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jay M. Gambetta, Easwar Magesan
  • Patent number: 9959166
    Abstract: Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including determining whether the memory includes a defective memory cell, receiving a message to be written to the memory, sub-dividing the message into a plurality of sub-messages, generating a first error correction code for the sub-messages, the first error correction code being a first type, generating a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type, generating a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes, and writing the combined message to the memory, at least a portion of the combined message being written to the defective memory cell.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: May 1, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Robert Mateescu, Zvonimir Z. Bandic, Yongjune Kim, Seung-Hwan Song
  • Patent number: 9948322
    Abstract: A method of merging data frames includes: receiving a first data frame having a plurality of sectors; receiving a second data frame having a plurality of sectors; generating a merged output data frame by merging, using a plurality of data paths including a plurality of multiplexers, sectors of the second data frame with sectors of the first data frame; and performing an error check on at least one check-data frame having sectors corresponding to those in the first data frame or the second data frame, where at least some of the sectors in the check-data frame are transmitted on a subset of the plurality of data paths that transmits sectors of the merged output data frame, and where the error check verifies the merged output data frame.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: April 17, 2018
    Assignees: WESTERN DIGITAL TECHNOLOGIES, INC., SKYERA, LLC
    Inventors: Jack W. Flinsbaugh, Rodney N. Mullendore
  • Patent number: 9946600
    Abstract: A method of detecting power reset of a server includes: after receiving an event signal, determining whether or not to initialize a random access memory (RAM) of a baseboard management controller (BMC) of the server based on the event signal thus received, and initializing the RAM when it is determined to initialize the same; determining whether a protocol error event has occurred according to a flag value of a power reset flag stored in the RAM; determining whether malfunction of a processor unit of the BMC has occurred when it is determined that the protocol error event has not occurred; and determining that a power reset event has occurred when it is determined that malfunction of the processor unit has not occurred.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: April 17, 2018
    Assignee: Mitac Computing Technology Corporation
    Inventor: Ming-I Kuo
  • Patent number: 9946596
    Abstract: In a network storage device that includes a plurality of data storage drives, error correction and/or recovery of data stored on one of the plurality of data storage drives is performed cooperatively by the drive itself and by a storage host that is configured to manage storage in the plurality of data storage drives. When an error-correcting code (ECC) operation performed by the drive cannot correct corrupted data stored on the drive, the storage host can attempt to correct the corrupted data based on parity and user data stored on the remaining data storage drives. In some embodiments, data correction can be performed iteratively between the drive and the storage host. Furthermore, the storage host can control latency associated with error correction by selecting a particular error correction process.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: April 17, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Daisuke Hashimoto, Hironori Uchikawa
  • Patent number: 9934087
    Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: reading a target physical unit based on a first read voltage level; performing a first decoding operation; reading an authentication physical unit based on a first candidate voltage level to obtain first assistance data and reading the authentication physical unit based on a second candidate voltage level to obtain second assistance data if the first decoding operation fails; obtaining a first estimation parameter according to the first assistance data and authentication data and obtaining a second estimation parameter according to the second assistance data and the authentication data; determining a second read voltage level according to the first estimation parameter and the second estimation parameter; and reading the target physical unit again based on the second read voltage level. Accordingly, the decoding efficiency may be improved.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: April 3, 2018
    Assignee: EpoStar Electronics Corp.
    Inventors: Yu-Hua Hsiao, Heng-Lin Yen