Error Correct And Restore Patents (Class 714/764)
  • Patent number: 11231862
    Abstract: Localized lookups for performing access requests to a database may be implemented. Mapping information for storage nodes of a network-based service storing different data for different databases may be obtained by a routing application co-hosted with a client application of the database at a same container host. Access requests from the client application are handled by the routing application and sent to storage nodes identified using the mapping information. An authorization token may be included along with the requests to verify authorization to perform the access request at the storage nodes.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: January 25, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Akshat Vig, Somasundaram Perianayagam, Rashmi Krishnaiah Setty, Stefano Stefani, James Christopher Sorenson, III, Craig Wesley Howard, Akhilesh Mritunjai
  • Patent number: 11228323
    Abstract: Methods and devices are provided for error correction of distributed data in distributed systems using Reed-Solomon codes. In one embodiment, processes are provided for error correction that include receiving a first correction code for data fragments stored in storage nodes, constructing a second correction code responsive to an unavailable storage node of the storage nodes, performing erasure repair of the unavailable storage node, and outputting a corrected data fragment. The first correction code is a Reed-Solomon code represented as a polynomial and the second correction code is represented as a second polynomial with an increased subpacketization size. Processes are configured to account for repair bandwidth and sub-packetization size. Code constructions and repair schemes accommodate different sizes of evaluation points and provide a flexible tradeoff between the subpacketization size repair bandwidth of codes.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: January 18, 2022
    Assignee: The Regents of the University of California
    Inventors: Zhiying Wang, Weiqi Li, Hamid Jafarkhani
  • Patent number: 11221769
    Abstract: A memory system includes a memory device, and a memory controller including a processor and an internal memory. A computer program including a neural network is stored in the memory system. The processor executes the computer program to extract a voltage level from each of a plurality of memory cells connected to one string select line (SSL), in which the memory cells and the SSL are included in a memory block of the memory device, provide the voltage levels as input to the neural network, and perform noise cancellation on the SSL, using the neural network, by changing at least one of the voltage levels from a first voltage level to a second voltage level. The first voltage level is classified into a first cluster of memory cells, and the second voltage level is classified into a second cluster of memory cells different from the first cluster.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: January 11, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Amit Berman, Elisha Halperin, Evgeny Blaichman
  • Patent number: 11221912
    Abstract: A processing device reads data from a memory device in response to a received request and performs a first error control operation on the data based on an initial operating characteristic to correct one or more errors in the data. The processing device determines that the first error control operation based on the initial operating characteristic failed to correct the one or more errors in the data, modifies the initial operating characteristic to generate a modified operating characteristic and performs a second error control operation on the data based on the modified operating characteristic to correct the one or more errors in the data.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: January 11, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Sivagnanam Parthasarathy, Sampath K. Ratnam, Shane Nowell, Renato C. Padilla
  • Patent number: 11216331
    Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: January 4, 2022
    Assignee: SK hynix Inc.
    Inventors: Kang-Sub Kwak, Young-Jun Yoon, Joon-Yong Choi
  • Patent number: 11216339
    Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: January 4, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Hun Seo, Kwang-Il Park, Seung-Jun Bae, Sang-Uhn Cha
  • Patent number: 11210008
    Abstract: A memory system includes a memory device and a controller. The controller performs multiple read operations on a target block, using a first duster of read threshold voltages. The controller generates a second duster of read threshold voltages using the first cluster when a difference between the maximum number of fail bits and the minimum number of fail bits associated with the multiple read operations exceeds a threshold. The controller splits pages in the target block into a first group of pages for the first cluster and a second group of pages for the second cluster. The controller performs additional read operations on the first group of pages using the first cluster and on the second group of pages using the second cluster.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: December 28, 2021
    Assignee: SK hynix Inc.
    Inventors: Fan Zhang, Chenrong Xiong, Xuanxuan Lu
  • Patent number: 11200105
    Abstract: Methods, systems, and apparatuses related to detecting and reporting failures for a memory device are described. When a count of bit-flip errors is above a fail threshold, a memory device can report a failure. Failure reports can indicate a rate at which the memory device is accumulating errors. An offset fail threshold may be applied instead of a default fail threshold, such as a standardized or specified threshold. The offset fail threshold can be a summation of the default fail threshold and an offset determined from an initial error count determined before the memory device has accumulated errors from use.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: December 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Randall J. Rooney, Gregg D. Wolff
  • Patent number: 11194687
    Abstract: Provided is a controller for controlling a memory device. The controller may include a media scanner suitable for performing a media scan operation of reading a predetermined size of data from the memory device in a predetermined cycle, detecting an error of the read data, generating corrected data of the read data, and storing the corrected data in the memory device, a period calculator suitable for calculating a power-off period, and a media scan controller suitable for changing the predetermined cycle according to the power-off period.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: December 7, 2021
    Assignee: SK hynix Inc.
    Inventors: You-Min Ji, Bum-Ho Kim
  • Patent number: 11182088
    Abstract: A method for operating a controller which controls a memory device including a plurality of memory blocks operating in multi-level cell mode or a single level cell mode includes setting some of the plurality of memory blocks operating in the multi-level cell mode, to system memory blocks in response to a power-off request from a host, setting the system memory blocks to the single level cell mode, and controlling the memory device to store system data in the system memory blocks.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: November 23, 2021
    Assignee: SK hynix Inc.
    Inventors: Ki-Sung Kim, Yong-Sang Lee
  • Patent number: 11171095
    Abstract: The present disclosure relates to an active x-ray attack prevention structure for secure integrated circuits. In particular, the present disclosure relates to a structure including a functional circuit, and at least one latchup sensitive diode circuit configured to induce a latchup condition in the functional circuit, placed in proximity of the functional circuit.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: November 9, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Vibhor Jain, Ajay Raman, Sebastian T. Ventrone, John J. Ellis-Monaghan, Siva P. Adusumilli, Yves T. Ngu
  • Patent number: 11150813
    Abstract: A memory system includes a non-volatile memory and a memory controller. During a read operation to read data stored in the non-volatile memory as an N-dimensional error correction code, where N is two or more, the memory controller performs an error correction process on the N-dimensional error correction code iteratively, the error correction process including a first decoding process on a first decoding input to produce a first decoding output and a second decoding process on a second decoding input to produce a second decoding output. During the error correction process, upon determining that errors remaining in the second decoding output after a most recent iteration would not be correctable, the memory controller performs a next iteration using a first decoding input for the next iteration, which is a modified form of the second decoding output of the most recent iteration.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: October 19, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoko Kifune
  • Patent number: 11133071
    Abstract: Memories including a controller configured to cause the memory to read a plurality of memory cells using a read voltage having a particular voltage level, determine a number of memory cells of a first subset of memory cells of the plurality of memory cells having a particular data state in response to the read voltage having the particular voltage level, and in response to determining that the number of memory cells of the first subset of memory cells having the particular data state is less than a particular threshold, adjust the voltage level of the read voltage based on the number of memory cells of the first subset of memory cells having the particular data state, and re-read the plurality of memory cells using the read voltage having the adjusted voltage level.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: September 28, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Vipul Patel
  • Patent number: 11112983
    Abstract: Devices and techniques are disclosed herein to control recovery of a memory device from a reduced power state. A memory controller can include a detection circuit configured to monitor the power supply voltage to an array of memory cells during the reduced power state. Control circuitry an initialization procedure for recovery of the memory device from the reduced power state, based on the state of the detection circuit.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Giuseppe Cariello
  • Patent number: 11115051
    Abstract: Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a hard decision decoding on a codeword, determining which check nodes are satisfied and which check nodes are unsatisfied after the hard decision decoding, scheduling a check node processing order by moving at least one unsatisfied check node to be processed ahead of at least one satisfied check node and performing a soft decision decoding on the codeword according to the check node processing order.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: September 7, 2021
    Assignee: INNOGRIT TECHNOLOGIES CO., LTD.
    Inventors: Yuan-mao Chang, Jie Chen, Chung-Li Wang
  • Patent number: 11113145
    Abstract: A memory device includes a plurality of pages. Each page includes a data region configured to store data, an error correction code (ECC) region configured to store ECC data that is used to detect and correct one or more errors occurring in the data stored in the data region, and a metadata region configured to store a write count of a corresponding page.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: September 7, 2021
    Assignee: SK hynix Inc.
    Inventor: Chang Hyun Park
  • Patent number: 11093145
    Abstract: Protecting in-memory configuration state registers. A request to access an in-memory configuration state register, such as a read or write request, is obtained. The in-memory configuration state register is mapped to memory. Error correction code of the memory is used to protect the access to the in-memory configuration state register.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: August 17, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 11074127
    Abstract: A semiconductor memory device includes an ECC circuit; an error information register; a scrubbing control circuit to count refresh row addresses and output a scrubbing address for a scrubbing operation to be performed on at least one sub-page in a first memory cell row each time N refresh row addresses are counted; and a control logic circuit configured to: control the ECC circuit to sequentially read data corresponding to a first codeword, perform error detection on the first codeword, and provide error information based on the error detection, the error information indicating an error occurrence count in the first codeword; and record the error information in the error information register and selectively determine, based on the error information, whether to write back a corrected first codeword in a memory location in which the data corresponding to the first codeword is stored.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: July 27, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sanguhn Cha, Juseong Hwang
  • Patent number: 11068177
    Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple memory blocks. The memory blocks include multiple table blocks configured to store tables and multiple data blocks configured to store data. The memory controller is configured to receive a predefined command which is a command from a host device to instruct the memory controller to perform initialization of the data storage device. The initialization of the data storage device includes a plurality of processing procedures which include a first portion of processing procedures and a second portion of processing procedures. The memory controller is configured to perform the first portion of processing procedures in response to the predefined command. After the first portion of processing procedures has been finished, the memory controller is configured to notify the host device that the data storage device is ready.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: July 20, 2021
    Assignee: Silicon Motion, Inc.
    Inventor: Kuan-Yu Ke
  • Patent number: 11055173
    Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: July 6, 2021
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Om Ranjan, Riccardo Gemelli, Denis Dutey
  • Patent number: 11057059
    Abstract: Examples described herein relate generally to content aware bit flipping decoders. An example device includes a decoder. The decoder is configured to: process one or more flip thresholds based on statistics of data to be decoded; and perform a bit flipping algorithm on the data using the one or more processed flip thresholds. Other examples relate to methods of processing one or more flip thresholds based on statistics of data to be decoded and performing a bit flipping algorithm on the data using the one or more processed flip thresholds.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: July 6, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Omer Fainzilber, David Avraham, Ran Zamir
  • Patent number: 11049551
    Abstract: A method of processing data in a memory can include accessing an array of memory cells located on a semiconductor memory die to provide a row of data including n bits, latching the n bits in one or more row buffer circuits adjacent to the array of memory cells on the semiconductor memory die to provide latched n bits operatively coupled to a column address selection circuit on the semiconductor memory die to provide a portion of the n latched bits as data output from the semiconductor memory die responsive to a memory read operation, and serially transferring the latched n bits in the row buffer circuit to an arithmetic logic unit (ALU) circuit located adjacent to the row buffer circuit on the semiconductor memory die.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: June 29, 2021
    Assignee: University of Virginia Patent Foundation
    Inventors: Marzieh Lenjani, Patricia Gonzalez, Mircea R. Stan, Kevin Skadron
  • Patent number: 11050440
    Abstract: An encoding method includes: receiving, by an encoder, an information for encoding; generating, by the encoder, a first portion codeword according to a first encoding rule and the information for encoding, wherein the first encoding rule is an encoding rule configured to generate LDPC code; generating, by the encoder, a second portion codeword according to a second encoding rule different from the first encoding rule and a double check region of the first portion codeword; and concatenating, by the encoder, the first portion codeword and the second portion codeword to generate a codeword. A plurality of trapping sets corresponding to the first encoding rule include at least one error bit within the double check region.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: June 29, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Huai Shih, Yu-Ming Huang, Hsiang-Pang Li, Hsi-Chia Chang
  • Patent number: 11023317
    Abstract: An apparatus includes an error correction component coupled to read recovery control circuitry. The error correction component can be configured to perform one or more initial error correction operations on codewords contained within a managed unit received thereto. The read recovery control circuitry can be configured to receive the error corrected codewords from the error correction component and determine whether codewords among the error corrected codewords contain an uncorrectable error. The read recovery control circuitry can be further configured to determine that a redundant array of independent disks (RAID) codeword included in the plurality of error corrected codewords contains the uncorrectable error, request that codewords among the error corrected codewords that contain the uncorrectable error are rewritten in response to the determination, and cause the plurality of error corrected codewords to be transferred to a host coupleable to the read recovery control circuitry.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: June 1, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Richard D. Wiita, Edward C. McGlaughlin, Gary J. Lucas
  • Patent number: 11010246
    Abstract: A method includes registering, by a first computing device, with a distributed storage network (DSN) to indicate that a first storage site is connected via a common local area network with the first computing device and is the primary storage site for the first computing device. The method continues with the first computing device to store a write threshold number of encoded data slices (EDSs) to the first storage site, obtaining a first writing pattern for writing the write threshold number of EDSs to the first plurality of storage units, and transmitting at least a portion of a remaining number of EDSs to one or more storage units at a second storage site, where the remaining number of EDSs are EDSs not included in the write threshold number of EDSs and the second storage site and the first storage site are each one of a sharing group of storage sites.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: May 18, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas Dubucq, Daniel J. Scholl
  • Patent number: 10998078
    Abstract: Provided herein may be a memory system and a method of operating the memory system. The memory system may include: a semiconductor memory device including a plurality of memory cells to be programmed to an erase state and a plurality of program state; and a controller configured to control the semiconductor memory device to perform a program operation or a read operation in response to a request of a host. The controller may control the semiconductor memory device such that when, after a first program operation of the program operation has been performed, a number of program fail bits of the plurality of memory cells is greater than a maximum allowed number of ECC bits, a second program operation is performed on selected memory cells of the plurality of memory cells.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventors: Jae Hyuk Bang, Dong Uk Lee
  • Patent number: 10983821
    Abstract: An apparatus and method are described for implementing a hybrid layer of address mapping for an IOMMU implementation.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Xiao Zheng, Yao Zu Dong, Kun Tian
  • Patent number: 10977119
    Abstract: Disclosed are techniques for managing parity information for data stored on a storage device. A method can be implemented at a computing device communicably coupled to the storage device, and include (1) receiving a request to write data into a data band of the storage device, (2) writing the data into stripes of the data band, comprising, for each stripe of the data band: (i) calculating first parity information for the data written into the stripe, (ii) writing the first parity information into a volatile memory, and (iii) in response to determining that a threshold number of stripes have been written: converting the first parity information into smaller second parity information, and (3) in response to determining that the data band is read-verified: (i) converting the second parity information into smaller third parity information, and (ii) storing the smaller third parity information into a parity band of the storage device.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: April 13, 2021
    Assignee: Apple Inc.
    Inventors: Eran Roll, Stas Mouler, Matthew J. Byom, Andrew W. Vogan, Muhammad N. Ashraf, Elad Harush, Roman Guy
  • Patent number: 10978171
    Abstract: Aspects of the present disclosure relate to techniques for identifying susceptibility to induced charge leakage. In examples, a susceptibility test sequence comprising a cache line flush instruction is used to repeatedly activate a row of a memory unit. The susceptibility test sequence causes induced charge leakage within rows that are physically adjacent to the activated row, such that a physical adjacency map can be generated. In other examples, a physical adjacency map is used to identify a set of adjacent rows to a target row. A susceptibility test sequence is used to repeatedly activate the set of adjacent rows, after which the content of the target row is analyzed to determine whether the any bits of the target row flipped as a result of induced charge leakage. If flipped bits are not identified, an indication is generated that the memory unit is not susceptible to induced charge leakage.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: April 13, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Stefan Saroiu, Lucian Cojocar, Alastair Wolman
  • Patent number: 10956264
    Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: March 23, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Masamichi Fujiwara, Kazumasa Yamamoto, Naoaki Kokubun, Tatsuro Hitomi, Hironori Uchikawa
  • Patent number: 10956266
    Abstract: A method begins by obtaining, for a set of data access requests to a set of storage units of a dispersed storage network, a storage-revision indicator from each of at least some storage units of the set of storage units, where the set of data access requests is regarding a data access transaction involving a set of encoded data slices. The method continues by generating an anticipated storage-revision indicator for the data access transaction based on a current revision level of the set of encoded data slices and a data access type of the data access transaction. The method continues by comparing the anticipated storage-revision indicator with the storage-revision indicators received from the at least some storage units. When a threshold number of the storage-revision indicators received from the at least some storage units substantially match the anticipated storage-revision indicator, the method continues by executing the data access transaction.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Greg R. Dhuse, Ravi V. Khadiwala
  • Patent number: 10951236
    Abstract: Various methods, computer storage media, and systems for implementing hierarchical data integrity verification, in distributed computing systems, are provided. A data manager operates to perform hierarchical data integrity verification operations on message-digests that are associated based on a linear property of a non-cryptographic function, such that a data integrity of source data is verifiable based on the message-digests combined based on an exclusive-or (XOR) operator. The data manager accesses data fragments that are erasure coded fragments and a parity fragment generated from the data fragments, which correspond to source data. The data manager generates and stores the data-fragment message-digests, data-parity message-digests, and parity-fragment message-digests in corresponding data fragment zones and parity fragment zones.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: March 16, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Daniel Chen, Cheng Huang, Jonathan J. Bruso, Marat Marsovich Galeev
  • Patent number: 10942805
    Abstract: An error correcting circuit receives a codeword including user data and a parity code, and performs an error correction operation on the user data. The circuit includes a first buffer, a decoder, a second buffer and a processor. The first buffer stores the codeword and sequentially outputs pieces of subgroup data obtained by dividing the codeword. The decoder generates pieces of integrity data for each of the pieces of subgroup data received from the first buffer, and performs the error correction operation on the user data using the parity code. The second buffer sequentially stores the pieces of integrity data for each of the pieces of subgroup data. The processor determines whether an error is present in the codeword based on the pieces of integrity data stored in the second buffer when at least one of the pieces of integrity data is updated in the second buffer.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: March 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Jun Hwang, Myung-Kyu Lee, Hong-Rak Son, Geun-Yeong Yu, Ki-Jun Lee
  • Patent number: 10922173
    Abstract: Described are fountain code constructs that solve multiple problems in distributed storage systems by providing systematic encoding, reduced repair locality, reduced encoding/decoding complexity, and enhanced reliability. Embodiments are suitable for the storage of large files and exhibit performance superior to existing codes, and demonstrate reduced implementation complexity and enhanced symbol repair locality.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: February 16, 2021
    Assignee: Queen's University at Kingston
    Inventors: Toritseju Okpotse, Shahram Yousefi
  • Patent number: 10915400
    Abstract: One or more blocks from a pool of storage area blocks of the memory component are allocated to a first set of purposed blocks. First write operations are performed to write first data to first data stripes at user blocks of the memory component. Whether the blocks in the first set of purposed blocks satisfy a condition indicating that the first set of purposed blocks are to be retired is determined. Responsive to the blocks in the first set of purposed blocks satisfying the condition, one or more other blocks from the pool of storage area blocks of the memory component are allocated to a second set of purposed blocks. Second write operations are performed to write second data to second data stripes at the user blocks of the memory component.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Sampath K. Ratnam
  • Patent number: 10901894
    Abstract: A heterogeneous memory system is implemented using a low-latency near memory (NM) and a high-latency far memory (FM). Pages in the memory system include NM blocks stored in the NM and FM blocks stored in the FM. A page is assigned to a region in the memory system based on the proportion of NM blocks in the page. When accessing a block, the block address is used to determine a region of the memory system, and a block offset is used to determine whether the block is stored in NM or FM. The memory system may observe memory accesses to determine the access statistics of the page and the block. Based on a page's hotness and access density, the page may be migrated to a different region. Based on a block's hotness, the block may be migrated between NM and FM allocated to the page.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: January 26, 2021
    Assignee: Oracle International Corporation
    Inventors: Lizy John, Jee Ho Ryoo, Hung-Ming Hsu, Karthik Ganesan
  • Patent number: 10901840
    Abstract: Enhanced error correction for data stored in storage devices are presented herein. An error correction circuit decodes an encoded data segment retrieved from a storage media. This decode uses a selected error correction scheme having an error correction limit. The error correction circuit tracks a number of bit corrections made to the encoded data segment during decode. A detection circuit sends a redundant version of the encoded data segment to the error correction circuit in response to the number of bit corrections satisfying a threshold limit set below the error correction limit to mitigate undetected errors in decoding the encoded data segment. An output circuit can transfer resultant data decoded by the error correction circuit to other systems, such as a host device.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: January 26, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Eran Sharon, Idan Alrod
  • Patent number: 10896092
    Abstract: A memory system is disclosed, including a memory component and a processing device configured to decode one or more codewords saved to a memory region of the memory component, detect that a number of bit errors corresponding to the decoding of the codeword exceeds a correction capability of the processing device, and execute an error recovery routine to reduce the number of detected bit errors to within the correction capability. The error recovery routine can include error recovery operations that are sequentially executed either until the number of bit errors is successfully reduced to within the correction capability or until a set of the error recovery operations has been executed. The error recovery operations can be ordered according to one or more factors, including energy used to execute a respective error recovery operation, a duration of the respective operation, and/or a likelihood of success of the respective operation.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Gerald L. Cadloni, Bruce A. Liikanen, Francis Chew, Larry J. Koudele
  • Patent number: 10884853
    Abstract: An apparatus includes a binary content addressable memory (BCAM) to store a plurality of error protection code (ECC) generated codewords (CWs), the BCAM divided into segments (sub-BCAMs), wherein the sub-BCAMs are to respectively store pre-defined first portions of the CWs, and to store corresponding second portions of a search word. In embodiments, the apparatus further includes logic circuitry, to obtain partial match results between the first portions of the CWs and corresponding second portions of the search word, and identify one or more CWs of the plurality of CWs that match the search word, based at least in part on the partial match results, wherein the match indicates that data included in the one or more CW is the same as the data included in the search word.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Wei Wu, Dinesh Somasekhar, Jon Stephan, Aravinda K. Radhakrishnan, Vivek Kozhikkottu
  • Patent number: 10880767
    Abstract: A contactless communication device includes a near field communication (NFC) module for generating an electromagnetic carrier signal and modulating the carrier signal according to data to be transmitted, and an antenna circuit coupled to and driven by said NFC module with the modulated carrier signal. The device includes an RF front end coupled between said NFC module and said antenna circuit and further includes a protocol detection circuit for detecting a protocol mode in response to an incoming signal received by the device. The protocol detection circuit includes a plurality of filters being adapted to generate an envelope of the incoming signal; a plurality of decoders being adapted to generate an output in response to a respective envelope generated by a corresponding one of the plurality of filters; and a decision unit being adapted to detect a protocol mode based on the output from each of the plurality of decoders.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: December 29, 2020
    Assignee: NXP B.V.
    Inventors: Steve Charpentier, Ulrich Andreas Muehlmann, Stefan Mendel
  • Patent number: 10879937
    Abstract: An HC of a code B is first transformed into an HB. A parity bit of the code B is obtained by performing an operation on the HB and an information bit of the code B. The parity bit is used to perform RS coding on a code A, to obtain a parity bit of the code A. A check code of a GEL code is obtained by performing an operation on the parity bits of the code B and the code A. Finally, a single bit parity check bit is added. The code A is defined in a finite field GF (2l1), the code B is defined in a finite field GF (2l2), and l1 and l2 are positive integers. A success rate of decoding the code A in the first row can be improved using this method.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: December 29, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Aleksei Eduardovich Maevskii, Vladimir Gritsenko, Shiyao Xiao, Hong Chen
  • Patent number: 10872011
    Abstract: A memory subsystem includes a data bus to couple a memory controller to one or more memory devices. The memory controller and one or more memory devices transfer data for memory access operations. The data transfer includes the transfer of data bits and associated check bits over a transfer cycle burst. The memory devices include internal error checking and correction (ECC) separate from the system ECC managed by the memory controller. With a 2N transfer cycle for 2{circumflex over (?)}N data bits for a memory device, the memory devices can provide up to 2N memory locations for N+1 internal check bits, which can leave up to (2N minus (N+1)) extra bits to be used by the system for more robust ECC.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: December 22, 2020
    Assignee: Intel Corporation
    Inventors: Kuljit S. Bains, Bill Nale, Rajat Agarwal
  • Patent number: 10867663
    Abstract: A control method for a memory is provided. External data is received. An error correct code scheme is performed on the external data to generate first parity data. The number of logic values equal to a specific logic value in the external data and the first parity data is calculated to generate a calculation result. First reverse data is generated according to the calculation result and tendency data. The external data and the first parity data are inverted and the inverted external data, the inverted first parity data and the first reverse data are written into a cell array in response to the calculation result and the tendency data matching a predetermined condition. The external data, the first parity data and the first reverse data are written into the cell array in response to the calculation result and the tendency data not matching the predetermined condition.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: December 15, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Wen-Chiao Ho
  • Patent number: 10866858
    Abstract: A storage device includes a nonvolatile memory (NVM) device having a plurality of memory blocks and a control circuit configured to perform a read for copy-back operation in response to a receipt of a corresponding command. The control circuit performs the read for copy-back operation by reading page data from a source memory block of the plurality, generating a syndrome from the read page data, outputting the syndrome, receiving error location data in response to outputting the syndrome, correcting the read page data using the received error location data, and writing the corrected read page data to a target memory block among the plurality.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: December 15, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Amit Berman
  • Patent number: 10867690
    Abstract: A memory module includes a first channel of first data memories and a first error correction code (ECC) memory, and a second channel of second data memories and a second ECC memory. Each first data memory transmits a corresponding first data set of first data sets with a memory controller. Each first data set corresponds to a burst length. Each second data memory transmits a corresponding second data set of the second data sets with the memory controller. Each second data set corresponds to the burst length. The first ECC memory stores first sub parity data for detecting at least one error in all of the first data sets stored in the first data memories. The second ECC memory stores second sub parity data for detecting at least one error in all of the second data sets stored in the second data memories.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: December 15, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Joong Kim, Duk-Sung Kim, Yoo-Jung Lee, Jang-Seok Choi
  • Patent number: 10861576
    Abstract: A nonvolatile memory device includes a memory cell array; a peripheral circuit configured to perform an operation corresponding to a command provided from an external device, for the memory cell array; a fail occurrence register configured to store fail occurrence information for intentionally causing an operation fail to occur; and a control logic configured to store the fail occurrence information in the fail occurrence register based on a fail occurrence command received from the external device, control the peripheral circuit to perform a test operation corresponding to a test operation command received from the external device, for the memory cell array, and control the peripheral circuit to cause an intentional fail to occur in the test operation, based on the fail occurrence information.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventor: Jee Yul Kim
  • Patent number: 10855769
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device detects memory error(s) associated with a plurality of sets of memory devices of sets of storage unit(s) (SU(s)) within the DSN that distributedly store a set of encoded data slices (EDSs). The computing device facilitates detection of EDS error(s) associated with the memory error(s). For a set of memory devices, the computing device establishes a corresponding memory replacement priority level and facilitates replacement of corresponding memory device(s) associated with the EDS error(s) based on the corresponding memory replacement priority level.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: December 1, 2020
    Assignee: PURE STORAGE, INC.
    Inventor: Thomas D. Cocagne
  • Patent number: 10855316
    Abstract: Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include generating a codeword based on a number of low density parity check (LDPC) codewords failing a LDPC decoding operation and performing a BCH decoding operation on the codeword.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Yingquan Wu
  • Patent number: 10846171
    Abstract: An error correction code (ECC) decoder of a semiconductor memory device is provided. The ECC decoder includes an ECC checker, a syndrome generator, and an error detection/correction circuit. The ECC checker generates characteristic information representing first error information associated with message bits in an input codeword that is read from a target page in a memory cell array. The syndrome generator outputs a syndrome vector representing second error information associated with the input codeword by performing an operation on the message bits and parity bits in the input codeword based on a parity check matrix. The an error detection/correction circuit generates a transmission codeword by selectively correcting an error bit in the input codeword based on the characteristic information and the syndrome vector, generates a flag signal indicating whether the transmission codeword includes an error bit, and outputs a transmission message based on the transmission codeword.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Hye Cho, Ki-Jun Lee, Myung-Kyu Lee, Jun Jin Kong
  • Patent number: 10831598
    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive metadata from an application, wherein the meta data indicates one or more processing operations which can accommodate a predetermined level of bit errors in read operations from memory, determine, from the metadata, pixel data for which error correction code bypass is acceptable, and generate one or more error correction code bypass hints for subsequent cache access to the pixel data for which error correction code bypass is acceptable, and transmit the one or more error correction code bypass hints to a graphics processing pipeline. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: November 10, 2020
    Assignee: INTEL CORPORATION
    Inventors: Altug Koker, Abhishek R. Appu, Kiran C. Veernapu, Joydeep Ray