Abstract: A memory system includes a memory; and a memory controller which includes a spare buffer suitable for storing an error location in the memory and data at the location, and commands the memory to perform a spare read operation when a read operation needs to be performed in a region of the memory including the error location.

Abstract: Disclosed is a storage device which includes a nonvolatile memory device, and a memory controller that performs a read operation on the nonvolatile memory device and performs an error correction operation on data read in the read operation. In the error correction operation, the memory controller estimates an error rate of the read data, and determines whether to perform a read retry operation based on the estimated error rate.

Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

Abstract: Methods and systems for a storage environment are provided. One method includes copying a data unit from a first temporary storage location corresponding to each zoned solid-state drive (ZNS SSD) of a first ZNS SSD set of a storage system to a first XOR module, while determining a first partial horizontal parity using the data unit stored in the first temporary storage location; and determining a vertical parity for each ZNS SSD of the first ZNS SSD set using the data unit provided to the first XOR module in a current cycle and vertical parity determined from a previous cycle.

Abstract: A fault indication from a fault source is to be provided to a demultiplexer which is configured to output the fault indication. The demultiplexer is configurable to output the fault indication to an OR gate of a plurality of OR gates coupled to a respective fault channel of a plurality of fault channels based on an application which uses the fault source as a resource. A reaction to the fault indication is performed based on the fault channel which received the fault indication.

Abstract: A memory controller having an error checking and correction (ECC) circuitry can detect an error in data being read from memory and correct that error with a retry flow without needing to send another read to the memory for the data. The read data is stored in a read data buffer (RDB) at the memory controller when the read data is received from memory. The memory controller has an error detection path from the RDB to the host and an error correction path. Read data that has no errors can be sent directly to the host. Instead of flushing the RDB in response to the error detection, the memory controller executes a retry flow, where the RDB provides the read data to the error correction path for error correction.

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of mixing input data delayed versions of at least a portion of the respective processing results with coefficient data specific to a processing mode selection. For example, a computing system with processing units may mix the input data delayed versions of respective outputs of various layers of multiplication/accumulation processing units (MAC units) for a transmission in a radio frequency (RF) wireless domain with the coefficient data to generate output data that is representative of the transmission being processed according to a wireless processing mode selection. In another example, such mixing input data with delayed versions of processing results may be to receive and process noisy wireless input data. Examples of systems and methods described herein may facilitate the processing of data for 5G wireless communications in a power-efficient and time-efficient manner.

Abstract: An integrated circuit includes a first set of inverters configured to receive a first set of check bits, and to generate a second set of check bits, a first memory cell array including a first portion of memory cells configured to store a first set of data, and a second portion of memory cells configured to store the second set of check bits, a second set of inverters to receive a third set of check bits, and to generate a fourth set of check bits, and an error correction code decoder configured to detect or correct an error in a second set of data or the fourth set of check bits thereby generating a set of output data and a been-attacked signal. The second set of data corresponds to the first set of data. The been-attacked signal indicates a reset attack by a user.

Abstract: An on-die controller can provide an error correction capability for data stored in an array of memory cells located on the same die as the on-die controller. The error correction capability provided by the on-die controller eliminates a need to transfer error correction code (ECC) data to an external controller that may have provided the error correction capability in lieu of the on-die controller, which can provide more channel bandwidth for other types of non-user data for further strengthening data reliability, security, integrity of the memory system.

Abstract: Disclosed herein are operation methods of a memory controller which controls a memory device. The method includes storing write data in a first area of the memory device, extracting first error position information indicating a position of at least one error included in data stored in the first area, storing the first error position information in a second area of the memory device, reading read data from the first area of the memory device, reading the first error position information from the second area of the memory device, refining the read data based on the first error position information to generate refined data, performing soft decision decoding based on the refined data to generate corrected data, and outputting the corrected data.

Abstract: An accelerator includes a processor and a hybrid memory system. The hybrid memory system includes a resistance-based non-volatile memory, a DRAM used as a cache of the resistance-based non-volatile memory, a non-volatile memory controller connected to the resistance-based non-volatile memory and configured to control the DRAM and the resistance-based non-volatile memory, a memory controller configured to process a memory request from the processor and control the DRAM, and a memory channel configured to connect the DRAM, the non-volatile memory controller, and the memory controller.

Abstract: Methods and systems for a storage environment are provided. One method includes copying a data unit from a first temporary storage location corresponding to each zoned solid-state drive (ZNS SSD) of a first ZNS SSD set of a storage system to a first XOR module, while determining a first partial horizontal parity using the data unit stored in the first temporary storage location; and determining a vertical parity for each ZNS SSD of the first ZNS SSD set using the data unit provided to the first XOR module in a current cycle and vertical parity determined from a previous cycle.

Abstract: A transceiver configured to communicate a burst of data bits and meta-data bits for the data bits includes data channels, auxiliary data channels, and at least one error correction channel. The transceiver includes an encoder that applies 11b7s encoding to a first number of the data bits to generate first PAM-3 symbols on some or all of the communication channels, and that applies 3b2s encoding to a second number of the data bits to generate second PAM-3 symbols on at least some of the communication channels.

Abstract: A data recovery method for a flash memory includes: reading data from the flash memory by using preset read voltage; calculating a check node error rate corresponding to the data; calculating a read voltage adjustment step size according to the check node error rate; adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, and repeating the operation of calculating a check node error rate corresponding to the data to operation of adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, until the check node error rate is minimum; and selecting a read voltage corresponding to the minimum check node error rate to read data from the flash memory, so as to perform data recovery.

Abstract: Aspects can include selecting memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second plurality of pages including corresponding second pluralities of bits, obtaining, based on the second pluralities of bits, extrinsic page information for a proposed error solution including a third plurality of bits indicating a reliability of respective bits of the first plurality of bits, and rejecting, in response to a determination that the proposed error solution indicates a modification to a reliable bit among the first plurality of bits, the proposed error solution to eliminate a false correction of the first plurality of bits.

Abstract: A processing-in-memory (PIM) device includes a data register configured to store reference value data, and a multiplication/accumulation (MAC) operator configured to perform a comparison operation, a multiplication operation, and an addition operation on first data and second data, based on the reference value data to generate MAC operation result data when a MAC operation is performed.

Abstract: A RAM chip includes host dies and parity dies. A memory controller receives system data to be stored on the RAM chip that is in excess of the storage capacity of the host dies. The memory controller encodes the system data in the parity symbols of the parity dies. The system data is retrieved by decoding the parity symbols and identifying the system data from the decoded information.

Abstract: A method and apparatus for predicting and managing a fault in memory includes detecting an error in data. The error is compared to one or more stored errors in a filter, and based upon the comparison, the error is predicted as a transient error or a permanent error for further action.

Abstract: A semiconductor device provides logic operations utilizing low-power memory blocks (“LMBs”) for power conservation. An LMB, in one embodiment, includes a first nonvolatile memory (“NVM”), a second NVM cell, and an LMB output terminal. The first NVM cell contains an NVM transistor able to store one (1) bit of first value persistently. The second NVM cell is configured to persistently store one (1) bit of second value which is opposite logic value of the first value. The LMB output terminal, coupled to a drain terminal of first NVM cell and a source terminal of second NVM cell, is operable to provide an output value in accordance with the first value.

Abstract: A semiconductor system includes a controller configured to output parity information that includes an expected value at which an error correction code (ECC) encoding operation has been performed on an address in a test mode of a semiconductor device and configured to receive failure information. The semiconductor system also includes the semiconductor device configured to store an internal parity generated by performing the ECC encoding operation on the address that is input in a normal mode of the semiconductor device and configured to output the failure information generated by comparing the parity information and an output parity generated from the internal parity that is stored in the semiconductor device in the test mode.

Abstract: A soft post package repair (sPPR) request is detected. Data stored in a target row of a memory array associated with the sPPR request is written to a buffer. Execution of non-maintenance requests on the target row is suspended. Responsive to suspension of execution of non-maintenance requests on the target row, the sPPR request is executed on the target row. Subsequent to completion of the sPPR request, execution of non-maintenance requests on the target row is resumed and the data stored in the buffer is written to the repaired target row.

Abstract: Methods, systems, and devices for internal error correction for memory devices are described. A memory device may perform a read operation at a memory array having a data partition and an error check partition and may obtain a first set of bits from the data partition and a second set of bits from the error check partition. The memory device may determine a first error detection result based on a value of a determined syndrome. The memory device may obtain a parity bit from the first set of bits and determine a second error detection result based on a comparison of the parity bit with a second function of the subset of the first set of bits. The memory device may transmit the first set of bits to a host device based at least in part on the first and second error detection results.

Abstract: Separate inter-die connectors for data and error correction information and related apparatuses, methods, and computing systems are disclosed. An apparatus including a master die, a target die, inter-die data connectors, and inter-die error correction connectors. The target die includes data storage elements. The inter-die data connectors electrically couple the master die to the target die. The inter-die data connectors are configured to conduct write data bits from the master die to the target die. The write data bits are written to the data storage elements. The inter-die error correction connectors electrically couple the master die to the target die. The inter-die error correction connectors are configured to conduct error correction information corresponding to the write data bits from the master die to the target die. The target die includes error correction circuitry configured to generate new error correction information responsive to the write data bits received from the master die.

Abstract: A method describes that a lost first block in a first stripe is directly reconstructed based on a first result obtained from a target quantity of storage devices, so that there is no need to read an unlost block in the first stripe. The first block may be reconstructed provided that the target quantity of first results are obtained. An amount of data of the first result is less than that of the unlost block in the first stripe. Therefore, a data transmission process occupies less network bandwidth, and this improves block reconstruction performance.

Abstract: Data bits are encoded in one or both of an eleven bit seven pulse amplitude modulated three-level (PAM-3) symbol (11b7s) format and a three bit two symbol (3b2s) format on a plurality of data channels and on an error correction channel. One or more of a cyclic redundancy check (CRC) value, a poison value, and a severity value are encoded as 11b7s and/or 3b2s PAM-3 symbols on the error correction channel.

Abstract: Error correcting memory systems and methods of operating the memory systems are disclosed. In some embodiments, a memory system includes: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory. The data scrubbing circuit may be configured to, in response to receiving a scrub data command, correct an error in the data memory. A code word length used to correct the error may be longer than a word length used during normal access of the data memory. In some embodiments, a memory system includes a first memory circuit associated with a first bit error rate and a second memory circuit associated with a second bit error rate. In some embodiments, a memory system includes an error correctable multi-level cell (MLC) array.

Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.

Abstract: A memory system may include a nonvolatile memory device comprising a first area and a second area having a higher data I/O operation speed than the first area, and a controller suitable for performing a first read operation on hot data having a hot property, among data stored in the first area. The controller may control the nonvolatile memory device to copy the hot data into the second area during the first read operation, and access the hot data copied in the second area, when a second read operation on the hot data is requested after the first read operation.

Abstract: Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.

Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Abstract: A method includes determining an encoded data slice of a first subset of encoded data slices associated with a set of encoded data slices requires rebuilding, where the first subset of encoded data slices is stored in a set of storage units and includes at least a decode threshold number of encoded data slices. The method further includes identifying a second encoded data slice of a second subset of encoded data slices of the set of encoded data slices, where the second subset of encoded data slices is not currently stored in the set of storage units. The method further includes generating the second encoded data slice from the first subset of encoded data slices and sending the second encoded data slice to the set of storage units, where when stored, the second encoded data slice no longer included in the second subset of encoded data slices.

Abstract: A method to perform data scrub operations by operating a memory device, the memory device comprising a main memory, an internal Error Correction Code (ECC) engine and a scrub memory. The method comprising: receiving a read command; accessing, based on the receiving the read command, a location in the main memory to read data at the location; error correcting data read during the accessing; and storing at the scrub memory information of the location based at least in part on the correcting the data meeting or exceeding an ECC threshold.

Abstract: Methods, systems, and devices for error log indication via error control information are described. For instance, a memory device may transmit, to a host device, a first signal including a set of error control bits indicating that an error log of the memory device includes information for use by the host device. The memory device may receive, from the host device in response to the first signal, a second signal including a request to retrieve the information of the error log. The memory device may transmit, to the host device in response to the second signal, a third signal including the information of the error log.

Abstract: A processing system of a storage network operates by: sending, to at least one storage unit of the storage network, at least one read request corresponding to at least a read threshold number of a set of encoded data slices to be retrieved, wherein the set of encoded data slices correspond to data, wherein the data is coded in accordance with dispersed error coding parameters that include a write threshold number and the read threshold number, wherein the write threshold number is a number of encoded data slices in the set of encoded data slices and wherein the read threshold number is a number of the set of encoded data slices that is required to decode the data; receiving, via the at least one processing circuit and from the at least one storage unit, a first subset of the set of encoded data slices, wherein the first subset is missing at least one missing encoded data slice that was not received from the at least one storage unit in response to the at least one read request and wherein a number of encoded

Abstract: A processing-in-memory (PIM) device includes an ECC logic circuit configured to generate write data and write parity from write input data when a write operation in an operation mode is performed, and generate converted data from read data and read parity when a read operation in an operation mode is performed; and a MAC operator configured to perform a MAC arithmetic operation for the converted data and buffer data to generate MAC operation result data.

Abstract: A memory controller is provided that is configured to control a memory accessed by a device connected to a host processor via a bus. The memory controller is configured to control a memory accessed by a device connected to a host processor via a bus, and includes a first interface circuit configured to communicate with the host processor; a second interface circuit configured to communicate with the memory; an error detection circuit configured to detect an error present in data received from the second interface circuit in response to a first read request received from the first interface circuit; a variable error correction circuit configured to correct the error based on at least one of a reference latency and a reference error correction level included in a first error correction option; and a fixed error correction circuit configured to correct the error in parallel with an operation of the variable error correction circuit.

Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first codeword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

Abstract: Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.

Abstract: Methods, systems, and apparatuses for a memory device (e.g., DRAM) including an error check and scrub (ECS) procedure in conjunction with refresh operations are described. The ECS procedure may include read/modify-write cycles when errors are detected in code words. In some embodiments, the memory device may complete the ECS procedure over multiple refresh commands, namely by performing a read (or read/modify) portion of the ECS procedure while a first refresh command is executed, and by performing a write portion of the ECS procedure while a second refresh command is executed. The ECS procedure described herein may facilitate avoiding signaling conflicts or interferences that may occur between the ECS procedure and other memory operations.

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include an interface to receive read and write requests from an application on a host. Storage, including at least one chip, may store data. An SSD controller may process the read and write requests from the application. A configuration module may configure the SSD. Storage may include a reliability table which may include entries specifying configurations of the SSD and reliabilities for those configurations.

Abstract: A processing-in-memory (PIM) device includes an CRC logic circuit configured to generate first write data, a first write fail check signal, second write data, and a second write fail check signal from first write input data and second write input data when a write operation in an operation mode is performed, and generate first converted data, a first fail flag signal, second converted data, and a second fail flag signal from first read data, a first read fail check signal, second read data, and a second read fail check signal when a read operation in the operation mode is performed; and a MAC operator configured to perform a MAC arithmetic operation for the first converted data and the second converted data, based on the first and second fail flag signals to generate MAC operation result data.

Abstract: Methods, systems, and devices for valid data aware media reliability scanning are described. An apparatus may include a memory array comprising a plurality of blocks and a controller coupled with the memory array. The controller may be configured to select a block of the plurality of blocks for a scan operation to determine a margin of reliability for a first set of data stored in the block. The controller may identify information associated with a status of a validity of sub-blocks of the first set of data in the block. The controller may determine a first subset of the sub-blocks storing valid data of the first set of data and a second subset of sub-blocks that are invalid based on identifying the information. The controller may perform the scan operation on the first subset of sub-blocks and not on the second subset of sub-blocks in the block.

Abstract: Methods, systems, and devices for read performance techniques for time retention are described. A memory system may store data in a block of memory cells and perform a power cycle operation. Based on performing the power cycle operation, the memory system may determine a first voltage offset associated with the block of memory cells by executing a first read command using an auto-read calibration operation. Based on the first voltage offset, and, in some examples, one or more additional voltage offsets, the memory system may calculate a retention time of data stored in the block of memory cells. The memory system may adjust a read voltage based on the retention time and perform one or more additional read commands.

Abstract: A controller including a non-volatile memory interface circuit connected to at least one non-volatile memory device and configured to control the at least one non-volatile memory device; an error correction circuit configured to perform an error correction operation on a codeword received from the non-volatile memory interface circuit according to an error correction decoding level from among a plurality of error correction decoding levels, wherein the non-volatile memory interface circuit is further configured to: receive side information from the at least one non-volatile memory device; predict a distribution of memory cells based on the side information; and select the error correction decoding level from among the plurality of error correction decoding levels according to the predicted distribution.

Abstract: A computer-implemented method for correcting one or more errors in a quantum computing system can include obtaining, by a computing system comprising one or more computing devices, a plurality of weighted detection graphs, each of the plurality of weighted detection graphs being descriptive of a plurality of error detection measurements and having a plurality of weights, each of the weights respectively determined according to an error probability. The method can include generating, by the computing system, a plurality of reweighted detection graphs based at least in part on a correlation between physical errors in the quantum computing system. The method can include correcting, by the computing system, one or more errors in a quantum computing system based at least in part on a global decoding of the plurality of reweighted detection graphs.

Abstract: Methods, devices, and systems for managing data refresh for semiconductor devices are provided. In one aspect, a semiconductor device includes a memory cell array having a plurality of blocks each including multiple pages and one or more integrated circuits coupled to the memory cell array. The one or more integrated circuits are configured to: read specific data from a page of a block in the memory cell array, perform a logic operation on the specific data in the page to obtain a logic operation result, count a number of bits having a specific value among the logic operation result, determine whether the number of bits is within a data refresh criterion for the page, and in response to determining that the number of bits is outside of the data refresh criterion, generate a data refresh warning message for the page in the block.

Abstract: A controller of a solid state drive (SSD) device, in response to determining that the SSD device is to transition to a power saving mode: transfers information from at least some of a volatile memory of an SSD device controller of the SSD device to a host memory of a host computer via a communication interface; and transitions the at least some of the volatile memory to an OFF state to reduce power consumption of the SSD device. In response to determining that the SSD device is to transition from the power saving mode to a normal operating mode, the controller also: transitions the at least some of the volatile memory to an ON state in which the at least some of the volatile memory is configured to retain data; and transfers the information from the host memory to the volatile memory of the SSD device controller via the communication interface.

Abstract: Devices, systems, and methods with proactive data loss notification and handling. A data storage device includes a memory and a controller. The controller includes a processor and controller memory. The controller memory stores a set of instructions that, when executed by the processor, instruct the controller to: detect an uncorrectable error correction code (UECC) during an internal data movement process of the storage device memory, modify a metadata field associated with a logical block address corresponding to the UECC, inform a host device about the UECC, and determine whether data stored in at least one adjacent region to the logical block address is lost.

Abstract: A solution for deteriorated non-volatile memory is shown. When determining that raw data read from the non-volatile memory is undesirable data, the controller updates a deterioration table to record a deteriorated logical address of the raw data that is the undesirable data. In response to a read request that a host issues to read the non-volatile memory for data of the deteriorated logical address, the controller obtains the deteriorated logical address from the deterioration table and informs the host that deterioration has happened at the deteriorated logical address.