Abstract: A computing system includes: a control circuit for determining a user data, generating a base set including a base protection data based on encoding the user data, calculating an extra protection data based on encoding the base set; and a storage circuit for storing the extra protection data (210) corresponding to the base set. The computing system can further include: an storage circuit for providing a received codeword corresponding to a user data and a base protection data, providing an extra protection data corresponding to the received codeword; and a control circuit for calculating a base syndrome from the received codeword, calculating a further syndrome from the extra protection data, and decoding the received codeword to recover the user data, the base protection data, or a combination thereof using the base syndrome and the further syndrome.

Abstract: Exemplary methods and apparatus are provided to reduce read retry latency within solid state devices (SSDs) with non-volatile memories (NVMs). The reduction in read retry latency may be accomplished in some examples by prioritizing read recovery of a regular codeword over an irregular codeword for a cross-die logical page, irrespective of the location in the page with read errors. In an illustrative example, a processor (a) performs a read retry for a second codeword by setting a read voltage level to a first level for a first die, then advancing through a read retry table for the second die until the second codeword is read successfully, and (b) then performs a read retry for the first codeword by setting a read voltage level for the second die to a second level, then advancing through a read retry table for the first die until the first codeword is successfully read.

Abstract: A data storage apparatus that includes a storage device and a processor coupled to the storage device. The processor is configured to receive in a memory, a first logical block entry for a first dump group and a second logical block entry for a second dump group; store in a reverse translation table, the first logical block entry for the first dump group and the second logical block entry for the second dump group; determine a first sequence number associated with the stored first logical block entry and the stored second logical block entry in the reverse translation table, wherein the first sequence number is a snapshot marker that determines a timestamp associated with the first logical block and the second logical block; and persist the first logical block entry for the first dump group in the storage device.

Abstract: A data storage apparatus that includes a storage device and a processor coupled to the storage device. The processor is configured to receive a read request for a first translation table entry associated with a logical block, identify a dump unit associated with the logical block using a hash function, determine a dump group associated with the dump unit, and identify a second translation table entry associated with the dump unit.

Abstract: According to one embodiment, a memory system includes an error mitigation encoder that executes error mitigation coding on write data to be stored in a processing target page of a non-volatile memory, a memory interface that writes the write data which has undergone the error mitigation coding in the processing target page of the non-volatile memory and reads the write data which has undergone the error mitigation coding from the processing target page as read data, an error mitigation decoder that performs error mitigation decoding on the read data read from the processing target page of the non-volatile memory, and an error mitigation coding rate deciding unit that decides an error mitigation coding rate of the error mitigation encoder and the error mitigation decoder on the basis of at least one of information indicating the processing target page and information indicating a device characteristic of the processing target page.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: A system and method are disclosed for performing address fault detection in a flash memory system. In one embodiment, a flash memory system comprises a memory array comprising flash memory cells arranged in rows and columns, a row decoder for receiving a row address as an input, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of flash memory cells in the memory array, an address fault detection array comprising a column of memory cells, wherein each of the plurality of word lines is coupled to a memory cell in the column, and an analog comparator for comparing a current drawn by the column with a reference current and for indicating a fault if the current drawn by the column exceeds the reference current.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for error reducing matrix generation. An apparatus includes a test circuit that performs a test on a set of memory cells. An apparatus includes a masking circuit that determines a masking array based on a test performed on a set of memory cells. An apparatus includes a decoding circuit that decodes encoded data from a set of memory cells based on a masking array.

Abstract: A method begins by a dispersed storage (DS) processing unit of a dispersed storage network (DSN) transmitting a write request to a set of storage units of the DSN. The write request is requesting DS error encoding of a data segment of a data object. The method continues by a first storage unit interpreting the write request to determine a DS error encoding function and a first pillar number of the DS error encoding. The method continues by the first storage unit executing the DS error encoding on at least a first portion of the data segment using at least a first portion of an encoding matrix to produce a first encoded data slice that corresponds to the first pillar number. The method continues by the first storage unit storing the first encoded data slice and sending an acknowledgement of storage to the DS processing unit.

Abstract: Remapping portions of a memory system having a plurality of non-volatile memory dice. A processing device performs a first error analysis of subslice elements to identify a first group of a predetermined number of subslice elements having highest error rates. The processing device determines which of the subslice elements are user subslice elements and remaps user subslice elements of the first group to spare subslice elements to remove subslice elements having the highest rates from a user space of the memory system. The processing device performs a second error analysis to identify a second group of subslice elements having the highest error rates and identifies user subslice elements of the first group that is/are not in the second group. For an identified user subslice element or elements of the first group not in the second group, the processing device reverses the remapping to reinstate removed subslice element(s) back into the user space.

Abstract: A system for establishing a shared key in a computing-resource-asymmetric field. The system includes: a first communicating unit configured to transmit an interaction request and interaction information of a first user to a second user, and receive interaction information from the second user; a first random number generator configured to generate a random number; a first memory configured to store private key information and public key information of the first user and the interaction information; a first processor configured to complete a computing demand of the first user; a second communicating unit configured to receive the interaction request and the interaction information from the first user, and transmit the interaction information to the first user; a second random number generator configured to generate a random number; a second memory configured to store private key information of the second user and the interaction information; and a second processor.

Abstract: Methods, apparatuses, and systems for error recovery in memory devices are described. A die-level redundancy scheme may be employed in which parity data associated with particular die may be stored. An example apparatus may include a printed circuit board that has memory devices each disposed on a planar surface of the printed circuit board. Each memory device may include two or more memory die, channels communicatively coupled the two or more memory die, and a memory controller communicatively coupled to the plurality of channels. The memory controller may deterministically maintain a die-level redundancy scheme via data transmission through the plurality of channels. The memory controller may also generate parity data associated with the two or more memory die in response to a data write event.

Abstract: An aspect includes generating, within a first memory device of a memory system, a plurality of event-based information associated with activity in the memory system. The event-based information is stored in a reserved portion of the first memory device. The event-based information is provided to a memory controller of the memory system corresponding with an access of a memory row across a plurality of memory devices of the memory system associated with the event-based information.

Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N?1 groups and the plurality of parity bits form a first group different from the N?1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N?1 groups; and providing a second word comprising updated data bits that form a second one of the N?1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N?1 groups.

Abstract: A semiconductor device includes an error count signal generation circuit and a row error control circuit. The error count signal generation circuit generates an error count signal which is enabled if the number of erroneous data of cells selected to perform an error scrub operation is equal to a predetermined number. The row error control circuit stores information concerning the number of the erroneous data in response to the error count signal if the number of the erroneous data is greater than or equal to the predetermined number or stores information concerning the number of row paths exhibiting the erroneous data in response to the error count signal after more erroneous data than the predetermined number is detected.

Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by an arbiter, is disclosed to include at least the following steps. After transmitting data to first storage units each connected to one of storage-unit access interfaces in a first batch, the arbiter issues a data write command to each first storage unit, thereby enabling each first storage unit to start a physical data programming. During the physical data programming of each first storage unit, data is transmitted to second storage units each connected to one of the storage-unit access interfaces in a second batch.

Abstract: The present disclosure, in various embodiments, describes technologies and techniques for use by a data storage controller for decoding codewords during an error correction read recovery process. In illustrative examples, an iterative procedure exploits artificial codewords generated using information obtained from a NAND or other non-volatile memory (NVM) in a previous sense operation. That is, procedures are described that use information obtained in one stage of read recovery to facilitate a subsequent stage to reduce the need to perform additional NAND senses. In one example, information obtained from a sense operation performed for an initial hard bit decode is used in subsequent soft bit decodes. Moreover, iterative decoding procedures are provided that progressively increase correction strength. The procedures may alternate between hard and soft reads while using syndrome weight to determine a failed bit code gradient for identifying the sensing voltage for a next hard sense.

Abstract: A data storage device includes a nonvolatile memory device and a controller configured to control an operation of the nonvolatile memory device. The controller includes an RAM in which a category table that categories with respect to LBAs are defined and a read voltage table that read voltages with respect to the categories are set are stored and a controller configured to, when a read request and an LBA to be read are received from a host apparatus, determine a category corresponding to the LBA with reference to the category table and perform a read operation on a read-requested memory cell of the nonvolatile memory device by applying a read voltage corresponding to the determined category to the memory cell with reference to the read voltage table.

Abstract: A method for determining two bits errors in transmission of 256 bits and the device for realization of this method is provided. By the method and device, the two error bits transferred bits can be determined and corrected by using least bits in operation. Therefore, the amount of data in transmission is increased with a least quantity and thus the transmission quality is not affected.

Abstract: A method for execution by a computing device of a dispersed storage network (DSN) begins by receiving a data segment for dispersed storage error encoding. Prior to encoding, the method continues by determining whether to compress the data segment by predicting a first estimated processing cost (EPC) based on EPCs to dispersed storage error decode a compressed set of encoded data slices to recover a compressed data segment and EPCs to decompress the compressed data segment to recover the data segment and by predicting a second EPC based on EPCs to dispersed storage error decode the set of encoded data slices to recover the data segment. When the first EPC compares favorably to the second EPC, the method continues by compressing the data segment to produce the compressed data segment and dispersed storage error encoding the compressed data segment to produce the compressed set of encoded data slices.

Abstract: Systems and methods are disclosed for executing access commands for a data storage device. A data storage device receives first data to be written to a plurality of dies/non-volatile memory arrays. The data storage device transfers a first metapage of the first data to the plurality of dies/non-volatile memory arrays. The data storage device also programs the first metapage to a first metablock of the plurality of dies and programs the first metapage to a second metablock of the plurality of dies/non-volatile memory arrays. The data storage device further transfers a second metapage to the plurality of dies/non-volatile memory arrays. Programming the first metapage to the first metablock may be simultaneous with transferring the second metapage to the plurality of dies/non-volatile memory arrays.

Abstract: A method for transferring data encoding begins by receiving a data access request to access a data object that is based on a set of encoded data slices (EDSs) that is distributedly stored among a plurality of storage units (SUs) associated with a plurality of storage sites, and continues with a computing device selecting respective numbers of SUs at each of the plurality of storage sites to support the data access request. The method continues with the computing device selecting another computing device that is associated with a storage site of the plurality of storage sites to process the data access request, based on the respective numbers of SUs at each of the plurality of storage sites. The method continues with the computing device transmitting the data access request to the another computing device to for processing.

Abstract: A memory system includes a non-volatile memory unit, a content-addressable memory unit coupled to the non-volatile memory unit, and an error injection logic unit coupled to the non-volatile memory unit and the content addressable memory unit. The non-volatile memory unit is programmed to allow a first error injection onto a first data word using the error injection logic unit. The error injection logic in combination with the content addressable memory unit replaces a bit cell in the memory system. The memory system performs an evaluation of various error detection and correction techniques.

Abstract: A method for execution within a dispersed storage network (DSN), where the method begins by calculating, utilizing a first integrity check value function, an integrity check value of a first type for each encoded data slice of a set of encoded data slices to produce a corresponding set of integrity check values. The method continues by issuing, via a network, one or more sets of write slice requests 1-n to a set of storage units 1-n within the DSN, where the one or more sets of write slice requests include a plurality of sets of the encoded data slices and a corresponding plurality of sets of the integrity check values. The method continues, when verifying integrity of a received encoded data slice, by a storage unit calculating, utilizing a second integrity check value function, an integrity check value of a second type for the encoded data slice.

Abstract: A system and method for adaptive multiple read of NAND flash memory. A solid state drive may employ adaptive multiple-read to perform enhanced performance error correction using soft decisions without a performance penalty that otherwise might result from performing unnecessary reads. The soft decision error correcting algorithm may employ lookup tables containing log likelihood ratios. The method may include performing one or more read operations to obtain one or more raw data words for a code word, attempting to decode the code words using the one or more raw data words, and performing additional read operations when the decoding attempt fails. This process may be repeated until a decoding attempt succeeds.

Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.

Abstract: A data read method for a memory storage device is provided. The data read method includes: receiving a first read command from a host system for reading first data; calculating an error bit number of the first data; and performing a correction of the first data. If the error bit number is not greater than a predetermined number, finishing the correction of the first data and returning the corrected first data at a pre-defined timing. If the error bit number is greater than a predetermined number, finishing the correction of the first data and returning the corrected first data after the pre-defined timing. In addition, a memory storage device using the data read method is also provided.

Abstract: A memory system includes a semiconductor storage device including a plurality of blocks of memory cells, each memory cell storing data in a non-volatile state, a controller configured to issue commands to the semiconductor storage device to perform various operations, including a read operation, a write operation, an erase operation, and a dummy operation. The read operation is an operation in which the semiconductor storage device reads data from a memory cell of a block in the semiconductor storage device, and outputs the read data to the controller, and the dummy operation is an operation in which the semiconductor storage device reads data from a memory cell of a block in the semiconductor storage device and does not output the read data to the controller and does not write the data to any of the memory cells of the blocks in the semiconductor storage device.

Abstract: A memory device comprising a main memory and a controller operably connected to the main memory. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.

Abstract: A real time memory address translation device is described herein. The address translation device operates to change memory addresses from one address space that is used by system buses to another address space that is used by a main memory of the associated system. The translation device may be placed on the same chip as a corresponding processor core, for example, on a system on chip. The on-chip arrangement of the translation device enables predictable translation times to meet real-time requirement of time-sensitive subsystems.

Abstract: An information processing method and an electronic device are described where the method includes determining, based on coding combination in a memory cell, an M-th page among N pages in the memory cell; obtaining, based on N?1 inter-page relationships between the M-th page and N?1 pages among the N pages except the M-th page, a first parameter; and adjusting, based on the first parameter, a current probability value of probability of that each bit of L bits corresponding to L pages among the N?1 pages is represented as 0 or 1, as a first probability value, L being a positive integer not greater than N?1.

Abstract: A storage device includes a nonvolatile memory device and a controller. A nonvolatile memory device includes a plurality of memory blocks. Each of the plurality of memory blocks is divided into a plurality of zones and is formed on a substrate. Each of the plurality of zones comprises one or more word lines. A controller performs a reliability verification read operation on a first zone of the plurality of zones of a memory block selected from the plurality of memory blocks if a number of read operations performed on the first zone reaches a first threshold value and performs the reliability verification read operation on a second zone of the plurality of zones of the selected memory block if a number of read operations performed on the second zone reaches a second threshold value.

Abstract: A memory device and associated techniques for reducing hot electron injection type of disturbs of memory cells. In one approach, after a pre-charge operation, voltages of a first group of adjacent word lines comprising a selected word line (WLn) and one or more drain-side word lines of WLn are increased after voltages of remaining word lines are increased. In another approach, after the pre-charge operation, voltages of the first group of adjacent word lines are increased in steps while voltages of remaining word lines are continuously increased. In another approach, voltages of the first group of adjacent word lines are increased from a negative voltage while voltages of remaining word lines are increased from 0 V. In another aspect, the disturb countermeasures can be implemented according to the position of WLn in a multi-tier stack.

Abstract: A multi-layer error correction coding (ECC) parity technique involves dividing a data band into sub-data bands, generating a respective 1st-layer sub-data band parity matrix for each associated sub-data band, and generating a respective (qth>1)-layer parity matrix for sets of associated adjacent sub-data bands. In the context of a data storage system, the parity generation may be performed at the system-side, and communicated and written to one or more associated data storage devices (DSDs) along with the corresponding data, whereby the DSDs may further associate track ECC information to the written data. In response to receiving at the system-side, location-identifying information about data errors that are not correctable by the DSD using track ECC information, the system may determine an amount of the multi-layer parity information needed to recover the corrupt data, and make a data/parity read request accordingly.

Abstract: A decoding method, a memory storage device, and a memory control circuit unit are provided. The decoding method includes: reading a codeword from a memory module and estimating error level information of the codeword; inputting the codeword and the error level information to an error checking and correcting circuit through a first message channel and a second message channel respectively; determining whether the error level information meets a default condition; if yes, inputting the codeword to a first decoding engine of the error checking and correcting circuit for decoding; otherwise, inputting the codeword to a second decoding engine of the error checking and correcting circuit for decoding, wherein a power consumption of the first decoding engine is lower than that of the second decoding engine, and a decoding success rate of the first decoding engine is lower than that of the second decoding engine. Therefore, an operating flexibility for decoding may be improved.

Abstract: A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.

Abstract: A storage system is provided comprising a controller and a memory. The controller is configured to identify at least two physical blocks of memory that are designated as bad blocks because of at least one defective wordline; identify which wordlines in the at least two physical blocks of memory are defective; and create a logical block of memory from non-defective wordlines in the at least two physical blocks of memory, wherein some portions of the logical block are mapped to one of the at least two physical blocks of memory, and wherein other portions of the logical block are mapped to another one of the at least two physical blocks of memory.

Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.

Abstract: The present invention relates to a method for backing up digital cinematographic content, comprising the steps of: generating, from said content, a digital stream encoded in a compressed format, or having said digital stream already encoded in a compressed format; and recording said digital stream encoded in a compressed format onto a photographic film.

Abstract: The present invention provides a data storage device including a flash memory and a controller. The flash memory has a plurality of SLC-spare blocks, a plurality of TLC-data blocks and a plurality of TLC-spare blocks. The controller writes a first data sector into a first TLC-spare block, and determines whether a first TLC-data block corresponding to a first logical address has valid data. When the first TLC-data block has valid data, the controller performs a reverse-lookup to obtain a second logical address corresponding to the first TLC-data block, releases the first TLC-data block, a second TLC-data block and a third TLC-data block which are mapped to the second logical address, and maps the first TLC-spare block to the first logical address.

Abstract: A distributed storage network (DSN) stores sets of encoded data slices in sets of storage units. A first storage unit assigned to store an encoded data slice included in a set of encoded data slices identifies a storage error associated with that encoded data slice. The first storage unit selects a second storage unit to generate a rebuilt encoded data slice to replace the encoded data slice with the error, and transmits a rebuild request associated with the storage error to the second storage unit. The second storage unit generates the rebuilt encoded data slice in response to the rebuild request, and transmits the rebuilt encoded data slice back to the first storage unit, which stores the rebuilt encoded data slice.

Abstract: A controller adapts read voltage thresholds of a non-volatile memory. In one embodiment, in response to selection of a block for adaptation of at least one read voltage threshold applicable to a physical page of the block, the controller issues a dummy read operation to the block to ensure the physical page is in a lower bit error rate (BER) state. The controller waits for a calibration read wait period following the dummy configuration read operation and, during the calibration read wait period, monitors for an interfering access to the non-volatile memory that would temporarily place the physical page in a higher BER state. In response to not detecting the interfering access during the calibration read wait period, the controller performs a calibration read operation for the physical page and adapts at least one read voltage threshold for the physical page based on results of the calibration read operation.

Abstract: A method for execution by a computing device of a dispersed storage network (DSN). The method begins by receiving a data segment of a data object for dispersed storage error encoding. Prior to the dispersed storage error encoding, the method continues by determining whether to compress the data segment by predicting a first estimated processing cost based on estimated processing costs to compress the data segment to produce a compressed data segment and estimated processing costs to dispersed storage error encode the compressed data segment and predicting a second estimated processing cost based on estimated processing costs to dispersed storage error encode the data segment. When the first estimated processing cost compares favorably to the second estimated processing cost, the method continues by compressing the data segment to produce the compressed data segment and dispersed storage error encoding the compressed data segment to produce a set of encoded data slices.

Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, and an error correction circuit. The control logic circuit generates control signals by decoding a command. The control logic circuit, in a write mode of the semiconductor memory device, controls the error correction circuit to read a first unit of data from a selected sub-page and to generate a first parity data based on one of the first sub unit of data and the second sub unit of data and a main data to be written into the sub-page while generating syndrome data by performing an error correction code decoding on the first unit of data. The error correction circuit, when a first sub unit of data includes at least one error bit, selectively modifies the first parity data based on a data mask signal associated with the main data.

Abstract: Methods for decoding information stored on a memory may include performing a hard read at an initial threshold and determining a first distribution percentage, performing a hard read at a subsequent threshold and determining a second distribution percentage, generating a log-likelihood ratio (LLR) based on the hard reads performed at the initial and subsequent thresholds, and based on the first and second distribution percentages, and soft decoding the information based on the generated LLR.

Abstract: In a network storage device that includes a plurality of data storage drives, error correction and/or recovery of data stored on one of the plurality of data storage drives is performed cooperatively by the drive itself and by a storage host that is configured to manage storage in the plurality of data storage drives. When an error-correcting code (ECC) operation performed by the drive cannot correct corrupted data stored on the drive, the storage host can attempt to correct the corrupted data based on parity and user data stored on the remaining data storage drives. In some embodiments, data correction can be performed iteratively between the drive and the storage host. Furthermore, the storage host can control latency associated with error correction by selecting a particular error correction process.

Abstract: A method and apparatus of a device that updates rules for a plurality of entities in a simulation as the simulation is running is described. In an exemplary embodiment, the device receives configuration parameters for the simulation, where the configuration parameters include a plurality of rules that control the interactions of the plurality of entities in the simulation. In addition, the device performs the simulation for a first plurality of iterations. Furthermore, the device analyzes the simulation results to determine if there is an update for the plurality of rules. If there is an update for the plurality of rules, the device creates the rule update for the plurality of rules. The device additionally applies the rule update to the plurality of rules.

Abstract: The invention pertains to semiconductor memories, and more particularly to enhancing the reliability of stacked memory devices. Apparatuses and methods are described for implementing RAID-style error correction to increase the reliability of the stacked memory devices.

Abstract: A method begins by detecting a recovery error when decoding a seemingly valid threshold number of existing encoded data slice. The method continues by sending a notice of the recovery error and a known integrity check value for the data segment to a rebuild module. The method continues by the rebuild module retrieving the set of existing encoded data slices and selectively decoding a different combination of a decode threshold number of existing encoded data slices of the set of existing encoded data slices until the data segment is successfully recovered. The method continues by dispersed storage error encoding the successfully recovered data segment to produce a set of new encoded data slices. The method continues by comparing the seemingly valid encoded data slices with corresponding new encoded data slices on an encoded data slice by encoded data slice basis to identify a corrupted encoded data slice.