Abstract: A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.

Abstract: A fault handling apparatus and a fault handling method which perform a built-in self-test (BIST) and a repair on a static random-access memory (SRAM) cell, and the fault handling apparatus and the fault handling method store the fault and repair history information of a previous SRAM test, provide the information to a current test, and reflect both BIST results and the information on the previous test, thereby performing multiple repairs until there is no available spare SRAM.

Abstract: A first BLUETOOTH device includes a transceiver configured to receive a control procedure packet from a second BLUETOOTH device during a BLUETOOTH connection event of a BLUETOOTH connection between the first BLUETOOTH device and the second BLUETOOTH device. The first BLUETOOTH device also includes a controller coupled to the transceiver and configured to set a more data (MD) bit of a response packet to the control procedure packet to a first value independent of whether the first BLUETOOTH device has more data to send to the second BLUETOOTH device. The first value corresponds to maintaining the BLUETOOTH connection event open. The transceiver is further configured to send the response packet to the second BLUETOOTH device during the BLUETOOTH connection event.

Abstract: A memory system connectable to a host, includes a non-volatile memory including a plurality of memory cell transistors and a controller configured to execute read operations on the non-volatile memory. The controller executes one or more first read operations on the non-volatile memory to obtain read data using read voltages that are determined from one of a plurality of entries stored in a shift table, and performs error correction on the read data, until the error correction is successful, and when the error correction on the read data is successful, records an index corresponding to the entry stored in the shift table that was used in obtaining the successfully error-corrected read data. The controller executes a second read operation on the non-volatile memory to obtain read data using read voltages that are determined from the entry stored in the shift table corresponding to the recorded index.

Abstract: Various embodiments set forth techniques for erasure coding of replicated data blocks. The techniques include receiving, by a pre-designated node, data associated with an erasure coded strip from a first node; receiving, by the pre-designated node, a replica for a first data block; saving the replica in an erasure coded strip; and in response to a trigger condition, replacing, by the pre-designated node, the replica and at least one replica of a second data block with an error correction block.

Abstract: Systems and methods are provided for storing data blocks in distributed storage. One example computer-implemented method includes, in response to receipt of a data block comprising data, generating a value N for the data block, wherein the value N includes a variable integer greater than one and dividing the data block into N segments, wherein each segment includes a portion of the data. The method also includes generating a value M for the data block, wherein the value M includes a variable integer greater than or equal to one, and adding M segments of chaff to the N segments. The method then includes encrypting the N segments and the M segments of chaff and distributing the M segments and the N segments in distributed storage, wherein the N segments and the M segments of chaff are stored in multiple different storage devices included in the distributed storage.

Abstract: A technique involves, in response to encountering a predefined number of consecutive I/O errors using a drive path to a storage drive, transitioning the drive path from online to quarantined to temporarily deny further I/O operations from being processed using the drive path. The technique further involves starting a quarantine timer that defines a quarantine time period. The technique further involves performing an update operation that updates the drive path. The update operation (i) changes the drive path from quarantined to removed to continue denying further I/O operations from being processed using the drive path when a removal notification is received before the quarantine time period expires, and (ii) changes the drive path from quarantined to back to online to allow further I/O operations to be processed using the drive path when a removal notification is not received before the quarantine time period expires.

Abstract: A method includes determining whether an encoded data slice (EDS) of an “x” number of EDSs associated with a set of EDSs requires rebuilding, where the “x” number of EDSs is stored in a set of storage units of the storage network and the encoded data slice is stored in a first storage unit of the set of storage units. When the encoded data slice requires rebuilding, the method continues by identifying one of a “z” number of EDSs to replace the encoded data slice, where the “z” number of EDSs are not currently stored in the set of storage units. The method continues by constructing the one of the “z” number of EDSs from a decode threshold number of EDSs of the “x” number of EDSs and sending the one of the “z” number of EDSs to a second storage unit of the set of storage units.

Abstract: A storage device may include a memory device and a memory controller. The memory device may include a plurality of data blocks, a plurality of replacement blocks to replace bad blocks, and a system block configured to store default system information. The memory controller may store, based on a result of comparing a lifetime of the memory device with a reference value, update system information corresponding to an update of the default system information, in a selected replacement block among the plurality of replacement blocks. The memory controller may control the memory device to set the selected replacement block as a target system block. The default system information may include one or more parameters corresponding to at least one operation among a read operation, a program operation, and an erase operation of the memory device.

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

Abstract: A memory which includes a downlink error correction circuit suitable for correcting an error in data transferred from a memory controller based on a downlink error correction code transferred from the memory controller to produce an error-corrected data so that when an uncorrectable error is detected in the downlink error correction circuit of the memory or when an uncorrectable error is detected in the memory error correction circuit of the memory, the information that there is an uncorrectable error may be transferred to the memory controller in the memory system by using an uncorrectable error signal and an error flag signal, thus, improving the reliability of the memory system.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller comprises an XOR module, an ECC module, a scrambler, an encoder, and comparison logic. The controller is configured to retrieve data from the memory device, decode the retrieved data, execute XOR protection logic on the decoded data, encode the decoded data, and compare the encoded data to the retrieved data stored in the memory device.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to poison data based on an indication provided by a host device coupled with the memory devices. The indication may include which one or more bits to poison (invert) at which stages of performing write or read operations. In some embodiments, the memory device may invert one or more bits according to the indication and then correct one or more errors associated with inverting the one or more bit to verify its on-die ECC functionality. In some embodiments, the memory device may provide the host device with poisoned data including one or more bits inverted according to the indication such that the host device may test system-level ECC functionality using the poisoned data.

Abstract: A data access system includes a flash memory, a first inversion circuit, a block buffer memory, an error checking and correcting circuit, a second inversion circuit, and an application circuit. The first inversion circuit inverts a plurality of pieces of data stored in a block of the flash memory to generate a plurality of pieces of inverted data. The block buffer memory stores the plurality of pieces of inverted data. When the ECC circuit determines that the plurality of pieces of inverted data are correctable, the ECC circuit corrects at least one piece of inverted data stored in the block buffer memory. The second inversion circuit inverts the plurality of pieces of inverted data stored in the block buffer memory to generate a plurality of pieces of recovered data. The application circuit receives the plurality of pieces of recovered data and performs a corresponding operation accordingly.

Abstract: Systems and methods are provided for storing data blocks in distributed storage. One exemplary computer-implemented method includes, in response to receipt of a data block comprising data, generating a value N for the data block, wherein the value N includes a variable integer greater than one and dividing the data block into N segments, wherein each segment includes a portion of the data. The method also includes generating a value M for the data block, wherein the value M includes a variable integer greater than or equal to one, and adding M segments of chaff to the N segments. The method then includes encrypting the N segments and the M segments of chaff and distributing the M segments and the N segments in distributed storage, wherein the N segments and the M segments of chaff are stored in multiple different storage devices included in the distributed storage.

Abstract: A memory component comprises a cyclic buffer partition portion and a snapshot partition portion. In response to receiving a signal that a trigger event has occurred, a processing device included in the memory component performs an error correction operation on a portion of data stored in the cyclic buffer partition portion, copies the data stored in the cyclic buffer partition portion to the snapshot partition portion in response to the error correction operation being successful, and sends the data stored in the cyclic buffer partition portion to a processing device operatively coupled to the memory component in response to the error correction operation not being successful.

Abstract: Runtime memory cell row defect detection and replacement includes detecting in a memory of a computer system operating in a runtime operating system mode, a defective row of memory cells having at least one defective cell. In response to the detection of the defective row, interrupting the operating system of the computer system and, in a runtime system maintenance mode, replacing the defective row of memory cells with a spare row of memory cells as a replacement row of memory cells. Execution of the operating system is then resumed in the runtime operating system mode Other aspects and advantages are described.

Abstract: Systems, methods and apparatus to implement bipolar read retry. In response to a determination that a first result of reading a set of memory cells using a first magnitude of read voltage is erroneous, a second magnitude of read voltage, greater than the first magnitude, is identified for the bipolar read retry. In the retry, a controller uses voltage drivers to apply, to the set of memory cells, first voltages of the second magnitude in a first polarity to obtain a second result of reading the set of memory cells and, after the second result is generated and in parallel with decoding the second result, apply second voltages of the second magnitude in a second polarity, opposite to the first polarity.

Abstract: An example apparatus includes a memory device having first sensing circuitry positioned adjacent an edge of an edge array section and selectably coupled to a row memory cells, the first sensing circuitry including a first sense amplifier selectably coupled via a first sense line to a first memory cell in the row and via a second sense line to the first memory cell. The example apparatus includes second sensing circuitry positioned at an opposite edge of the edge array section and selectably coupled to the row via a third sense line, the second sensing circuitry including a second sense amplifier selectably coupled via the third sense line to a second memory cell in the row. The example apparatus further includes a component positioned outside the edge array section and proximate the first sensing circuitry, the component configured to perform an operation based on data sensed by the first sensing circuitry.

Abstract: A memory controller accesses a memory page in a memory block of a storage memory array of a memory device. The memory controller reads memory data stored in the accessed memory page. The memory controller determines a number of error bits associated with the memory data. The memory controller obtains an erase count corresponding to the accessed memory page, the erase count indicating a number of erase operations performed on the accessed memory page. The memory controller determines, from among one or more error threshold values, an error threshold value based at least on the erase count. The memory controller determines a relationship between the number of error bits and the error threshold value. The memory controller triggers a data refresh for the accessed memory block if the relationship between the number of error bits and the error threshold value satisfy a known criterion.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving a set of read offsets for a block of the memory device, the set of read offsets comprising a default read offset, selecting the default read offset from the set of read offsets based on one or more criteria, applying the default read offset to a read operation performed with respect to the block, determining that a second set of criteria associated with removing the default read offset is satisfied, and removing the default read offset responsive to determining that the second set of criteria is satisfied.

Abstract: According to one general aspect, an apparatus may include a regeneration-code-aware (RCA) storage device configured to calculate at least one type of data regeneration code for data error correction. The RCA storage device may include a memory configured to store data in chunks which, in turn, comprise data blocks. The RCA storage device may include a processor configured to compute, when requested by an external host device, a data regeneration code based upon a selected number of data blocks. The RCA storage device may include an external interface configured to transmit the data regeneration code to the external host device.

Abstract: Methods, systems, and devices for read threshold adjustment techniques for memory are described. A memory device may read a codeword from a memory array of the memory device using a read threshold having a first value. The memory device may increment one or more counters of the memory device based on reading the codeword. The counter may indicate a quantity of bits of the codeword that correspond to a first logic value. The memory device may detect an error, such as an uncorrectable error, in the codeword based on reading the codeword. The memory device may adjust the read threshold from the first value to the second value based on the quantity of bits indicated by the counter. The memory device may read the codeword using the read threshold having the second value.

Abstract: A memory includes: a memory core including sequentially disposed N data cell regions and an ECC cell region respectively suitable for storing N data pieces of K bits and a corresponding ECC of M bits; and an error correction circuitry suitable for generating the ECC based on the data pieces and error-correcting the data pieces based on the ECC, through a check matrix configured by a message part of a [M×(K*N)] bit-dimension and an ECC part of a [M×M] bit-dimension, wherein the message part includes N characteristic indicator groups of a [M/2×K] bit-dimension, respectively corresponding to the data pieces, and each including K indicators of a [M/2×1] bit-dimension and having the same value, and wherein a hamming distance between the indicators respectively corresponding to the data pieces stored in neighboring ones among the data cell regions is 1 or M/2.

Abstract: A memory-testing circuit configured to perform a test of a memory comprising error-correcting code circuitry comprises repair circuitry configured to allocate a spare row or row block in the memory for a defective row or row block in the memory, a defective row or row block being a row or row block in which a memory word has a number of error bits greater than a preset number, wherein the test of the memory comprises: disabling the error-correcting code circuitry, performing a pre-repair operation, the pre-repair operation comprising: determining whether the memory has one or more defective rows or row blocks, and allocating one or more spare rows or row blocks for the one or more defective rows or row blocks if the one or more spare rows or row blocks are available, and performing a post-repair operation on the repaired memory.

Abstract: A method and apparatus for masking errors in a DRAM write are disclosed to perform a partial write request with an SSD controller. In embodiments, write data from a host is provided to the controller that is not aligned to the DRAM data. The controller issues a read command from the LBA of a data storage device, and a corresponding write command to write the data received from the host, prior to receipt of the read data, to perform a partial write. The read data is error corrected, and in the event an error is found in the read data, bytes containing an error are masked. The read data, including masked read data, and write data are merged to form partial write data, and written to the DRAM. In certain embodiments, the partial write data may be provided to a logic analyzer to assess the masked read data for debug analysis.

Abstract: A system may include multiple memory cells to store logical data, age tracking circuitry to track a time since a previous access of a particular memory cell, and control circuitry to access the memory cell. Such access may include a read operation of the memory cell, a write operation to the memory cell, or both. The control circuitry may determine an electrical parameter of the memory cell based at least in part on the tracked time since the previous access of the memory cell.

Abstract: A memory system includes a non-volatile memory including at least one memory cell, a buffer, and a memory controller. The memory controller acquires first data from the buffer. The first data includes a plurality of bits of data. The memory controller generates second data by performing a randomization process on the first data, generates a flag that is information used to identify an error suppression encoding process, based on the second data, and stores the flag in the buffer. The memory controller acquires third data and the flag from the buffer. The third data is 1-bit data of the first data. The memory controller generates storage data by performing the error suppression encoding process based on the acquired flag and the randomization process on the third data, and writes the storage data into the memory cell.

Abstract: A read method of a nonvolatile memory device is provided. The method includes storing data sensed from selected memory cells of the nonvolatile memory device into a page buffer, performing an error decoding operation by performing error detection on the sensed data to detect and error, correcting the detected error if the error is detected, and overwriting the page buffer with the corrected data, and de-randomizing data stored in the page buffer by using a seed after the error decoding operation has completed.

Abstract: Apparatuses, systems, and methods for error correction. A memory array may be coupled to an error correction code (ECC) circuit along a read bus and a write bus. The ECC circuit includes a read portion and a write portion. As part of a mask write operation, read data and read parity may be read out along the read bus to the read portion of the ECC circuit and write data may be received along data terminals by the write portion of the ECC circuit. The write portion of the ECC circuit may generate amended write data based on the write data and the read data, and may generate amended parity based on the read parity and the amended write data. The amended write data and amended parity may be written back to the memory array along the write bus.

Abstract: Methods, systems, and devices for operating a memory device are described. An error correction bit flipping scheme may include methods, systems, and devices for performing error correction of one or more bits (e.g., a flip bit) and for efficiently communicating error correction information. The data bits and the flip bit (e.g., an error corrected flip bit) may be directly transmitted (e.g., to a flip decision component). The flip bit may be transmitted to the flip decision component over a dedicated and/or unidirectional line that is different from one or more other lines that carry data bits (e.g., to the flip decision component).

Abstract: The subject technology provides for scanning blocks of a flash memory device for erased pages. A first codeword read from a page of a block in a flash memory device is received and provided to a first decoder for decoding. In response to receiving a first success indicator from the first decoder indicating that the first codeword was successfully decoded, first decoded data is provided from the first decoder to a second decoder for verification of the first decoded data. In response to receiving a first failure indicator from the second decoder indicating that the first decoded data was not verified, the page of the block is identified as being in an erased state based on the first success indicator received from the first decoder and the first failure indicator received from the second decoder.

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive metadata from an application, wherein the meta data indicates one or more processing operations which can accommodate a predetermined level of bit errors in read operations from memory, determine, from the metadata, pixel data for which error correction code bypass is acceptable, and generate one or more error correction code bypass hints for subsequent cache access to the pixel data for which error correction code bypass is acceptable, and transmit the one or more error correction code bypass hints to a graphics processing pipeline. Other embodiments are also disclosed and claimed.

Abstract: A quasi-volatile memory (QV memory) stack includes at least one semiconductor die, having formed thereon QV memory circuits, bonded to a second semiconductor on which a memory controller for the QV memory (“QV memory controller”) is formed. The circuits in the bonded semiconductor dies are electrically connected using numerous copper interconnect conductors and conductive through-silicon vias (TSVs). The QV memory controller may include one or more interfaces to additional devices (“back-channel devices”) to enable the QV memory controller to also serve as a controller for each back-channel device and to provide additional services. The QV memory controller performs data transfers between a back-channel device and the QV memory without intervention by the host CPU.

Abstract: Provided herein is a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes: a memory cell array including a plurality of word lines; a peripheral circuit coupled to the memory cell array through the plurality of word lines and configured to apply a program voltage to a selected word line of the plurality of word lines during a program operation and apply a pass voltage to unselected word lines of the plurality of word lines; and control logic configured to control the peripheral circuit to apply a first pass voltage to word lines adjacent to the selected word line among the unselected word lines during a first program operation of the program operation and apply a second pass voltage to the word lines adjacent to the selected word line during a second program operation of the program operation.

Abstract: Methods, systems, and devices related to error detection code generation techniques are described. A memory device may identify a first set of bits for transmission to a host device and calculate an error detection code associated with the first set of bits. Prior to transmitting the first set of bits, the memory device may modify one or more bits of the first set of bits to generate a second set of bits for transmission from the memory device to the host device. The memory device may modify one or more bits of the first error detection code to generate a second error detection code based on a parity of the modified one or more bits of the first set of bits. The memory device may transmit the second set of bits and the second error detection code to the host device.

Abstract: A memory controller performs an efficient error correction operation. The memory controller controls a memory device. The memory controller includes: an error corrector configured to perform one or more error correction operations to correct an error included in data read from the memory device during a read operation, the one or more error correction operations including a first error correction operation performed using a first read voltage determined based on a threshold voltage distribution obtained by assuming that a number of memory cells in an erase state is equal to a number of memory cells in a program state and a data controller in communication with the error corrector to receive first error correction data obtained from the first error correction operation and configured to store the first error correction data in the memory controller.

Abstract: Methods, systems, and devices for operating memory cell(s) using an enhanced bit flipping scheme are described. An enhanced bit flipping scheme may include methods, systems, and devices for performing error correction of data bits in a codeword concurrently with the generation of a flip bit that indicates whether data bits in a corresponding codeword are to be flipped; for refraining from performing error correction of inversion bit(s) in the codeword; and for generating a high-reliability flip bit using multiple inversion bits. For instance, a flip bit that is even more reliable may be generated by determining whether a number of, a majority of, or all of the inversion bits indicate that the data bits are in an inverted state.

Abstract: A memory device includes a memory cell array and a memory controller. The memory cell array includes a plurality of memory blocks. Each of the memory blocks includes a plurality of word lines. A plurality of memory chunks is coupled to at least one of the word lines. The memory controller is configured to program data to a particular memory chunk of the plurality of memory chunks by performing a chunk operation that includes selecting a particular word line from the plurality of word lines, selecting a particular memory chunk from the plurality of memory chunks that are coupled to the particular word line, and applying a program voltage to a particular memory block corresponding to the particular memory chunk to program data to the particular memory chunk.

Abstract: A memory device includes a memory array with at least one memory macro, a flag, and a controller. The controller is coupled to the memory array. Each bit of data stored in the at least one memory macro is presented as a first bit type or a second bit type. The controller is configured to select one of a first situation mode and a second situation mode as a selected situation mode according to a first retention time of the first bit type and a second retention time of the second bit type. The first situation mode is that a number of bits with the first bit type in data is larger than a number of bit with the second bit type in data, and the second situation mode is that the number of bit with the first bit type in data is not larger than the number of bits with the second bit type in data. In a write operation of the at least one memory macro, the controller determines that an input data is meet the selected situation mode or not.

Abstract: Localized lookups for performing access requests to a database may be implemented. Mapping information for storage nodes of a network-based service storing different data for different databases may be obtained by a routing application co-hosted with a client application of the database at a same container host. Access requests from the client application are handled by the routing application and sent to storage nodes identified using the mapping information. An authorization token may be included along with the requests to verify authorization to perform the access request at the storage nodes.

Abstract: Methods and devices are provided for error correction of distributed data in distributed systems using Reed-Solomon codes. In one embodiment, processes are provided for error correction that include receiving a first correction code for data fragments stored in storage nodes, constructing a second correction code responsive to an unavailable storage node of the storage nodes, performing erasure repair of the unavailable storage node, and outputting a corrected data fragment. The first correction code is a Reed-Solomon code represented as a polynomial and the second correction code is represented as a second polynomial with an increased subpacketization size. Processes are configured to account for repair bandwidth and sub-packetization size. Code constructions and repair schemes accommodate different sizes of evaluation points and provide a flexible tradeoff between the subpacketization size repair bandwidth of codes.

Abstract: A processing device reads data from a memory device in response to a received request and performs a first error control operation on the data based on an initial operating characteristic to correct one or more errors in the data. The processing device determines that the first error control operation based on the initial operating characteristic failed to correct the one or more errors in the data, modifies the initial operating characteristic to generate a modified operating characteristic and performs a second error control operation on the data based on the modified operating characteristic to correct the one or more errors in the data.

Abstract: A memory system includes a memory device, and a memory controller including a processor and an internal memory. A computer program including a neural network is stored in the memory system. The processor executes the computer program to extract a voltage level from each of a plurality of memory cells connected to one string select line (SSL), in which the memory cells and the SSL are included in a memory block of the memory device, provide the voltage levels as input to the neural network, and perform noise cancellation on the SSL, using the neural network, by changing at least one of the voltage levels from a first voltage level to a second voltage level. The first voltage level is classified into a first cluster of memory cells, and the second voltage level is classified into a second cluster of memory cells different from the first cluster.

Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

Abstract: A memory system includes a memory device and a controller. The controller performs multiple read operations on a target block, using a first duster of read threshold voltages. The controller generates a second duster of read threshold voltages using the first cluster when a difference between the maximum number of fail bits and the minimum number of fail bits associated with the multiple read operations exceeds a threshold. The controller splits pages in the target block into a first group of pages for the first cluster and a second group of pages for the second cluster. The controller performs additional read operations on the first group of pages using the first cluster and on the second group of pages using the second cluster.

Abstract: Methods, systems, and apparatuses related to detecting and reporting failures for a memory device are described. When a count of bit-flip errors is above a fail threshold, a memory device can report a failure. Failure reports can indicate a rate at which the memory device is accumulating errors. An offset fail threshold may be applied instead of a default fail threshold, such as a standardized or specified threshold. The offset fail threshold can be a summation of the default fail threshold and an offset determined from an initial error count determined before the memory device has accumulated errors from use.

Abstract: Provided is a controller for controlling a memory device. The controller may include a media scanner suitable for performing a media scan operation of reading a predetermined size of data from the memory device in a predetermined cycle, detecting an error of the read data, generating corrected data of the read data, and storing the corrected data in the memory device, a period calculator suitable for calculating a power-off period, and a media scan controller suitable for changing the predetermined cycle according to the power-off period.

Abstract: A method for operating a controller which controls a memory device including a plurality of memory blocks operating in multi-level cell mode or a single level cell mode includes setting some of the plurality of memory blocks operating in the multi-level cell mode, to system memory blocks in response to a power-off request from a host, setting the system memory blocks to the single level cell mode, and controlling the memory device to store system data in the system memory blocks.