Abstract: A method is disclosed for updating parity information in a RAID 6 system wherein only one parity block is read during each write operation. Both parity blocks may be updated from the new data, the data being overwritten and either of the old blocks of parity information. A method for load balancing in a RAID 6 system using this method is also disclosed.

Abstract: A method for computing and storing parity information in a RAID system includes dividing each segment in a stripe into a data block and a parity block, and storing in each parity block, parity information for a limited number of other data blocks in the stripe. A method for rebuilding data in a RAID system includes rebuilding the data from parity information and storing the rebuilt data on reserve portions of the remaining disks in the system.

Abstract: Integrated circuits with memory elements may be provided. Integrated circuits may include memory error detection circuitry that is capable of correcting single-bit errors, correcting adjacent double-bit errors, and detecting adjacent triple-bit errors. The memory error detection circuitry may include encoding circuitry that generates parity check bits interleaved among memory data bits. The memory error detection circuitry may include decoding circuitry that is used to generate output data and error signals to indicate whether a correctable soft error or an uncorrectable soft error has been detected. The output data may be written back to the memory elements if a correctable soft error is detected. The memory error detection circuitry may be operable in a pipelined or a non-pipelined mode depending on the desired application.

Abstract: Solid-state random access memory including error correction capability applied to memory arrays entering and exiting a data retention mode. Error correction coding of the data to be retained is performed upon determining that a portion of the memory is to enter data retention mode; the parity bits (i.e., bits in addition to those required for storage of the payload) are stored in available memory cells within or external to the retention domain. Upon exit from retention mode, the code words are decoded to correct any errors, and the payload data are returned to the original cells. Error correction encoding and decoding is not performed in the normal operating mode.

Abstract: A processing module encodes data using a dispersed storage error coding function to produce a set of encoded data slices and identifies storage units for storage of the set of encoded data slices. The processing module determines that a storage unit of the storage units is unavailable, where the storage unit is targeted to store an encoded data slice of the set of encoded data slices. The processing module selects a foster storage unit of the storage units for temporarily storing the encoded data slice. When the storage unit is available, the processing module transfers the encoded data slice from the foster storage unit to the storage unit.

Abstract: According to one embodiment, a controller controls writing into and reading from a storage apparatus that includes a first data-storage unit and a second data-storage unit. The second data-storage unit stores user data and parity data of the user data. The first data-storage unit stores the parity data. The controller includes a parity updating unit and a parity writing unit. When parity data is updated, the parity updating unit writes the updated parity data into the first data-storage unit. When a certain requirement is satisfied, the parity writing unit reads the parity data written in the first data-storage unit, and writes the parity data thus read into the second data-storage unit.

Abstract: A memory system and method using at least one memory device die stacked with and coupled to a logic die by interconnects, such as through silicon vias. One such logic die includes an ECC system generating error checking and correcting (“ECC) bits corresponding to write data. The write data are transmitted to the memory device dice in a packet containing a serial burst of a plurality of parallel data bits. The ECC bits are transmitted to the memory device dice using through silicon vias that are different from the vias through which data are coupled. Such a logic die could also include a data bus inversion (“DBI”) system encoding the write data using a DBI algorithm and transmitting to the memory device dice DBI bits indicating whether the write data have been inverted. The DBI bits are transmitted using through silicon vias that are shared with the ECC bits when they are unused for transferring the ECC bits.

Abstract: A method includes, after data is stored at a data area of a memory device and error correction code (ECC) data corresponding to the data is stored at an ECC area corresponding to the data area, detecting a triggering condition. In response to detecting the triggering condition, the method also includes storing second ECC data in the ECC area, where the second ECC data includes redundant information for a first portion of the data area and storing third ECC data at the memory device. The third ECC data includes redundant information for a second portion of the data area.

Abstract: A method includes initiating a compression operation to compress data to be stored in a group of storage elements at a memory device that includes an error correction coding (ECC) engine. The method includes selecting one of a first mode of the ECC engine to generate a first number of parity bits and a second mode of the ECC engine to generate a second number of parity bits based on an extent of compression of the data. The method also includes encoding the compressed data to generate parity bits corresponding to the compressed data and storing the compressed data and the parity bits to the group of storage elements according to a page format that includes a data portion and a parity portion. The compressed data is stored in the data portion and at least some of the parity bits are stored in the parity portion.

Abstract: A flexible and relatively hardware efficient LDPC encoder is described. The encoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the encoding process. Each command of a relatively simple microcode used to describe the code structure can be stored and executed multiple times to complete the encoding of a codeword. Different codeword lengths can be supported using the same set of microcode instructions but with the code being implemented a different number of times depending on the lifting factor selected to be used. The LDPC encoder can switch between encoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor used to control the encoding processes. When coding codewords shorter than the maximum supported codeword length some block storage locations and/or registers may go unused.

Abstract: A method begins by a distributed storage (DS) processing module retrieving a data slice from a local memory and performing a partial task on the data slice. When the performing of the partial task is complete, the method continues with the DS processing module determining whether at least a retrieval number of slices of a set of slices of a data segment that includes the data slice is available from a set of DST execution units. When the at least a retrieval number of slices is available, the method continues with the DS processing module deleting the data slice from the local memory. When the at least a retrieval number of slices of the set of slices is not available, the method continues with the DS processing module determining whether execution of a task on the data segment is complete and deleting the data slice when the execution is complete.

Abstract: A system and a method for restoring damaged data programmed on a memory, such as a Flash memory, including detecting a failure of a memory controller to successfully decode encoded data using a first decoding algorithm, performing soft sampling of the encoded data to provide soft samples of the encoded data, applying, for example, by a computer coupled to the memory controller, a second decoding algorithm on the soft samples of the encoded data. The second decoding algorithm may have an error correction capability exceeding an error correction capability of the first decoding algorithm.

Abstract: A method performed by an I/O unit connected to another I/O unit in a network device. The method includes receiving a packet; segmenting the packet into a group of data blocks; storing the group of data blocks in a data memory; generating data protection information for a data block of the group of data blocks; creating a control block for the data block; storing, in a control memory, a group of data items for the control block, the group of data items including information associated with a location, of the data block, within the data memory and the data protection information for the data block; performing a data integrity check on the data block, using the data protection information, to determine whether the data block contains a data error; and outputting the data block when the data integrity check indicates that the data block does not contain a data error.

Abstract: A storage control apparatus receives a write request for a storage apparatus. When the storage control apparatus receives the write request, the storage control apparatus duplicates into a specific storage area, data stored in a storage area of the storage apparatus and parity data whose generation source is the data. The storage control apparatus determines whether one of the storage apparatuses is started up for which a writing process is executed in response to the write request. When the storage apparatus is re-started, the storage control apparatus writes the data duplicated in the specific storage area into the storage area of the duplication source of the storage apparatus and writes the parity data duplicated in the specific storage area into the storage area of the duplication source of the storage apparatus.

Abstract: An exemplary method for accessing a flash memory. The method comprising obtaining a first random sequence; utilizing the first random sequence as a first seed for generating a second random sequence, wherein the first random sequence is not equivalent to the second random sequence; scrambling data according to the second random sequence for generating scrambled data; performing an error correction encoding operation upon the first random sequence and the scrambled data for generating parity check code; and storing the scrambled data and the parity check code to the flash memory.

Abstract: To provide a memory array for information bit that stores information bits, a memory array for check bit that stores check bits, a correction circuit that, in response to a write request, reads the information bit and the check bit corresponding to a write address from the respective memory arrays and corrects an error included in the information bit, and a mixer temporarily holding information bit corrected by the correction circuit. The mixer overwrites only a part of bytes of the held information bits with write data according to a byte mask signal. Accordingly, a capacity required for the memory array for check bit can be reduced while the byte mask function is maintained.

Abstract: Provided is an operation method which can be applied to a PRAM, an ReRAM, and a solid electrolyte memory which stores error correction codes, each of which comprises of symbols, each of which comprises bits, and which codes allow error correction in units of symbols. In the operation method, the respective symbols are read by using different reference cells 12. When a correctable error is detected in read data from data cells forming the error correction codes and corresponding to an input address, a data in a data cell corresponding to the error bit is corrected for a first error symbol of an one bit error pattern, and data in a reference cell that is used to read the second error symbol are corrected for a second error symbol related to a multi-bit error pattern.

Abstract: A method of performing forward error correction with configurable latency, where a configurable latency algorithm evaluates a target Bit Error Rate (BER) against an actual BER and adjusts the size of a configurable buffer such that the target BER may be achieved when utilizing the smallest buffer size possible. When errors are corrected without the utilization of each of the configurable buffer locations, the algorithm reduces the size of the buffer by y buffer locations; the algorithm may continue to successively reduce the size of said buffer until the minimum number of buffer locations are utilized to achieve the target BER. If the buffer locations have been reduced such that the buffer size is too small and the target BER cannot be achieved, the algorithm may increase the size of the buffer until the minimum number of buffer locations are utilized to achieve the target BER.

Abstract: A system including a first plurality of memory cells to store data, and a memory controller to read the first plurality of memory cells and to identify one or more of the first plurality of memory cells in response to the one or more of the first plurality of memory cells being defective. A second plurality of memory cells stores information regarding locations of the one or more of the first plurality of memory cells. The second plurality of memory cells stores the information at a lower density than the first plurality of memory cells. The information read from the second plurality of memory cells has a lower probability of error than the data read from the first plurality of memory cells.

Abstract: Methods, apparatuses, systems, and architectures for providing fast, independent, and reliable retrieval of system data (e.g., metadata) from a storage system, which enables minimal degradation in the reliability of user data. Methods generally include encoding the system data at least twice, at least once independently and at least once jointly along with user data. Methods can also include decoding the system data first, and upon a decoding failure, jointly decoding the system data and the user data.

Abstract: A bit error corrector includes an aging bit pattern memory operable to store at least one aging bit pattern which conveys aging-related effects within a succession of uncorrected bit patterns, a bit pattern modifier operable to modify a current, uncorrected bit pattern using the at least one aging bit pattern and generate a modified bit pattern, and a bit pattern comparator operable to compare the current uncorrected bit pattern with a corrected bit pattern which is based on the modified bit pattern and determine a corresponding comparative bit pattern. An aging bit pattern determiner is operable to recursively determine a new aging bit pattern based on the at least one aging bit pattern and the comparative bit pattern, and store the new aging bit pattern in the aging bit pattern memory for use during modification of a subsequent uncorrected bit pattern by the bit pattern modifier.

Abstract: Methods, systems, and apparatus, including computer program products, featuring generating a plurality of error-correcting code chunks from a plurality of data chunks. The error-correcting code chunks can be used to reconstruct one or more of the data chunks. The data chunks are allocated to a local group of storage nodes. The error correcting code chunks are allocated between the local group of storage nodes and one or more remote groups of storage nodes. Each remote group of storage nodes is allocated one or more unique error-correcting code chunks from the error-correcting code chunks. Any of the error-correcting code chunks not allocated to a remote group of storage nodes are allocated to the local group of storage nodes.

Abstract: A method for data storage includes, in a memory that includes multiple memory blocks, specifying at a first time a first over-provisioning overhead, and storing data in the memory while retaining in the memory blocks memory areas, which do not hold valid data and whose aggregated size is at least commensurate with the specified first over-provisioning overhead. Portions of the data from one or more previously-programmed memory blocks containing one or more of the retained memory areas are compacted. At a second time subsequent to the first time, a second over-provisioning overhead, different from the first over-provisioning overhead, is specified, and data storage and data portion compaction is continued while complying with the second over-provisioning overhead.

Abstract: The present invention relates to a data processing device and a data processing method capable of improving the resistance to data error. In a case where an LDPC code having a code length of 4,320 bits is mapped into 16 signal points, when a code bit of 4×2 bits and the (#i+1)-th bit from the most significant bit of symbol bits of 4×2 bits of two consecutive symbols are bits b#i and y#i, a demultiplexer performs an interchange process in which b0 is allocated to y0, b1 is allocated to y4, b2 is allocated to y1, b3 is allocated to y6, b4 is allocated to y2, b5 is allocated to y5, b6 is allocated to y3, and b7 is allocated to y7 for an LDPC code having a coded rate of 1/2, and b0 is allocated to y0, b1 is allocated to y4, b2 is allocated to y5, b3 is allocated to y2, b4 is allocated to y1, b5 is allocated to y6, b6 is allocated to y3, and b7 is allocated to y7 for an LDPC code having a coded rate of 7/12, 2/3, and 3/4.

Abstract: An ECC controller comprises an ECC encoder, an ECC divider, an ECC constructor and an ECC decoder. The ECC encoder is configured to generate ECC data with different lengths in response to information data to be stored into a flash memory. The ECC divider is configured to divide each ECC datum generated by the ECC encoder into one or more ECC segments according to the length of the ECC datum. The ECC constructor is configured to generate an ECC datum by combining one or more ECC segments for each information datum read from the flash memory. The ECC decoder is configured to correct the errors of the information data read from the flash memory device by using the ECC data generated by the ECC constructor.

Abstract: For facilitating data verification using a checksum in conjunction with a sidefile by a processor device in a computing environment, first block signatures having a first size are calculated for first blocks of a first volume stored on a storage device. The first block signatures are stored to a sidefile. Second block signatures having a second size different from the first size are calculated for second blocks of a second volume stored on the storage device. The second block signatures are stored to the sidefile.

Abstract: For facilitating data verification using a checksum in conjunction with a sidefile by a processor device in a computing environment, first block signatures having a first size are calculated for first blocks of a first volume stored on a storage device. The first block signatures are stored to a sidefile. Second block signatures having a second size different from the first size are calculated for second blocks of a second volume stored on the storage device. The second block signatures are stored to the sidefile.

Abstract: Apparatus and methods for generating checksums may process two or more segments of a message in parallel, and may be used with a communications channel having time slots. An apparatus may include a cumulative checksum generator to generate a cumulative checksum for a message, a partial checksum generator to generate one or more partial checksums from one or more respective message segments, and a speculative checksum generator to generate a speculative checksum for each of one or more time slots. In one aspect, a partial checksum corresponding with an initial segment of the message may be generated from at least an initialization vector. A speculative checksum selector may select a first speculative checksum for use in determining whether the message was transmitted without error. The generating of partial and speculative checksums results in a maximally pipe-lined architecture with speed limited only by a minimal cumulative CRC calculation that is fundamentally unavoidable.

Abstract: Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.

Abstract: Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error.

Abstract: A flash memory solid-state-drive (SSD) has a smart storage switch that reduces write acceleration that occurs when more data is written to flash memory than is received from the host. Page mapping rather than block mapping reduces write acceleration. Host commands are loaded into a Logical-Block-Address (LBA) range FIFO. Entries are sub-divided and portions invalidated when a new command overlaps an older command in the FIFO. Host data is aligned to page boundaries with pre- and post-fetched data filling in to the boundaries. Repeated data patterns are detected and encoded by compressed meta-data codes that are stored in meta-pattern entries in a meta-pattern cache of a meta-pattern flash block. The sector data is not written to flash. The meta-pattern entries are located using a meta-data mapping table. Storing host CRC's for comparison to incoming host data can detect identical data writes that can be skipped, avoiding a write to flash.

Abstract: An aliasing module is defined and connected to receive a first bit stream to be transmitted over a data bus from a memory to an external controller of the memory. The aliasing module is defined and connected to alias the first bit stream as a second bit stream and transmit the second bit stream over the data bus in lieu of the first bit stream. A de-aliasing module is defined and connected to receive the second bit stream from the data bus at the external controller. The de-aliasing module is defined and connected to de-alias the received second bit stream back to the first bit stream and provide the first bit stream to the external controller for processing.

Abstract: According to an embodiment, a programmable logic device includes a plurality of logic blocks, memory and a logic unit. The logic blocks are grouped into one or more partitions. The memory stores authentication and partition information uploaded to the programmable logic device prior to partition programming. The logic unit authenticates programming access to the one or more partitions based on the authentication information and controls programming of the one or more partitions based on the partition information.

Abstract: A data storage system includes a memory circuit and a control circuit. The control circuit is operable to receive data bits provided for storage in memory cells of the memory circuit. The control circuit is operable to compare each of the data bits provided for storage in a corresponding one of the memory cells having a stuck-at fault to a value of the stuck-at fault, and to invert each of the data bits having a different value than the value of the stuck-at fault of the corresponding one of the memory cells to generate encoded data bits. The control circuit is operable to generate redundant bits that indicate the encoded data bits to invert to regenerate the data bits.

Abstract: A data storage system includes a memory circuit and a control circuit. The control circuit is operable to receive data bits provided for storage in memory cells of the memory circuit. The control circuit is operable to compare each of the data bits provided for storage in a corresponding one of the memory cells having a stuck-at fault value to the stuck-at fault value. The control circuit is operable to generate encoded data bits by inverting each of the data bits having a different value than the stuck-at fault value of the corresponding one of the memory cells and by maintaining a digital value of each of the data bits having the stuck-at fault value of the corresponding one of the memory cells. The control circuit is operable to prevent any of the data bits from being stored in the memory cells determined to have unstable values. The control circuit is operable to generate redundant bits that indicate at least one operation to perform on the encoded data bits to regenerate the data bits.

Abstract: Methods of writing data to and reading data from memory devices and systems for writing and reading data are disclosed. In a particular embodiment, a method includes writing data bits a first time into a memory. Auxiliary parity bits are written in the memory, where the auxiliary parity bits are computed based on the data bits. Subsequent to writing the data bits a first time and writing the auxiliary parity bits, the data bits are written a second time into the memory. Writing the data bits the first time and writing the data bits the second time are directed to one or more storage elements at a common physical address in the memory. Subsequent to writing the data bits the second time, the auxiliary parity bits are discarded while maintaining the data bits in the memory.

Abstract: A block management method for managing physical blocks of a rewritable non-volatile memory module, and a memory controller and a memory storage device using the same are provided. The method includes maintaining an error information table for recording one or more error correctable physical blocks among the physical blocks and an error bit number corresponding to the one or more error correctable physical blocks. The method further includes selecting a physical block for writing data according to the one or more error correctable physical blocks and the error bit number thereof recorded in the error information table. Accordingly, the data stability of the memory storage device can be improved.

Abstract: A storage system with a data recovery function and its method reduce errors in a storage medium to a recoverable range of a general ECC function by repeating a testing and recovery procedure for one or more times to assure the accuracy of reading data and enhance the data reliability effectively. The data recovery procedure includes the steps of providing test data by a test data generator of the storage system, writing the test data into a memory block where error data is found, finding an error bit by reading the test data, reducing the error to a recoverable range of the ECC technique by the recovery procedure. If the error bit cannot be found or reduced to a recoverable range of the ECC technique within an upper limit of the number of tests, the memory block is marked as bad.

Abstract: A method for transmitting a data transfer block, the data transfer block comprising at least one data segment having a predetermined number of one or more data units, to be identified using validity information, and a header segment, the method including the following steps: a) writing a data unit into a first area of an output register predetermined for the data segment, from which the buffered data transfer block is transmitted via a bus system at a predetermined transmission instant with the aid of a time multiplexing method; b) writing a validity datum, implemented as a toggle bit or as an N-bit counter, into a second area of the output register predetermined for the header segment, the particular validity datum specifying the validity of the corresponding written data unit; c) enabling the data transfer block buffered in the output register for transmission, after the particular data unit and the corresponding validity datum are written into the output register; d) repeating steps (a) through (c) until t

Abstract: Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with extended error correction protection. In some embodiments, a parity cache is used to store parity values of data values stored in a plurality of codewords of an NVM device. Other embodiments may be described and claimed.

Abstract: An approach is provided for processing structure Low Density Parity Check (LDPC) codes. Memory storing edge information and a posteriori probability information associated with a structured parity check matrix used to generate Low Density Parity Check (LDPC) coded signal are accessed. The edge information represent relationship between bit nodes and check nodes, and are stored according to a predetermined scheme that permits concurrent retrieval of a set of the edge information.

Abstract: Embodiments of circuits and method for dual redundant register files with error detection and correction mechanisms are described herein. Other embodiments and related examples are also described herein.

Abstract: A memory system including a primary memory storage partition, a secondary memory storage partition, and a memory controller that is connected to read and write to the primary memory storage partition and detect a permanent bit error at an address associated with the primary memory storage partition. In response to a detected permanent bit error, the memory controller stores data from the address associated with the permanent bit error to an address associated with the secondary memory storage partition.

Abstract: A semiconductor recording device includes: flash memories including a plurality of physical blocks each including a plurality of pages; an external interface unit which receives data to be recorded on the flash memories; a first ECC generation unit which generates a first ECC code by adding parity data to the data; a data writing unit which records the data based on the first ECC code into the pages in the flash memories; and a page shuffling unit which controls assignment of a symbol of the first ECC code to the pages, and the page shuffling unit controls the assignment of the symbol of the first ECC code such that the symbol of the first ECC code is assigned to pages having at least two page numbers in the physical blocks included in a group.

Abstract: Erasure-encoded data is stored across a plurality of storage devices in a data storage system. The erasure-encoded data includes k data elements to store on k data storage devices and m parity elements to store on m parity storage devices, wherein for a given minimum Hamming distance d of the data storage system and m?(d?1), data elements are assigned only to corresponding unique combinations of parity elements of size (d?1).

Abstract: To provide a memory array for information bit that stores information bits, a memory array for check bit that stores check bits, a correction circuit that, in response to a write request, reads the information bit and the check bit corresponding to a write address from the respective memory arrays and corrects an error included in the information bit, and a mixer temporarily holding information bit corrected by the correction circuit. The mixer overwrites only a part of bytes of the held information bits with write data according to a byte mask signal. Accordingly, a capacity required for the memory array for check bit can be reduced while the byte mask function is maintained.

Abstract: The invention is directed to a method and apparatus for decoding encoded data symbols. The invention is also directed to corresponding encoding methods. The decoder arrangement comprises an input for receiving encoded data and an identifier associated with a coding scheme used to create said encoded data. A processor in the decoding arrangement determines from the identifier, a mapping between said encoded data and the original data. A decoder uses the mapping to extract the original data from the encoded data. The operation of the decoder is independent of the coding scheme used in the encoding process.

Abstract: A method of reading and correcting data within a memory device that includes reading each data bit of a data word using a plurality of reference cells corresponding to each data bit, performing error detection on the read data bits, and correcting a read data bit when an error is detected using error correction code (ECC) and writing each corresponding reference cells to an original memory state thereof.

Abstract: A data error measuring circuit for a semiconductor memory apparatus includes a data error correction unit that compares data with parity data to correct data, a data selection unit that outputs the data or the corrected data as selected data in response to a test selection signal, and a test result output unit that receives the selected data and the parity data to output a test result signal in response to the test selection signal.

Abstract: One or more embodiments of the invention set forth techniques to perform integer division using addition operations in order to provide address translation capabilities to a processor. The processor supports a memory that maintains checksum information such that address requests received by the processor need to be translated to a checksum address and an actual data address that accounts for use of portions of the memory to store checksum information. Once the checksum address and the actual data address are computed, the processor can confirm the integrity of the data stored in the actual data address and correct any errors if need be, based on the checksum information stored in the checksum address.