Abstract: A method, a memory controller and a processor architecture for protecting an application in a memory are disclosed. The application is cached as memory lines according to a size of a cache line. For example, the method comprises: in response to a load access request from a processor, reading from the memory a flagged memory line and an ECC checksum corresponding to the memory line, wherein the flagged memory line is obtained by performing a logic operation on a predetermined bit of the memory line and a flag bit for identifying the memory line; performing an ECC check on the flagged memory line by using the ECC checksum to obtain a value of the flag bit of the memory line; restoring the flagged memory line to the memory line according to the value of the flag bit; and determining whether or not to load the memory line according to the value of the flag bit and the type of the load access request from the processor.

Abstract: The storage system includes a first memory device configured to store data sent from a host system, a first memory device controller configured to control read/write access of the data from/to the first memory device, an arithmetic circuit unit configured to calculate parity data based on the data, a second memory device configured to store the parity data, a second memory device controller configured to control read/write access of the parity data from/to the second memory device. With this storage system, read access speed of the first memory device is faster than read access speed of the second memory device.

Abstract: A data read-out circuit is provided with a sense amplifier circuit and a selector. The sense amplifier circuit senses a stored data stored in a memory cell array by using a plurality of reference levels to generate a plurality of read data, respectively. Thus, the sense amplifier circuit outputs the plurality of read data with regard to the stored data. The selector selects a data corresponding to any one of the plurality of read data based on a control signal and outputs the selected data as an output data.

Abstract: A file server architecture decouples logical storage from physical storage and provides proactive detection and containment of faults, errors, and corruptions in a file system, in order to enable in place (online) and non-intrusive recovery. The file system is built upon a thinly provisioned logical volume, and there are stored three copies of the metadata defining the logical volume in order to provide quick, deterministic, and reliable recovery from a faulted system. A first copy of the metadata is distributed among all of the slices of physical storage allocated to the logical volume. A second copy of the metadata is stored in a root slice of the logical volume. A third copy of the metadata is stored separate from the slices of physical storage allocated to the logical volume.

Abstract: A hardware accelerator includes a first buffer, a second buffer, address generator(s), a translation read-only memory (ROM), a cyclic redundancy check (CRC) generator, a convolutional encoder and a controller. The first and second buffers store information bits. The address generator(s) generate(s) an address for accessing the first buffer, the second buffer and a shared memory architecture (SMA). The translation ROM is used in generating a translated address for accessing the first buffer and the second buffer. The controller sets parameters for the CRC generator, the convolutional encoder and the address generator, and performs a predefined sequence of control commands for channel processing, such as reordering, block coding, parity tailing, puncturing, convolutional encoding, and interleaving, on the information bits by manipulating the information bits while moving the information bits among the first buffer, the second buffer, the SMA, the CRC generator, and the convolutional encoder.

Abstract: Data is stored in a nonvolatile memory so that different pages of data stored in the same memory cells are encoded according to different encoding schemes. A first page is decoded according to its encoding scheme and an output is provided based on the decoding of the first page that is subsequently used in decoding a second page.

Abstract: To store an input string of M N-tuples of bits, a substitution transformation is selected in accordance with the input string and is applied to the input string to provide a transformed string of M N-tuples of bits. M or more memory cells are programmed to represent the transformed string and preferably also to represent a key of the transformation. Alternatively, the memory selectively programs each of M or more cells to a respective one of 2N states. A mapping that maps the binary numbers in [0,2N?1] into respective states is selected in accordance with the input string and is used to program M cells to represent the input string. Preferably, a key of the mapping is stored in the memory in association with the M cells.

Abstract: A stream including plural access units is recorded on an information recording medium. Each access unit has a first packet that includes basic data as well as a second packet which includes extension data related to the basic data. The basic data is data that is decodable in a completed state without using extension data, and the extension data is data for improving the quality of data generated from the basic data. The header of the first packet holds first information, which indicates that the first packet includes the basic data, and the header of the second packet holds second information which indicates that the second packet includes the extension data. This arrangement allows a decoder that decodes only basic data to process the access unit, which includes the basic data and the extension data.

Abstract: A semiconductor integrated circuit device includes a first memory cell coupled to a first WL and one of a pair of BLs for information bits, a second memory cell coupled to the first WL and one of a pair of BLs for parity bits, a third memory cell coupled to a second WL and the other of the pair of BLs for information bits, a fourth memory cell coupled to the second WL and the other of the pair of BLs for parity bits, column switches which connect the pair of complementary BLs for parity bits to a pair of data lines for parity bits, and a logic correction circuit connected to one of the pair of data lines for parity bits. The logic correction circuit executes a parity bit rewrite operation.

Abstract: A device, method, and computer readable medium for programming a codeword are presented. The method includes writing a first codeword portion to portions of nonvolatile memory rows, and writing a second codeword portion to portions of nonvolatile memory rows, wherein the first group of memory rows and the second group belong to non-overlapping groups. The device includes multiple nonvolatile memory rows, and a controller receiving a codeword comprising a first codeword portion and a second codeword portion. The controller writing the first codeword portion to portions of nonvolatile memory rows, and writing the second codeword portion to portions of nonvolatile memory rows, wherein the first group of nonvolatile memory rows differs and the second group of nonvolatile memory rows belong to non-overlapping groups, and the first and second groups of memory rows belong to multiple rows. A computer readable medium having stored thereon instructions performing methods described herein.

Abstract: An information recording medium reading method is provided. The information recording medium has a user data area for recording data and at Least one spare area for recording replacements for defects of the user data area. The method includes steps of sequentially reading the user data area upon a registered defect is read. searching a corresponding replacement for the registered defect in a cache buffer; reading the corresponding replacement and neighboring replacements thereof from the spare area if the corresponding replacement is failed to be found in the searching step; storing the read replacements in the cache buffer; and repeating the above steps until a reading procedure is completed. A reading apparatus, which includes the cache buffer for storing the replacements and implements the above method, is also provided.

Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

Abstract: A decoder for error correction an encoded message, such as one encoded by a turbo encoder, with reduced iterations due to an improved stopping criterion. The decoder includes an error correction loop that iteratively processes a message that is encoded prior to transmittal over a communication channel. The error correction loop generates, such as with a Reed-Solomon decoder, an error location polynomial in each iterative process. A stopping mechanism in the decoder allows an additional iteration of the message decoding based on the error location polynomial, such as by obtaining the degree of the error location polynomial and comparing it to a threshold. In one example, the threshold is the maximum number of symbol errors correctable by the Reed-Solomon code embodied in the decoder. The stopping mechanism allows additional iterations when the stopping criterion (or polynomial degree) is greater than the maximum number of symbol errors correctable by the Reed-Solomon code.

Abstract: A two-level error control protocol detects errors on the subline level and corrects errors using the codeword for the entire line. This enables a system to read small pieces of coded data and check for errors before accepting them, and in case errors are detected, the whole codeword is read for error correction.

Abstract: A method of verifying the integrity of code in a programmable memory, the method including: receiving the code from an insecure memory; generating error detection bits for the code as it is received from the insecure memory; storing the code and the error detection bits in the programmable memory; and verifying the integrity of the code stored in the programmable memory by performing an authentication check on the code and the error detection bits stored in the programmable memory.

Abstract: Systems and methods of tracking error data are disclosed. A method includes receiving a first checksum associated with error locations of a first error correction code operation and receiving a second checksum associated with error locations of a second error correction code operation. The first checksum is compared to the second checksum and an action is initiated on a region of a memory array based on a result of the comparison.

Abstract: A memory system including asymmetric high-speed differential memory interconnect includes one or more buffer units coupled to one or more memory units such as memory modules, for example, via a parallel interconnect. The memory system also includes a memory controller coupled to each of the buffer units via a respective serial interconnect. The memory controller may control data transfer between the memory controller and the one or more buffer units. During normal operation, each of the buffer units may be configured to receive data from the memory controller via the respective serial interconnect and to transmit the data to the one or more memory units via the parallel interconnect, in response to receiving command information from the memory controller. Further, the memory controller may be configured to modify a phase alignment of information transmitted from the memory controller based upon information received from the buffer units.

Abstract: In one embodiment, a memory device comprises a first partition to divide the memory device into a first segment to hold a first data block and a second segment to hold a second data block, and a codeword in a single internal word of the memory device.

Abstract: The present invention includes a memory device with a data memory and an error correction code control circuit. The data memory stores data parity information for error correction. The error correction code control circuit is configured to receive a selection signal indicative of whether an error correction mode is to be used. Power to access the portion of the memory storing the parity information is disabled when the error correction mode is enabled.

Abstract: Circuits, architectures, systems, methods, algorithms, software and firmware for indicating positions of defective data storage cells using reserved (e.g., “pilot”) cells. The circuit generally includes a memory having multiple subunits, each subunit containing multiple data storage cells and at least one reserved cell. The reserved cells store information identifying whether one or more data storage cells in a subunit are defective. The method of identifying defective memory positions generally includes determining the status of data storage cells in a multi-subunit memory; storing such status information in a reserved cell; and reading the reserved cell. In various embodiments, the reserved cells differentiate between fewer voltage levels and/or store a lower density of information than the data storage cells. The present invention improves error correction capabilities using cells that are typically already available in many conventional nonvolatile memories.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a destination indication to aid in posted write buffer loading. In some embodiments, a memory device includes a posted write buffer having a first element and a second element. The memory device may also include logic to detect a destination indication associated with received write data. In some embodiments, the logic determines whether to store the received write data in the first element or the second element based, at least in part, on the destination indication. Other embodiments are described and claimed.

Abstract: Data for a second Multi-Protocol Encapsulation-Forward Error Correcting (MPE-FEC) data frame is received while application data from a first MPE-FEC frame is undergoing error correction. The incoming data is buffered in a supplemental buffer having a size smaller than that needed for an entire MPE-FEC frame. As the supplemental buffer is filled, additional data from the second frame is stored in a buffer previously used to store error correction data for the first MPE-FEC frame. When corrected application data from the first MPE-FEC frame is transferred from an application data buffer used to hold application data undergoing correction, the second MPE-FEC frame data is transferred from the supplemental and error correction data buffers to the application data buffer. Additional data for the second frame is then placed directly into the application and error correction data buffers.

Abstract: Embodiments of the invention are generally directed to improving the reliability, availability, and serviceability of a memory device. In some embodiments, a memory device includes a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits corresponding to the data bits. The memory device may also include error correction logic on the same die as the memory core. In some embodiments, the error correction logic enables the memory device to compute ECC bits and to compare the stored ECC bits with the computed ECC bits.

Abstract: In a method for error handling in transmission of a datum over a communications system, at least two data words consisting of bits are generated for the datum in accordance with a predefined coding rule, and one of the generated data words is selected taking into consideration a running digital sum formed over the corresponding data word, and the running digital sum of the selected data word is used for the formation of a first running digital sum. The selected data word is converted into a code data word, and a bit of the data word is in each case assigned a two-bit string with two different single-bit values. The code data word and the first running digital sum are transmitted. The received code data word is examined to ascertain whether an erroneous two-bit string exists, in which case the error is corrected using the first running digital sum.

Abstract: Checking an error recognition functionality of a memory circuit including a memory that stores a datum, and a check value circuit that executes the error recognition functionality, is performed by a monitoring circuit. The memory circuit provides the datum to the check value circuit, wherein the check value circuit checks the datum provided thereto for errors and outputs an error signal if an error is present. The monitoring circuit is coupled to the check value circuit and influences the check value circuit, the memory circuit or the datum provided to the check value circuit so that the check value circuit discovers an error in a check in a case of correct execution of the error recognition functionality, and outputs an alarm signal if the check value circuit does not output an error signal upon the influence of the monitoring circuit.

Abstract: The conventional error conceal processing generates a greatly fluctuating irregular sound which is unpleasant to ears and causes a remarkable echo effect and click noise. A notification signal detection unit (301) judges processing for an input frame. In case of an error frame, a sound detection unit (303) makes judgment whether a preceding non-error data frame is a sound signal. If it is a sound frame, a sound copying unit (304) generates a replacing frame. If it is a non-sound frame, a transient signal detection unit (305) judges whether it is an attack signal by the transient signal detection and selects an appropriate area from the preceding non-error frame.

Abstract: Embodiments include a DRAM cache structure, associated circuits and method of operations suitable for use with high-speed caches. The DRAM caches do not require regular refresh of its data and hence the refresh blank-out period and refresh power are eliminated, thus improving cache availability and reducing power compared to conventional DRAM caches. Compared to existing SRAM caches, the new cache structures can potentially achieve the same (or better) speed, lower power and better tolerance to chip process variations in future process technologies.

Abstract: A method, system, and machine-readable medium for controlling access to data of a tape data storage medium are disclosed. In accordance with one embodiment, a method is provided which comprises conveying data access control metadata from a tape cartridge comprising a tape data storage medium to a host, receiving decrypted metadata from the host, comparing a checksum value determined utilizing the decrypted metadata with checksum data stored within the tape cartridge; and processing a request to access the tape data storage medium received from the host based upon a comparison of the checksum value and checksum data. In the described method embodiment, the data access control metadata comprises encrypted metadata corresponding to a data storage parameter, where data is stored within the tape data storage medium utilizing the data storage parameter and the decrypted metadata is generated by the host utilizing the encrypted metadata.

Abstract: A method secures a memory in which individually read-accessible binary words are saved. The method includes defining a memory zone covering a plurality of words, calculating a cumulative signature according to all of the words in the memory zone, and storing the cumulative signature as an expected signature of the memory zone to check the integrity of data read in the memory. The method can be applied to the securing of smart cards.

Abstract: A method and apparatus are provided for implementing enhanced vertical ECC storage in a dynamic random access memory. A dynamic random access memory (DRAM) is split into a plurality of groups. Each group resides inside a DRAM row address strobe (RAS) page so that multiple locations inside a group can be accessed without incurring an additional RAS access penalty. Each group is logically split into a plurality of segments for storing data with at least one segment for storing ECC for the data segments. For a write operation, data are written in a data segment and then ECC for the data are written in an ECC segment. For a read operation, ECC are read from an ECC segment, then data are read from the data segment.

Abstract: A mechanism for performing remote direct memory access (RDMA) operations between a first server and a second server. The apparatus includes a packet parser and a protocol engine. The packet parser processes a TCP segment within an arriving network frame, where the packet parser performs one or more speculative CRC checks according to an upper layer protocol (ULP), and where the one or more speculative CRC checks are performed concurrent with arrival of the network frame. The protocol engine is coupled to the packet parser. The protocol engine receives results of the one or more speculative CRC checks, and selectively employs the results for validation of a framed protocol data unit (FPDU) according to the ULP.

Abstract: A NAND flash memory device performing an error detecting and data reloading operation during a copy back program operation is provided. The device includes a cell array having a plurality of planes and a parity cell array having a plurality of parity planes. Each of the parity planes stores a parity of each of the planes. Additionally, the device includes a parity generating and parity column selecting circuit generating a new parity about reloaded data from an outside during a copy back program operation, and storing the new parity on a parity plane corresponding to a plane on which the reloaded data is stored.

Abstract: Embodiments of the invention are generally directed to improving the reliability, availability, and serviceability of a memory device. In some embodiments, a memory device includes a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits corresponding to the data bits. The memory device may also include error correction logic on the same die as the memory core. In some embodiments, the error correction logic enables the memory device to compute ECC bits and to compare the stored ECC bits with the computed ECC bits.

Abstract: A semiconductor memory device includes a parity generation circuit which generates a parity bit corresponding to a first number of data bits, a memory cell array including memory cells, and having first and second areas, the first area storing data, the second area storing the parity bit, a syndrome generation circuit which generates a syndrome bit for correcting an error in read data which are read from the first area, has the first number of data bits and corresponds to the parity bit read from the second area, based on the parity bit and the read data, and a parity correction circuit which corrects the parity bit generated by the parity generation circuit. The parity generation circuit generates the parity bit for data which includes input data and a part of the read data.

Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32 K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register.

Abstract: A semiconductor device includes a plurality of laser fuses and each laser fuse represents a bit of data. A first set of the plurality of laser fuses represents a unique identifier that corresponds to the semiconductor device. Also, a second set of the plurality of laser fuses represents error correction coding data that corresponds to the unique identifier. The unique identifier can be a digital rights management identification. Also, the error correction coding data is configured for use by a Reed-Solomon error correcting method to correct the unique identifier. Alternatively, the error correction coding data is configured for use by a cyclic redundancy check method.

Abstract: A method for remedying data corruption in a first circuit, which may be a CAM or a TCAM. The method includes providing a RAM circuit external to the first circuit, the RAM circuit being configured for storing error detection information for data stored in the first circuit. The method also includes scrubbing the data stored in the first circuit during scrubbing cycles of the first circuit. The scrubbing corrects stored bit patterns read from the first circuit that fail an error detection test using error detection information corresponding to individual ones of the stored bit patterns. In an embodiment, ECC may be employed for the error detection test and also to correct any single bit error found.

Abstract: A method includes storing a first data to a first portion of a storage location of a storage component of a processing device in association with a first store operation and obtaining a second data from the storage location, the second data being stored at the storage location prior to the first data. The method further includes determining whether the storage location has a bit error at second portion of the storage location different from the first portion based on the second data obtained from the storage location. The method additionally includes storing a third data to a second portion of the storage location in response to determining the storage location has a bit error at the second portion, wherein the third data is to correct the bit error.

Abstract: Techniques are disclosed for minimizing the effects of soft errors associated with memory devices that are individually accessible. By way of example, a method of organizing a column in a memory array of a memory device protected by an error correction code comprises the step of maximizing a distance of the error correction code by maximizing a physical distance between memory bits associated with a memory line within the column protected by the error correction code. Other soft error protection techniques may include use of a feed forward error correction code or use of a memory operation (e.g., read or write operation) suppress and retry approach.

Abstract: Disclosed herein is a memory device which comprises a nonvolatile memory having first and second areas and a controller that stores backup data along with checksum data alternately in the first and second areas. In the first and second areas, data storing areas and checksum areas are respectively provided. The highest bit of checksum data stored in each of the checksum areas is used as the bit based on which the latest updated side is recognized.

Abstract: An architecture and method for executing write commands in a storage array is disclosed. The data strips of the data stripes of the storage array each include a parity check bit. The parity strip of each stripe includes a plurality of parity check bits, each of which is uniquely associated with one of the data strips of the stripes. The inclusion within each data stripe of parity bits associated with each data strip and the party strip provides a method for identifying a corrupted or degraded data condition that occurs as a result of a server failing fails during a write command.

Abstract: A semiconductor having an internal memory of the present invention comprises a first memory copying and holding a data held in a storage device; a second memory holding a check code of the data held in the first memory, and being constantly supplied with a source voltage not lower than a data-holding-guarantee voltage; a data check unit detecting error in the data held by the first memory based on the check code; and reloading units copying only the data corresponded to the block having a data error detected therein by the data check unit, from the storage device to the first memory, to make it possible to detect any error in the data held in the first memory to thereby guarantee the data, and to lower the source voltage to be supplied to the first memory.

Abstract: A stored data processing apparatus includes: a format controller that adds an error correction code to data written onto a disk medium for each first block; a redundant data generation section that performs calculation for each bit position using data of all the first blocks in a second block and outputs a result of the calculation as calculation data, the second block being constituted by a plurality of the first blocks each including the error correction code added by the format controller and specified as an update target; and an MPU that writes the calculation data output from the redundant data generation section in a third block associated with the second block as the update target.

Abstract: Apparatuses and methods for utilizing error correction code in a data buffer or data storage device. In one variation, a single memory device is utilized to store both the data and the associated error correction code. The data and the associate error correction codes are stored on separate memory banks on the memory device. The error correction code may be consolidated into one or more regions on the memory device to improve the utilization of the available memory space on the memory device. In addition, by utilizing separate memory banks to store the data and the associated error correction code, the data and the error correction code can be accessed in an overlapping manner.

Abstract: Device and method for controlling caches, comprising a decoder configured to decode additional information of datasets retrievable from a memory, wherein the decoded additional information is configured to control whether particular ones of the datasets are to be stored in a cache.

Abstract: Circuit arrangement including an encoding unit having a first input for receiving an address word and a second input for receiving a data word and a check word, wherein the encoding unit outputs an alarm signal if the check word does not correspond to at least the address word or the data word.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for using the same memory type for both error check and non-error check systems. In an embodiment, a memory device is capable of operating in an error check mode and in a non-error check mode. The memory device includes an output having N error check bit paths for every M data bit paths. In one embodiment, the memory device is to transfer N error check bits with a corresponding M data bits, if the memory device is operating in an error check mode. Other embodiments are described and claimed.

Abstract: A method according to one embodiment may include operating an integrated circuit in a selected mode of operation. The integrated circuit may include first circuitry and second circuitry. The first circuitry may be capable of performing at least one operation including, at least in part, generating check data based at least in part upon other data, regenerating the other data based at least in part upon the check data, and/or determining locations of the check data and the other data in storage. The second circuitry may be capable of controlling, at least in part, at least one interface to transmit from and/or receive at the integrated circuit the check data and/or the other data. Depending at least in part upon the selected mode of operation, the first circuitry may be either enabled to perform or disabled from performing the at least one operation.

Abstract: Storage protection keys and system data share the same physical storage. The key region is dynamically relocatable by firmware. A Configuration Array is used to map the absolute address of the key region in to its physical address. The absolute address of keys can be fixed even though the physical location of the keys is relocated into a different region. A triple-detect double correct ECC scheme is used to protect keys. The ECC scheme is different from regular data in the storage and can be used to detect illegal access. Extra firmware and hardware is also designed to restrain customer's applications from directly accessing keys. With the key region being relocatable, the firmware could move the key region away from a known faulty area in a memory to improve system RAS. We also achieved the commonality objective that key memory device can use the same memory devices with other server systems that do not use keys.

Abstract: Methods and apparatus for programming a non-volatile memory array comprising addressable units are provided. The addressable units are configured to store at least a main portion and an error correction portion. An exemplary method for programming the non-volatile memory array includes, in response to a first condition, switching from an error correction enabled mode to an error correction disabled mode and programming at least the main portion of at least one addressable unit of the non-volatile memory array in the error correction disabled mode. The exemplary method further includes, in response to a second condition, switching from the error correction disabled mode to an error correction fill mode and programming at least the error correction portion of the at least one addressable unit of the non-volatile memory array in the error correction fill mode.